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Merge branch 'fix/fix_psram_mode_reg_wrong_timing_v5.0' into 'release/v5.0'

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psram: fixed mode reg read bad timing on octal and hex psrams (v5.0)

See merge request espressif/esp-idf!35954
This commit is contained in:
morris 2025-01-23 15:39:18 +08:00
commit 02e655706d
1 changed files with 4 additions and 3 deletions
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7
components/esp_psram/esp32s3/esp_psram_impl_octal.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -28,6 +28,7 @@
#define OCT_PSRAM_WR_CMD_BITLEN 16
#define OCT_PSRAM_ADDR_BITLEN 32
#define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
#define OCT_PSRAM_RD_REG_DUMMY_BITLEN (2*(5-1))
#define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
#define OCT_PSRAM_CS1_IO SPI_CS1_GPIO_NUM
#define OCT_PSRAM_VENDOR_ID 0xD
@ -113,7 +114,7 @@ static void s_init_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *mode_reg_co
int cmd_len = 16;
uint32_t addr = 0x0; //0x0 is the MR0 register
int addr_bit_len = 32;
int dummy = OCT_PSRAM_RD_DUMMY_BITLEN;
int dummy = OCT_PSRAM_RD_REG_DUMMY_BITLEN;
opi_psram_mode_reg_t mode_reg = {0};
int data_bit_len = 16;
@ -176,7 +177,7 @@ static void s_get_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *out_reg)
esp_rom_spiflash_read_mode_t mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE;
int cmd_len = 16;
int addr_bit_len = 32;
int dummy = OCT_PSRAM_RD_DUMMY_BITLEN;
int dummy = OCT_PSRAM_RD_REG_DUMMY_BITLEN;
int data_bit_len = 16;
//Read MR0~1 register