diff --git a/components/efuse/efuse_table_gen.py b/components/efuse/efuse_table_gen.py index 4cf06452ee..1253886f47 100755 --- a/components/efuse/efuse_table_gen.py +++ b/components/efuse/efuse_table_gen.py @@ -495,8 +495,7 @@ def main(): global idf_target parser = argparse.ArgumentParser(description='ESP32 eFuse Manager') - parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32', 'esp32s2', 'esp32s3', 'esp32c3', - 'esp32c2', 'esp32c6', 'esp32h2', 'esp32p4', 'esp32c5', 'esp32c61'], default='esp32') + parser.add_argument('--idf_target', '-t', help='Target chip type', default='esp32') parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true') parser.add_argument('--debug', help='Create header file with debug info', default=False, action='store_false') parser.add_argument('--info', help='Print info about range of used bits', default=False, action='store_true') diff --git a/components/efuse/esp32h4/esp_efuse_table.c b/components/efuse/esp32h4/esp_efuse_table.c index 970645c6bf..771ad91a10 100644 --- a/components/efuse/esp32h4/esp_efuse_table.c +++ b/components/efuse/esp32h4/esp_efuse_table.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table b26e7466c400977081a142076ef1a5bb +// md5_digest_table 6bfa2ae917ac6cbce5b70a55ea6a78bd // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -51,10 +51,6 @@ static const esp_efuse_desc_t WR_DIS_LOCK_KM_KEY[] = { {EFUSE_BLK0, 1, 1}, // [] wr_dis of LOCK_KM_KEY, }; -static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, -}; - static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG, }; @@ -83,14 +79,6 @@ static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT, }; -static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of HYS_EN_PAD, -}; - -static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL, -}; - static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { {EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT, }; @@ -143,10 +131,6 @@ static const esp_efuse_desc_t WR_DIS_XTS_DPA_CLK_ENABLE[] = { {EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_CLK_ENABLE, }; -static const esp_efuse_desc_t WR_DIS_ECDSA_DISABLE_P192[] = { - {EFUSE_BLK0, 14, 1}, // [] wr_dis of ECDSA_DISABLE_P192, -}; - static const esp_efuse_desc_t WR_DIS_ECC_FORCE_CONST_TIME[] = { {EFUSE_BLK0, 14, 1}, // [] wr_dis of ECC_FORCE_CONST_TIME, }; @@ -159,14 +143,6 @@ static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE, }; -static const esp_efuse_desc_t WR_DIS_XTAL_48M_SEL[] = { - {EFUSE_BLK0, 17, 1}, // [] wr_dis of XTAL_48M_SEL, -}; - -static const esp_efuse_desc_t WR_DIS_XTAL_48M_SEL_MODE[] = { - {EFUSE_BLK0, 17, 1}, // [] wr_dis of XTAL_48M_SEL_MODE, -}; - static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = { {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW, }; @@ -203,18 +179,10 @@ static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION, }; -static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { - {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE, -}; - static const esp_efuse_desc_t WR_DIS_HUK_GEN_STATE[] = { {EFUSE_BLK0, 19, 1}, // [] wr_dis of HUK_GEN_STATE, }; -static const esp_efuse_desc_t WR_DIS_BLK1[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1, -}; - static const esp_efuse_desc_t WR_DIS_MAC[] = { {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, }; @@ -223,164 +191,40 @@ static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of MAC_EXT, }; -static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR, +static const esp_efuse_desc_t WR_DIS_PVT_LIMIT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PVT_LIMIT, }; -static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR, +static const esp_efuse_desc_t WR_DIS_PVT_CELL_SELECT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PVT_CELL_SELECT, }; -static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, +static const esp_efuse_desc_t WR_DIS_PVT_PUMP_LIMIT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PVT_PUMP_LIMIT, }; -static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, +static const esp_efuse_desc_t WR_DIS_PUMP_DRV[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PUMP_DRV, }; -static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR, +static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WDT_DELAY_SEL, }; -static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR, +static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of HYS_EN_PAD, }; -static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP, +static const esp_efuse_desc_t WR_DIS_PVT_GLITCH_CHARGE_RESET[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PVT_GLITCH_CHARGE_RESET, }; -static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR, +static const esp_efuse_desc_t WR_DIS_VDD_SPI_LDO_ADJUST[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of VDD_SPI_LDO_ADJUST, }; -static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP, -}; - -static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VENDOR, -}; - -static const esp_efuse_desc_t WR_DIS_TEMP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of TEMP, -}; - -static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, -}; - -static const esp_efuse_desc_t WR_DIS_PA_TRIM_VERSION[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of PA_TRIM_VERSION, -}; - -static const esp_efuse_desc_t WR_DIS_TRIM_N_BIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of TRIM_N_BIAS, -}; - -static const esp_efuse_desc_t WR_DIS_TRIM_P_BIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of TRIM_P_BIAS, -}; - -static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, -}; - -static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_HP_DBIAS, -}; - -static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_LP_DBIAS, -}; - -static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBG[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBG, -}; - -static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBIAS, -}; - -static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBG[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBG, -}; - -static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBIAS, -}; - -static const esp_efuse_desc_t WR_DIS_LP_HP_DBIAS_VOL_GAP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LP_HP_DBIAS_VOL_GAP, -}; - -static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, -}; - -static const esp_efuse_desc_t WR_DIS_TEMPERATURE_SENSOR[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMPERATURE_SENSOR, -}; - -static const esp_efuse_desc_t WR_DIS_OCODE[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF, +static const esp_efuse_desc_t WR_DIS_FLASH_LDO_POWER_SEL[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_LDO_POWER_SEL, }; static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { @@ -423,10 +267,6 @@ static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = { {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_EXCHG_PINS, }; -static const esp_efuse_desc_t WR_DIS_VDD_SPI_AS_GPIO[] = { - {EFUSE_BLK0, 30, 1}, // [] wr_dis of VDD_SPI_AS_GPIO, -}; - static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { {EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG, }; @@ -463,204 +303,212 @@ static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2, }; -static const esp_efuse_desc_t DIS_ICACHE[] = { - {EFUSE_BLK0, 40, 1}, // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled, -}; - static const esp_efuse_desc_t DIS_USB_JTAG[] = { - {EFUSE_BLK0, 41, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 39, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 44, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 41, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = { - {EFUSE_BLK0, 45, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 42, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t DIS_TWAI[] = { - {EFUSE_BLK0, 46, 1}, // [] Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 43, 1}, // [] Represents whether TWAI function is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { - {EFUSE_BLK0, 47, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled, -}; - -static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { - {EFUSE_BLK0, 48, 3}, // [] Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even number: enabled, + {EFUSE_BLK0, 44, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled, }; static const esp_efuse_desc_t DIS_PAD_JTAG[] = { - {EFUSE_BLK0, 51, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 45, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 52, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 46, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled, }; -static const esp_efuse_desc_t USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 57, 1}, // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged, +static const esp_efuse_desc_t PVT_GLITCH_EN[] = { + {EFUSE_BLK0, 50, 1}, // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable, }; -static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { - {EFUSE_BLK0, 58, 1}, // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned, +static const esp_efuse_desc_t PVT_GLITCH_MODE[] = { + {EFUSE_BLK0, 52, 2}, // [] Use to configure glitch mode, }; -static const esp_efuse_desc_t KM_DISABLE_DEPLOY_MODE[] = { - {EFUSE_BLK0, 64, 4}, // [] Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled \\ 0: enabled., -}; - -static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE[] = { - {EFUSE_BLK0, 68, 2}, // [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles, -}; - -static const esp_efuse_desc_t KM_DEPLOY_ONLY_ONCE[] = { - {EFUSE_BLK0, 70, 4}, // [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds, -}; - -static const esp_efuse_desc_t FORCE_USE_KEY_MANAGER_KEY[] = { - {EFUSE_BLK0, 74, 4}, // [] Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds, -}; - -static const esp_efuse_desc_t FORCE_DISABLE_SW_INIT_KEY[] = { - {EFUSE_BLK0, 78, 1}, // [] Set this bit to disable software written init key; and force use efuse_init_key, -}; - -static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 80, 2}, // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16, +static const esp_efuse_desc_t DIS_CORE1[] = { + {EFUSE_BLK0, 54, 1}, // [] Represents whether the CPU-Core1 is disabled. 1: Disabled. 0: Not disable, }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 82, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}, + {EFUSE_BLK0, 55, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 85, 1}, // [] Revoke 1st secure boot key, + {EFUSE_BLK0, 58, 1}, // [] Revoke 1st secure boot key, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 86, 1}, // [] Revoke 2nd secure boot key, + {EFUSE_BLK0, 59, 1}, // [] Revoke 2nd secure boot key, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 87, 1}, // [] Revoke 3rd secure boot key, + {EFUSE_BLK0, 60, 1}, // [] Revoke 3rd secure boot key, }; static const esp_efuse_desc_t KEY_PURPOSE_0[] = { - {EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Represents the purpose of Key0, + {EFUSE_BLK0, 64, 5}, // [KEY0_PURPOSE] Represents the purpose of Key0, }; static const esp_efuse_desc_t KEY_PURPOSE_1[] = { - {EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Represents the purpose of Key1, + {EFUSE_BLK0, 69, 5}, // [KEY1_PURPOSE] Represents the purpose of Key1, }; static const esp_efuse_desc_t KEY_PURPOSE_2[] = { - {EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Represents the purpose of Key2, + {EFUSE_BLK0, 74, 5}, // [KEY2_PURPOSE] Represents the purpose of Key2, }; static const esp_efuse_desc_t KEY_PURPOSE_3[] = { - {EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Represents the purpose of Key3, + {EFUSE_BLK0, 79, 5}, // [KEY3_PURPOSE] Represents the purpose of Key3, }; static const esp_efuse_desc_t KEY_PURPOSE_4[] = { - {EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Represents the purpose of Key4, + {EFUSE_BLK0, 84, 5}, // [KEY4_PURPOSE] Represents the purpose of Key4, }; static const esp_efuse_desc_t KEY_PURPOSE_5[] = { - {EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Represents the purpose of Key5, + {EFUSE_BLK0, 89, 5}, // [KEY5_PURPOSE] Represents the purpose of Key5, }; static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { - {EFUSE_BLK0, 112, 2}, // [] Represents the spa secure level by configuring the clock random divide mode, -}; - -static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 116, 1}, // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled, -}; - -static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 117, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled, -}; - -static const esp_efuse_desc_t KM_XTS_KEY_LENGTH_256[] = { - {EFUSE_BLK0, 123, 1}, // [] Set this bitto configure flash encryption use xts-128 key. else use xts-256 key, -}; - -static const esp_efuse_desc_t FLASH_TPUW[] = { - {EFUSE_BLK0, 124, 4}, // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, -}; - -static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 128, 1}, // [] Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled, -}; - -static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 129, 1}, // [] Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: enabled, -}; - -static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 130, 1}, // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled, -}; - -static const esp_efuse_desc_t LOCK_KM_KEY[] = { - {EFUSE_BLK0, 131, 1}, // [] Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock, -}; - -static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 132, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable, -}; - -static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 133, 1}, // [] Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: disabled, -}; - -static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { - {EFUSE_BLK0, 134, 2}, // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}, -}; - -static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { - {EFUSE_BLK0, 136, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot.\\ 1: forced\\ 0:not forced, -}; - -static const esp_efuse_desc_t SECURE_VERSION[] = { - {EFUSE_BLK0, 137, 16}, // [] Represents the version used by ESP-IDF anti-rollback feature, -}; - -static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = { - {EFUSE_BLK0, 153, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled.\\ 1: disabled\\ 0: enabled, -}; - -static const esp_efuse_desc_t HYS_EN_PAD[] = { - {EFUSE_BLK0, 154, 1}, // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled, + {EFUSE_BLK0, 94, 2}, // [] Represents the spa secure level by configuring the clock random divide mode, }; static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = { - {EFUSE_BLK0, 155, 2}, // [] Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: Moderate 1. Low\\ 0: Disabled, + {EFUSE_BLK0, 96, 2}, // [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled, }; static const esp_efuse_desc_t XTS_DPA_CLK_ENABLE[] = { - {EFUSE_BLK0, 157, 1}, // [] Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: Disable., -}; - -static const esp_efuse_desc_t HUK_GEN_STATE[] = { - {EFUSE_BLK0, 160, 9}, // [] Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ Even of 1 is valid., -}; - -static const esp_efuse_desc_t XTAL_48M_SEL[] = { - {EFUSE_BLK0, 169, 3}, // [] Represents whether XTAL frequency is 48MHz or not. If not; 40MHz XTAL will be used. If this field contains Odd number bit 1: Enable 48MHz XTAL\ Even number bit 1: Enable 40MHz XTAL, -}; - -static const esp_efuse_desc_t XTAL_48M_SEL_MODE[] = { - {EFUSE_BLK0, 172, 1}, // [] Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: eFuse\\ 0: strapping-PAD-state, -}; - -static const esp_efuse_desc_t ECDSA_DISABLE_P192[] = { - {EFUSE_BLK0, 173, 1}, // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable, + {EFUSE_BLK0, 98, 1}, // [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable., }; static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = { - {EFUSE_BLK0, 174, 1}, // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable, + {EFUSE_BLK0, 99, 1}, // [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable, +}; + +static const esp_efuse_desc_t ECDSA_P384_ENABLE[] = { + {EFUSE_BLK0, 100, 1}, // [] Represents if the chip supports ECDSA P384, +}; + +static const esp_efuse_desc_t SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 101, 1}, // [] Represents whether secure boot is enabled or disabled. 1: enabled 0: disabled, +}; + +static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 102, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled, +}; + +static const esp_efuse_desc_t KM_DISABLE_DEPLOY_MODE[] = { + {EFUSE_BLK0, 103, 5}, // [] Represents whether the new key deployment of key manager is disabled. Bit0: Represents whether the new ECDSA key deployment is disabled0: Enabled1: DisabledBit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is disabled0: Enabled1: DisabledBit2: Represents whether the new HMAC key deployment is disabled0: Enabled1: DisabledBit3: Represents whether the new DS key deployment is disabled0: Enabled1: Disabled, +}; + +static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE[] = { + {EFUSE_BLK0, 108, 2}, // [] Represents the cycle at which the Key Manager switches random numbers.0: Controlled by the \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For more information; please refer to Chapter \ref{mod:keymng} \textit{\nameref{mod:keymng}}1: 8 Key Manager clock cycles2: 16 Key Manager clock cycles3: 32 Key Manager clock cycles, +}; + +static const esp_efuse_desc_t KM_DEPLOY_ONLY_ONCE[] = { + {EFUSE_BLK0, 110, 5}, // [] Represents whether the corresponding key can be deployed only once.Bit0: Represents whether the ECDSA key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit2: Represents whether the HMAC key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit3: Represents whether the DS key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only once, +}; + +static const esp_efuse_desc_t FORCE_USE_KEY_MANAGER_KEY[] = { + {EFUSE_BLK0, 115, 5}, // [] Represents whether the corresponding key must come from Key Manager. Bit0: Represents whether the ECDSA key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit2: Represents whether the HMAC key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit3: Represents whether the DS key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key Manager, +}; + +static const esp_efuse_desc_t FORCE_DISABLE_SW_INIT_KEY[] = { + {EFUSE_BLK0, 120, 1}, // [] Represents whether to disable the use of the initialization key written by software and instead force use efuse\_init\_key.0: Enable1: Disable, +}; + +static const esp_efuse_desc_t KM_XTS_KEY_LENGTH_256[] = { + {EFUSE_BLK0, 121, 1}, // [] Represents which key flash encryption uses.0: XTS-AES-256 key1: XTS-AES-128 key, +}; + +static const esp_efuse_desc_t LOCK_KM_KEY[] = { + {EFUSE_BLK0, 122, 1}, // [] Represents whether the keys in the Key Manager are locked after deployment.0: Not locked1: Locked, +}; + +static const esp_efuse_desc_t FLASH_TPUW[] = { + {EFUSE_BLK0, 123, 3}, // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 127, 1}, // [] Represents whether Download mode is disabled or enabled. 1: disabled 0: enabled, +}; + +static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 128, 1}, // [] Represents whether direct boot mode is disabled or enabled. 1: disabled 0: enabled, +}; + +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + {EFUSE_BLK0, 129, 1}, // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled 0: enabled, +}; + +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 130, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable, +}; + +static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 131, 1}, // [] Represents whether security download is enabled or disabled. 1: enabled 0: disabled, +}; + +static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 132, 2}, // [] Represents the type of UART printing. 00: force enable printing 01: enable printing when GPIO8 is reset at low level 10: enable printing when GPIO8 is reset at high level 11: force disable printing, +}; + +static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 134, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced 0:not forced, +}; + +static const esp_efuse_desc_t SECURE_VERSION[] = { + {EFUSE_BLK0, 135, 16}, // [] Represents the version used by ESP-IDF anti-rollback feature, +}; + +static const esp_efuse_desc_t HUK_GEN_STATE[] = { + {EFUSE_BLK0, 151, 5}, // [] Represents whether the HUK generate mode is valid.Odd count of bits with a value of 1: InvalidEven count of bits with a value of 1: Valid, +}; + +static const esp_efuse_desc_t FLASH_LDO_EFUSE_SEL[] = { + {EFUSE_BLK0, 156, 1}, // [] Represents whether to select efuse control flash ldo default voltage. 1 : efuse 0 : strapping, +}; + +static const esp_efuse_desc_t USB_EXCHG_PINS[] = { + {EFUSE_BLK0, 168, 1}, // [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged, +}; + +static const esp_efuse_desc_t USB_OTG_FS_EXCHG_PINS[] = { + {EFUSE_BLK0, 169, 1}, // [] Represents whether the D+ and D- pins of USB_OTG_FS PHY is exchanged. 1: exchanged 0: not exchanged, +}; + +static const esp_efuse_desc_t USB_PHY_SEL[] = { + {EFUSE_BLK0, 170, 1}, // [] Represents whether to exchange the USB_SERIAL_JTAG PHY with USB_OTG_FS PHY. 1: exchanged. 0: not exchanged, +}; + +static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 171, 3}, // [] Represents whether JTAG is disabled in soft way. Odd number: disabled Even number: enabled, +}; + +static const esp_efuse_desc_t IO_LDO_ADJUST[] = { + {EFUSE_BLK0, 174, 8}, // [] Represents configuration of IO LDO mode and voltage., +}; + +static const esp_efuse_desc_t IO_LDO_1P8[] = { + {EFUSE_BLK0, 182, 1}, // [] Represents select IO LDO voltage to 1.8V or 3.3V. 1: 1.8V 0: 3.3V, +}; + +static const esp_efuse_desc_t DCDC_CCM_EN[] = { + {EFUSE_BLK0, 183, 1}, // [] Represents whether change DCDC to CCM mode, }; static const esp_efuse_desc_t MAC[] = { @@ -676,160 +524,40 @@ static const esp_efuse_desc_t MAC_EXT[] = { {EFUSE_BLK1, 48, 16}, // [] Represents the extended bits of MAC address, }; -static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { - {EFUSE_BLK1, 64, 4}, // [] Minor chip version, +static const esp_efuse_desc_t PVT_LIMIT[] = { + {EFUSE_BLK1, 64, 16}, // [] Power glitch monitor threthold, }; -static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 68, 2}, // [] Minor chip version, +static const esp_efuse_desc_t PVT_CELL_SELECT[] = { + {EFUSE_BLK1, 80, 7}, // [] Power glitch monitor PVT cell select, }; -static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 70, 1}, // [] Disables check of wafer version major, +static const esp_efuse_desc_t PVT_PUMP_LIMIT[] = { + {EFUSE_BLK1, 87, 8}, // [] Use to configure voltage monitor limit for charge pump, }; -static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK1, 71, 1}, // [] Disables check of blk version major, +static const esp_efuse_desc_t PUMP_DRV[] = { + {EFUSE_BLK1, 96, 4}, // [] Use to configure charge pump voltage gain, }; -static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { - {EFUSE_BLK1, 72, 3}, // [] BLK_VERSION_MINOR of BLOCK2, +static const esp_efuse_desc_t WDT_DELAY_SEL[] = { + {EFUSE_BLK1, 100, 2}, // [] Represents the threshold level of the RTC watchdog STG0 timeout. 0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16, }; -static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { - {EFUSE_BLK1, 75, 2}, // [] BLK_VERSION_MAJOR of BLOCK2, +static const esp_efuse_desc_t HYS_EN_PAD[] = { + {EFUSE_BLK1, 102, 1}, // [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled 0:disabled, }; -static const esp_efuse_desc_t FLASH_CAP[] = { - {EFUSE_BLK1, 77, 3}, // [] Flash capacity, +static const esp_efuse_desc_t PVT_GLITCH_CHARGE_RESET[] = { + {EFUSE_BLK1, 103, 1}, // [] Represents whether to trigger reset or charge pump when PVT power glitch happened.1:Trigger charge pump. 0:Trigger reset, }; -static const esp_efuse_desc_t FLASH_VENDOR[] = { - {EFUSE_BLK1, 80, 3}, // [] Flash vendor, +static const esp_efuse_desc_t VDD_SPI_LDO_ADJUST[] = { + {EFUSE_BLK1, 105, 8}, // [] Represents configuration of FLASH LDO mode and voltage., }; -static const esp_efuse_desc_t PSRAM_CAP[] = { - {EFUSE_BLK1, 83, 3}, // [] Psram capacity, -}; - -static const esp_efuse_desc_t PSRAM_VENDOR[] = { - {EFUSE_BLK1, 86, 2}, // [] Psram vendor, -}; - -static const esp_efuse_desc_t TEMP[] = { - {EFUSE_BLK1, 88, 2}, // [] Temp (die embedded inside), -}; - -static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 90, 3}, // [] Package version, -}; - -static const esp_efuse_desc_t PA_TRIM_VERSION[] = { - {EFUSE_BLK1, 93, 3}, // [] PADC CAL PA trim version, -}; - -static const esp_efuse_desc_t TRIM_N_BIAS[] = { - {EFUSE_BLK1, 96, 5}, // [] PADC CAL N bias, -}; - -static const esp_efuse_desc_t TRIM_P_BIAS[] = { - {EFUSE_BLK1, 101, 5}, // [] PADC CAL P bias, -}; - -static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = { - {EFUSE_BLK1, 106, 4}, // [] Active HP DBIAS of fixed voltage, -}; - -static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = { - {EFUSE_BLK1, 110, 4}, // [] Active LP DBIAS of fixed voltage, -}; - -static const esp_efuse_desc_t LSLP_HP_DBG[] = { - {EFUSE_BLK1, 114, 2}, // [] LSLP HP DBG of fixed voltage, -}; - -static const esp_efuse_desc_t LSLP_HP_DBIAS[] = { - {EFUSE_BLK1, 116, 4}, // [] LSLP HP DBIAS of fixed voltage, -}; - -static const esp_efuse_desc_t DSLP_LP_DBG[] = { - {EFUSE_BLK1, 120, 4}, // [] DSLP LP DBG of fixed voltage, -}; - -static const esp_efuse_desc_t DSLP_LP_DBIAS[] = { - {EFUSE_BLK1, 124, 5}, // [] DSLP LP DBIAS of fixed voltage, -}; - -static const esp_efuse_desc_t LP_HP_DBIAS_VOL_GAP[] = { - {EFUSE_BLK1, 129, 5}, // [] DBIAS gap between LP and HP, -}; - -static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { - {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, -}; - -static const esp_efuse_desc_t TEMPERATURE_SENSOR[] = { - {EFUSE_BLK2, 128, 9}, // [] Temperature calibration data, -}; - -static const esp_efuse_desc_t OCODE[] = { - {EFUSE_BLK2, 137, 8}, // [] ADC OCode, -}; - -static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = { - {EFUSE_BLK2, 145, 10}, // [] Average initcode of ADC1 atten0, -}; - -static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = { - {EFUSE_BLK2, 155, 10}, // [] Average initcode of ADC1 atten0, -}; - -static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = { - {EFUSE_BLK2, 165, 10}, // [] Average initcode of ADC1 atten0, -}; - -static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = { - {EFUSE_BLK2, 175, 10}, // [] Average initcode of ADC1 atten0, -}; - -static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = { - {EFUSE_BLK2, 185, 10}, // [] HI DOUT of ADC1 atten0, -}; - -static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = { - {EFUSE_BLK2, 195, 10}, // [] HI DOUT of ADC1 atten1, -}; - -static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = { - {EFUSE_BLK2, 205, 10}, // [] HI DOUT of ADC1 atten2, -}; - -static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = { - {EFUSE_BLK2, 215, 10}, // [] HI DOUT of ADC1 atten3, -}; - -static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK2, 225, 4}, // [] Gap between ADC1 CH0 and average initcode, -}; - -static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK2, 229, 4}, // [] Gap between ADC1 CH1 and average initcode, -}; - -static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK2, 233, 4}, // [] Gap between ADC1 CH2 and average initcode, -}; - -static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK2, 237, 4}, // [] Gap between ADC1 CH3 and average initcode, -}; - -static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK2, 241, 4}, // [] Gap between ADC1 CH4 and average initcode, -}; - -static const esp_efuse_desc_t ADC1_CH5_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK2, 245, 4}, // [] Gap between ADC1 CH5 and average initcode, +static const esp_efuse_desc_t FLASH_LDO_POWER_SEL[] = { + {EFUSE_BLK1, 113, 1}, // [] Represents which flash ldo be select: 1: FLASH LDO 1P2 0 : FLASH LDO 1P8, }; static const esp_efuse_desc_t USER_DATA[] = { @@ -917,11 +645,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { - &WR_DIS_DIS_ICACHE[0], // [] wr_dis of DIS_ICACHE - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = { &WR_DIS_DIS_USB_JTAG[0], // [] wr_dis of DIS_USB_JTAG NULL @@ -957,16 +680,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[] = { - &WR_DIS_HYS_EN_PAD[0], // [] wr_dis of HYS_EN_PAD - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { - &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT NULL @@ -1032,11 +745,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_P192[] = { - &WR_DIS_ECDSA_DISABLE_P192[0], // [] wr_dis of ECDSA_DISABLE_P192 - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[] = { &WR_DIS_ECC_FORCE_CONST_TIME[0], // [] wr_dis of ECC_FORCE_CONST_TIME NULL @@ -1052,16 +760,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTAL_48M_SEL[] = { - &WR_DIS_XTAL_48M_SEL[0], // [] wr_dis of XTAL_48M_SEL - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTAL_48M_SEL_MODE[] = { - &WR_DIS_XTAL_48M_SEL_MODE[0], // [] wr_dis of XTAL_48M_SEL_MODE - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = { &WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW NULL @@ -1107,21 +805,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { - &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[] = { &WR_DIS_HUK_GEN_STATE[0], // [] wr_dis of HUK_GEN_STATE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { - &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1 - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { &WR_DIS_MAC[0], // [WR_DIS.MAC_FACTORY] wr_dis of MAC NULL @@ -1132,203 +820,48 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { - &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_LIMIT[] = { + &WR_DIS_PVT_LIMIT[0], // [] wr_dis of PVT_LIMIT NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { - &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_CELL_SELECT[] = { + &WR_DIS_PVT_CELL_SELECT[0], // [] wr_dis of PVT_CELL_SELECT NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { - &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_PUMP_LIMIT[] = { + &WR_DIS_PVT_PUMP_LIMIT[0], // [] wr_dis of PVT_PUMP_LIMIT NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { - &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PUMP_DRV[] = { + &WR_DIS_PUMP_DRV[0], // [] wr_dis of PUMP_DRV NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { - &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { + &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { - &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[] = { + &WR_DIS_HYS_EN_PAD[0], // [] wr_dis of HYS_EN_PAD NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = { - &WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_CHARGE_RESET[] = { + &WR_DIS_PVT_GLITCH_CHARGE_RESET[0], // [] wr_dis of PVT_GLITCH_CHARGE_RESET NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = { - &WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_LDO_ADJUST[] = { + &WR_DIS_VDD_SPI_LDO_ADJUST[0], // [] wr_dis of VDD_SPI_LDO_ADJUST NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = { - &WR_DIS_PSRAM_CAP[0], // [] wr_dis of PSRAM_CAP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[] = { - &WR_DIS_PSRAM_VENDOR[0], // [] wr_dis of PSRAM_VENDOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[] = { - &WR_DIS_TEMP[0], // [] wr_dis of TEMP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { - &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PA_TRIM_VERSION[] = { - &WR_DIS_PA_TRIM_VERSION[0], // [] wr_dis of PA_TRIM_VERSION - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_N_BIAS[] = { - &WR_DIS_TRIM_N_BIAS[0], // [] wr_dis of TRIM_N_BIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_P_BIAS[] = { - &WR_DIS_TRIM_P_BIAS[0], // [] wr_dis of TRIM_P_BIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { - &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = { - &WR_DIS_ACTIVE_HP_DBIAS[0], // [] wr_dis of ACTIVE_HP_DBIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = { - &WR_DIS_ACTIVE_LP_DBIAS[0], // [] wr_dis of ACTIVE_LP_DBIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[] = { - &WR_DIS_LSLP_HP_DBG[0], // [] wr_dis of LSLP_HP_DBG - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[] = { - &WR_DIS_LSLP_HP_DBIAS[0], // [] wr_dis of LSLP_HP_DBIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[] = { - &WR_DIS_DSLP_LP_DBG[0], // [] wr_dis of DSLP_LP_DBG - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = { - &WR_DIS_DSLP_LP_DBIAS[0], // [] wr_dis of DSLP_LP_DBIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[] = { - &WR_DIS_LP_HP_DBIAS_VOL_GAP[0], // [] wr_dis of LP_HP_DBIAS_VOL_GAP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { - &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[] = { - &WR_DIS_TEMPERATURE_SENSOR[0], // [] wr_dis of TEMPERATURE_SENSOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = { - &WR_DIS_OCODE[0], // [] wr_dis of OCODE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = { - &WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = { - &WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = { - &WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = { - &WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = { - &WR_DIS_ADC1_HI_DOUT_ATTEN0[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = { - &WR_DIS_ADC1_HI_DOUT_ATTEN1[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = { - &WR_DIS_ADC1_HI_DOUT_ATTEN2[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = { - &WR_DIS_ADC1_HI_DOUT_ATTEN3[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_LDO_POWER_SEL[] = { + &WR_DIS_FLASH_LDO_POWER_SEL[0], // [] wr_dis of FLASH_LDO_POWER_SEL NULL }; @@ -1382,11 +915,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[] = { - &WR_DIS_VDD_SPI_AS_GPIO[0], // [] wr_dis of VDD_SPI_AS_GPIO - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = { &WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG NULL @@ -1432,88 +960,53 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { - &DIS_ICACHE[0], // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { - &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled + &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled + &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = { - &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled + &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { - &DIS_TWAI[0], // [] Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: enabled + &DIS_TWAI[0], // [] Represents whether TWAI function is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { - &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { - &SOFT_DIS_JTAG[0], // [] Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even number: enabled + &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { - &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled + &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled NULL }; -const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { - &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged +const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_EN[] = { + &PVT_GLITCH_EN[0], // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable NULL }; -const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { - &VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned +const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_MODE[] = { + &PVT_GLITCH_MODE[0], // [] Use to configure glitch mode NULL }; -const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[] = { - &KM_DISABLE_DEPLOY_MODE[0], // [] Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled \\ 0: enabled. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[] = { - &KM_RND_SWITCH_CYCLE[0], // [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[] = { - &KM_DEPLOY_ONLY_ONCE[0], // [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[] = { - &FORCE_USE_KEY_MANAGER_KEY[0], // [] Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[] = { - &FORCE_DISABLE_SW_INIT_KEY[0], // [] Set this bit to disable software written init key; and force use efuse_init_key - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 +const esp_efuse_desc_t* ESP_EFUSE_DIS_CORE1[] = { + &DIS_CORE1[0], // [] Represents whether the CPU-Core1 is disabled. 1: Disabled. 0: Not disable NULL }; @@ -1572,18 +1065,68 @@ const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = { + &XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = { + &XTS_DPA_CLK_ENABLE[0], // [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { + &ECC_FORCE_CONST_TIME[0], // [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ECDSA_P384_ENABLE[] = { + &ECDSA_P384_ENABLE[0], // [] Represents if the chip supports ECDSA P384 + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled + &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled. 1: enabled 0: disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[] = { + &KM_DISABLE_DEPLOY_MODE[0], // [] Represents whether the new key deployment of key manager is disabled. Bit0: Represents whether the new ECDSA key deployment is disabled0: Enabled1: DisabledBit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is disabled0: Enabled1: DisabledBit2: Represents whether the new HMAC key deployment is disabled0: Enabled1: DisabledBit3: Represents whether the new DS key deployment is disabled0: Enabled1: Disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[] = { + &KM_RND_SWITCH_CYCLE[0], // [] Represents the cycle at which the Key Manager switches random numbers.0: Controlled by the \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For more information; please refer to Chapter \ref{mod:keymng} \textit{\nameref{mod:keymng}}1: 8 Key Manager clock cycles2: 16 Key Manager clock cycles3: 32 Key Manager clock cycles + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[] = { + &KM_DEPLOY_ONLY_ONCE[0], // [] Represents whether the corresponding key can be deployed only once.Bit0: Represents whether the ECDSA key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit2: Represents whether the HMAC key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit3: Represents whether the DS key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only once + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[] = { + &FORCE_USE_KEY_MANAGER_KEY[0], // [] Represents whether the corresponding key must come from Key Manager. Bit0: Represents whether the ECDSA key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit2: Represents whether the HMAC key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit3: Represents whether the DS key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key Manager + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[] = { + &FORCE_DISABLE_SW_INIT_KEY[0], // [] Represents whether to disable the use of the initialization key written by software and instead force use efuse\_init\_key.0: Enable1: Disable NULL }; const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[] = { - &KM_XTS_KEY_LENGTH_256[0], // [] Set this bitto configure flash encryption use xts-128 key. else use xts-256 key + &KM_XTS_KEY_LENGTH_256[0], // [] Represents which key flash encryption uses.0: XTS-AES-256 key1: XTS-AES-128 key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[] = { + &LOCK_KM_KEY[0], // [] Represents whether the keys in the Key Manager are locked after deployment.0: Not locked1: Locked NULL }; @@ -1593,42 +1136,37 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled + &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: enabled + &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[] = { - &LOCK_KM_KEY[0], // [] Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: disabled + &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled. 1: enabled 0: disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { - &UART_PRINT_CONTROL[0], // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} + &UART_PRINT_CONTROL[0], // [] Represents the type of UART printing. 00: force enable printing 01: enable printing when GPIO8 is reset at low level 10: enable printing when GPIO8 is reset at high level 11: force disable printing NULL }; const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { - &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot.\\ 1: forced\\ 0:not forced + &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced 0:not forced NULL }; @@ -1637,48 +1175,48 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = { - &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled.\\ 1: disabled\\ 0: enabled - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = { - &HYS_EN_PAD[0], // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = { - &XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: Moderate 1. Low\\ 0: Disabled - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = { - &XTS_DPA_CLK_ENABLE[0], // [] Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: Disable. - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[] = { - &HUK_GEN_STATE[0], // [] Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ Even of 1 is valid. + &HUK_GEN_STATE[0], // [] Represents whether the HUK generate mode is valid.Odd count of bits with a value of 1: InvalidEven count of bits with a value of 1: Valid NULL }; -const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL[] = { - &XTAL_48M_SEL[0], // [] Represents whether XTAL frequency is 48MHz or not. If not; 40MHz XTAL will be used. If this field contains Odd number bit 1: Enable 48MHz XTAL\ Even number bit 1: Enable 40MHz XTAL +const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_EFUSE_SEL[] = { + &FLASH_LDO_EFUSE_SEL[0], // [] Represents whether to select efuse control flash ldo default voltage. 1 : efuse 0 : strapping NULL }; -const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL_MODE[] = { - &XTAL_48M_SEL_MODE[0], // [] Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: eFuse\\ 0: strapping-PAD-state +const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { + &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged NULL }; -const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[] = { - &ECDSA_DISABLE_P192[0], // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable +const esp_efuse_desc_t* ESP_EFUSE_USB_OTG_FS_EXCHG_PINS[] = { + &USB_OTG_FS_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins of USB_OTG_FS PHY is exchanged. 1: exchanged 0: not exchanged NULL }; -const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { - &ECC_FORCE_CONST_TIME[0], // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable +const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[] = { + &USB_PHY_SEL[0], // [] Represents whether to exchange the USB_SERIAL_JTAG PHY with USB_OTG_FS PHY. 1: exchanged. 0: not exchanged + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { + &SOFT_DIS_JTAG[0], // [] Represents whether JTAG is disabled in soft way. Odd number: disabled Even number: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_IO_LDO_ADJUST[] = { + &IO_LDO_ADJUST[0], // [] Represents configuration of IO LDO mode and voltage. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_IO_LDO_1P8[] = { + &IO_LDO_1P8[0], // [] Represents select IO LDO voltage to 1.8V or 3.3V. 1: 1.8V 0: 3.3V + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DCDC_CCM_EN[] = { + &DCDC_CCM_EN[0], // [] Represents whether change DCDC to CCM mode NULL }; @@ -1697,198 +1235,48 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { - &WAFER_VERSION_MINOR[0], // [] Minor chip version +const esp_efuse_desc_t* ESP_EFUSE_PVT_LIMIT[] = { + &PVT_LIMIT[0], // [] Power glitch monitor threthold NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { - &WAFER_VERSION_MAJOR[0], // [] Minor chip version +const esp_efuse_desc_t* ESP_EFUSE_PVT_CELL_SELECT[] = { + &PVT_CELL_SELECT[0], // [] Power glitch monitor PVT cell select NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { - &DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major +const esp_efuse_desc_t* ESP_EFUSE_PVT_PUMP_LIMIT[] = { + &PVT_PUMP_LIMIT[0], // [] Use to configure voltage monitor limit for charge pump NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { - &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major +const esp_efuse_desc_t* ESP_EFUSE_PUMP_DRV[] = { + &PUMP_DRV[0], // [] Use to configure charge pump voltage gain NULL }; -const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { - &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2 +const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { + &WDT_DELAY_SEL[0], // [] Represents the threshold level of the RTC watchdog STG0 timeout. 0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { - &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2 +const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = { + &HYS_EN_PAD[0], // [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled 0:disabled NULL }; -const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = { - &FLASH_CAP[0], // [] Flash capacity +const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_CHARGE_RESET[] = { + &PVT_GLITCH_CHARGE_RESET[0], // [] Represents whether to trigger reset or charge pump when PVT power glitch happened.1:Trigger charge pump. 0:Trigger reset NULL }; -const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { - &FLASH_VENDOR[0], // [] Flash vendor +const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_LDO_ADJUST[] = { + &VDD_SPI_LDO_ADJUST[0], // [] Represents configuration of FLASH LDO mode and voltage. NULL }; -const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = { - &PSRAM_CAP[0], // [] Psram capacity - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = { - &PSRAM_VENDOR[0], // [] Psram vendor - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = { - &TEMP[0], // [] Temp (die embedded inside) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { - &PKG_VERSION[0], // [] Package version - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_PA_TRIM_VERSION[] = { - &PA_TRIM_VERSION[0], // [] PADC CAL PA trim version - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_TRIM_N_BIAS[] = { - &TRIM_N_BIAS[0], // [] PADC CAL N bias - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_TRIM_P_BIAS[] = { - &TRIM_P_BIAS[0], // [] PADC CAL P bias - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = { - &ACTIVE_HP_DBIAS[0], // [] Active HP DBIAS of fixed voltage - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = { - &ACTIVE_LP_DBIAS[0], // [] Active LP DBIAS of fixed voltage - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[] = { - &LSLP_HP_DBG[0], // [] LSLP HP DBG of fixed voltage - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[] = { - &LSLP_HP_DBIAS[0], // [] LSLP HP DBIAS of fixed voltage - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[] = { - &DSLP_LP_DBG[0], // [] DSLP LP DBG of fixed voltage - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = { - &DSLP_LP_DBIAS[0], // [] DSLP LP DBIAS of fixed voltage - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[] = { - &LP_HP_DBIAS_VOL_GAP[0], // [] DBIAS gap between LP and HP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { - &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[] = { - &TEMPERATURE_SENSOR[0], // [] Temperature calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { - &OCODE[0], // [] ADC OCode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = { - &ADC1_AVE_INITCODE_ATTEN0[0], // [] Average initcode of ADC1 atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = { - &ADC1_AVE_INITCODE_ATTEN1[0], // [] Average initcode of ADC1 atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = { - &ADC1_AVE_INITCODE_ATTEN2[0], // [] Average initcode of ADC1 atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = { - &ADC1_AVE_INITCODE_ATTEN3[0], // [] Average initcode of ADC1 atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = { - &ADC1_HI_DOUT_ATTEN0[0], // [] HI DOUT of ADC1 atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = { - &ADC1_HI_DOUT_ATTEN1[0], // [] HI DOUT of ADC1 atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = { - &ADC1_HI_DOUT_ATTEN2[0], // [] HI DOUT of ADC1 atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = { - &ADC1_HI_DOUT_ATTEN3[0], // [] HI DOUT of ADC1 atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH0 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH1 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH2 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH3 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH4 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH5_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH5 and average initcode +const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_POWER_SEL[] = { + &FLASH_LDO_POWER_SEL[0], // [] Represents which flash ldo be select: 1: FLASH LDO 1P2 0 : FLASH LDO 1P8 NULL }; diff --git a/components/efuse/esp32h4/include/esp_efuse_table.h b/components/efuse/esp32h4/include/esp_efuse_table.h index f45ac551be..36163bc224 100644 --- a/components/efuse/esp32h4/include/esp_efuse_table.h +++ b/components/efuse/esp32h4/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table b26e7466c400977081a142076ef1a5bb +// md5_digest_table 6bfa2ae917ac6cbce5b70a55ea6a78bd // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -26,7 +26,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; @@ -34,8 +33,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; @@ -55,12 +52,9 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_P192[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTAL_48M_SEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTAL_48M_SEL_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; @@ -70,52 +64,19 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; #define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PA_TRIM_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_N_BIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_P_BIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_LIMIT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_CELL_SELECT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_PUMP_LIMIT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PUMP_DRV[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_CHARGE_RESET[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_LDO_ADJUST[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_LDO_POWER_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; @@ -136,7 +97,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; #define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; @@ -153,23 +113,16 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; #define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; #define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CORE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; @@ -187,70 +140,49 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; #define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_P384_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[]; extern const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_EFUSE_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG_FS_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_IO_LDO_ADJUST[]; +extern const esp_efuse_desc_t* ESP_EFUSE_IO_LDO_1P8[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_CCM_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; #define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PA_TRIM_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_TRIM_N_BIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_TRIM_P_BIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_LIMIT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_CELL_SELECT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_PUMP_LIMIT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PUMP_DRV[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_CHARGE_RESET[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_LDO_ADJUST[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_POWER_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];