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sar: init sar periph power state

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This commit is contained in:
Armando 2023-04-23 18:17:25 +08:00
parent 46a1253022
commit 08c77a7eaf
6 changed files with 49 additions and 0 deletions
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8
components/esp_hw_support/port/esp32/rtc_init.c
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@ -12,6 +12,9 @@
#include "soc/dport_reg.h"
#include "hal/efuse_ll.h"
#include "soc/gpio_periph.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
void rtc_init(rtc_config_t cfg)
@ -104,6 +107,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)

8
components/esp_hw_support/port/esp32c2/rtc_init.c
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@ -21,6 +21,9 @@
#include "esp_hw_log.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
static const char *TAG = "rtc_init";
@ -121,6 +124,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 1);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)

8
components/esp_hw_support/port/esp32c3/rtc_init.c
View File

@ -21,6 +21,9 @@
#include "esp_hw_log.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
static const char *TAG = "rtc_init";
@ -166,6 +169,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 1);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)

8
components/esp_hw_support/port/esp32h2/rtc_init.c
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@ -20,6 +20,9 @@
#include "esp_efuse_table.h"
#include "i2c_pmu.h"
#include "soc/clkrst_reg.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
void pmu_ctl(void);
void dcdc_ctl(uint32_t mode);
@ -135,6 +138,11 @@ void rtc_init(rtc_config_t cfg)
}
/* config dcdc frequency */
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL0_REG, RTC_CNTL_FSW_DCDC, RTC_CNTL_DCDC_FREQ_DEFAULT);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
void pmu_ctl(void)

8
components/esp_hw_support/port/esp32s2/rtc_init.c
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@ -18,6 +18,9 @@
#include "esp_hw_log.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
__attribute__((unused)) static const char *TAG = "rtc_init";
@ -173,6 +176,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)

9
components/esp_hw_support/port/esp32s3/rtc_init.c
View File

@ -25,6 +25,10 @@
#include "esp_efuse_table.h"
#include "esp_private/spi_flash_os.h"
#include "hal/efuse_hal.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
#define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
@ -206,6 +210,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)