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Merge branch 'bugfix/postpone_cpu_pll_off_time_in_slp_v5.2' into 'release/v5.2'

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fix(clk): postpone CPU PLL off time in sleep (v5.2)

See merge request espressif/esp-idf!36301
This commit is contained in:
morris 2025-01-15 10:14:27 +08:00
commit 0e42d52009
2 changed files with 15 additions and 4 deletions
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7
components/esp_hw_support/include/esp_private/rtc_clk.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -19,8 +19,9 @@ extern "C" {
* `rtc_clk_cpu_freq_set_xtal` instead. It will always disable the corresponding PLL after switching the CPU clock
* source to XTAL (except for S2).
*
* Currently, this function should only be called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU
* clock source back to XTAL (by default) before reset.
* Currently, this function is only called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU
* clock source back to XTAL (by default) before reset, and in `esp_sleep_start` to switch CPU clock source to XTAL
* before entering sleep for PMU supported chips.
*/
void rtc_clk_cpu_set_to_default_config(void);

12
components/esp_hw_support/sleep_modes.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -71,6 +71,7 @@
#include "esp_private/sleep_cpu.h"
#include "esp_private/sleep_modem.h"
#include "esp_private/esp_clk.h"
#include "esp_private/rtc_clk.h"
#include "esp_private/esp_task_wdt.h"
#include "esp_private/sar_periph_ctrl.h"
#include "esp_private/mspi_timing_tuning.h"
@ -762,7 +763,16 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
// Save current frequency and switch to XTAL
rtc_cpu_freq_config_t cpu_freq_config;
rtc_clk_cpu_freq_get_config(&cpu_freq_config);
#if SOC_PMU_SUPPORTED
// For PMU supported chips, CPU's PLL power can be turned off by PMU, so no need to disable the PLL at here.
// Leaving PLL on at this stage also helps USJ keep connection and retention operation (if they rely on this PLL).
rtc_clk_cpu_set_to_default_config();
#else
// For earlier chips, there is no PMU module that can turn off the CPU's PLL, so it has to be disabled at here to save the power consumption.
// Though ESP32C3/S3 has USB CDC device, it can not function properly during sleep due to the lack of APB clock (before C6, USJ relies on APB clock to work).
// Therefore, we will always disable CPU's PLL (i.e. BBPLL).
rtc_clk_cpu_freq_set_xtal();
#endif
#if SOC_PM_SUPPORT_EXT0_WAKEUP
// Configure pins for external wakeup