mirror of
https://github.com/espressif/esp-idf
synced 2025-03-10 01:29:21 -04:00
Merge branch 'feature/support_isp_hisp_p4' into 'master'
feature(isp): Add ISP histogram support for esp32p4 Closes IDF-10192 See merge request espressif/esp-idf!31342
This commit is contained in:
Gao Xu
commit
0e4464c363
@ -14,7 +14,8 @@ if(CONFIG_SOC_ISP_SUPPORTED)
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"src/isp_ccm.c"
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"src/isp_awb.c"
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"src/isp_ae.c"
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"src/isp_gamma.c")
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"src/isp_gamma.c"
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"src/isp_hist.c")
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endif()
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if(CONFIG_SOC_ISP_BF_SUPPORTED)
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@ -18,3 +18,4 @@
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#include "driver/isp_bf.h"
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#include "driver/isp_ccm.h"
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#include "driver/isp_sharpen.h"
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#include "driver/isp_hist.h"
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@ -30,7 +30,7 @@ typedef struct {
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bool has_line_end_packet; ///< Enable line end packet
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uint32_t h_res; ///< Input horizontal resolution, i.e. the number of pixels in a line
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uint32_t v_res; ///< Input vertical resolution, i.e. the number of lines in a frame
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int intr_priority; ///< The interrupt priority, range 0~3
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int intr_priority; ///< The interrupt priority, range 0~3, if set to 0, the driver will try to allocate an interrupt with a relative low priority (1,2,3)
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} esp_isp_processor_cfg_t;
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/**
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186
components/esp_driver_isp/include/driver/isp_hist.h
Normal file
186
components/esp_driver_isp/include/driver/isp_hist.h
Normal file
@ -0,0 +1,186 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_err.h"
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#include "driver/isp_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* ISP Histogram Struct
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* |<----------------------------- INTERVAL_NUMS = 16 ------------------------------>|
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* | | | | |
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* | Segment 0 | Segment 1 | ............ | Segment 15 |
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* 0 threshold 0 threshold 1 ... threshold 14 255
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* |<------------------------------------------------------------------------------->|
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*/
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/**
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* @brief Hist controller config
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*/
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typedef struct {
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isp_window_t window; /*!< The sampling window of histogram, see `isp_window_t`*/
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isp_hist_sampling_mode_t hist_mode; /*!< ISP histogram sampling mode */
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isp_hist_rgb_coefficient_t rgb_coefficient; /*!< RGB coefficients, adjust the sensitivity to red, geen, and blue colors in the image,
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only effect when hist_mode is ISP_HIST_SAMPLING_RGB, the sum of all coefficients decimal should be 256**/
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isp_hist_weight_t window_weight[ISP_HIST_BLOCK_X_NUM * ISP_HIST_BLOCK_Y_NUM]; /*!< Weights of histogram's each subwindows, the sum of all subwindows's weight decimal should be 256*/
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uint32_t segment_threshold[ISP_HIST_INTERVAL_NUMS]; /*!< Threshold to segment the histogram into intervals, range 0~255 */
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} esp_isp_hist_config_t;
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/**
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* @brief New an ISP hist controller
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*
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* @param[in] isp_proc ISP Processor handle
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* @param[in] hist_cfg Pointer to hist config. Refer to ``esp_isp_hist_config_t``.
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* @param[out] ret_hdl hist controller handle
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*
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid
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* - ESP_ERR_INVALID_STATE Invalid state
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* - ESP_ERR_NOT_FOUND No free interrupt found with the specified flags
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* - ESP_ERR_NO_MEM If out of memory
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*/
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esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_hist_config_t *hist_cfg, isp_hist_ctlr_t *ret_hdl);
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/**
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* @brief Delete an ISP hist controller
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*
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* @param[in] hist_ctlr hist controller handle
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*
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid.
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* - ESP_ERR_INVALID_STATE Driver state is invalid.
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*/
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esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr);
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/**
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* @brief Enable an ISP hist controller
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*
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* @param[in] hist_ctlr hist controller handle
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*
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid.
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* - ESP_ERR_INVALID_STATE Driver state is invalid.
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*/
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esp_err_t esp_isp_hist_controller_enable(isp_hist_ctlr_t hist_ctlr);
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/**
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* @brief Disable an ISP hist controller
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*
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* @param[in] hist_ctlr hist controller handle
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*
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid.
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* - ESP_ERR_INVALID_STATE Driver state is invalid.
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*/
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esp_err_t esp_isp_hist_controller_disable(isp_hist_ctlr_t hist_ctlr);
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/**
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* @brief Trigger hist reference statistics for one time and get the result
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*
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* @param[in] hist_ctlr hist controller handle
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* @param[in] timeout_ms Timeout in millisecond
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* - timeout_ms < 0: Won't return until finished
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* - timeout_ms = 0: No timeout, trigger one time statistics and return immediately,
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* in this case, the result won't be assigned in this function,
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* but you can get the result in the callback `esp_isp_hist_cbs_t::on_statistics_done`
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* - timeout_ms > 0: Wait for specified milliseconds, if not finished, then return timeout error
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* @param[out] out_res hist reference statistics result
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*
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* @return
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* - ESP_OK On success
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* - ESP_ERR_TIMEOUT Wait for the result timeout
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* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid.
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* - ESP_ERR_INVALID_STATE Driver state is invalid.
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*/
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esp_err_t esp_isp_hist_controller_get_oneshot_statistics(isp_hist_ctlr_t hist_ctlr, int timeout_ms, isp_hist_result_t *out_res);
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/**
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* @brief Start hist continuous statistics of the reference in the window
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* @note This function is an asynchronous and non-block function,
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* it will start the continuous statistics and return immediately.
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* You have to register the hist callback and get the result from the callback event data.
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*
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* @param[in] hist_ctlr hist controller handle
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG Null pointer
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* - ESP_ERR_INVALID_STATE Driver state is invalid.
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*/
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esp_err_t esp_isp_hist_controller_start_continuous_statistics(isp_hist_ctlr_t hist_ctlr);
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/**
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* @brief Stop hist continuous statistics of the reference in the window
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*
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* @param[in] hist_ctlr hist controller handle
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG Null pointer
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* - ESP_ERR_INVALID_STATE Driver state is invalid.
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*/
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esp_err_t esp_isp_hist_controller_stop_continuous_statistics(isp_hist_ctlr_t hist_ctlr);
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/**
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* @brief Event data of callbacks
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*/
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typedef struct {
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isp_hist_result_t hist_result; /*!< The histogram reference statistics result */
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} esp_isp_hist_evt_data_t;
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/**
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* @brief Prototype of ISP hist event callback
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*
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* @param[in] handle ISP hist controller handle
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* @param[in] edata ISP hist event data
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* @param[in] user_data User registered context, registered when in `esp_isp_hist_register_event_callbacks()`
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*
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* @return Whether a high priority task is woken up by this function
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*/
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typedef bool (*esp_isp_hist_callback_t)(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_evt_data_t *edata, void *user_data);
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/**
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* @brief Group of ISP hist callbacks
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*
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* @note These callbacks are all running in an ISR environment.
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* @note When CONFIG_ISP_ISR_IRAM_SAFE is enabled, the callback itself and functions called by it should be placed in IRAM.
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* Involved variables should be in internal RAM as well.
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*/
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typedef struct {
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esp_isp_hist_callback_t on_statistics_done; ///< Event callback, invoked when histogram statistic done.
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} esp_isp_hist_cbs_t;
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/**
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* @brief Register hist event callbacks
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*
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* @note User can deregister a previously registered callback by calling this function and setting the to-be-deregistered callback member in
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* the `cbs` structure to NULL.
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* @note When CONFIG_ISP_ISR_IRAM_SAFE is enabled, the callback itself and functions called by it should be placed in IRAM.
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* Involved variables (including `user_data`) should be in internal RAM as well.
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*
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* @param[in] hist_ctlr hist controller handle
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* @param[in] cbs Group of callback functions
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* @param[in] user_data User data, which will be delivered to the callback functions directly
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*
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* @return
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* - ESP_OK: On success
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* - ESP_ERR_INVALID_ARG: Invalid arguments
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* - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment
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*/
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esp_err_t esp_isp_hist_register_event_callbacks(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_cbs_t *cbs, void *user_data);
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#ifdef __cplusplus
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}
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#endif
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@ -76,6 +76,11 @@ typedef struct isp_awb_controller_t *isp_awb_ctlr_t;
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*/
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typedef struct isp_ae_controller_t *isp_ae_ctlr_t;
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/**
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* @brief Type of ISP HIST controller handle
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*/
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typedef struct isp_hist_controller_t *isp_hist_ctlr_t;
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/*---------------------------------------------
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Event Callbacks
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----------------------------------------------*/
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@ -68,6 +68,7 @@ typedef struct isp_processor_t {
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isp_af_ctlr_t af_ctlr[SOC_ISP_AF_CTLR_NUMS];
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isp_awb_ctlr_t awb_ctlr;
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isp_ae_ctlr_t ae_ctlr;
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isp_hist_ctlr_t hist_ctlr;
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isp_fsm_t bf_fsm;
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isp_fsm_t sharpen_fsm;
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esp_isp_evt_cbs_t cbs;
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@ -82,6 +83,7 @@ typedef struct isp_processor_t {
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uint32_t ae_isr_added: 1;
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uint32_t awb_isr_added: 1;
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uint32_t sharp_isr_added: 1;
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uint32_t hist_isr_added: 1;
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} isr_users;
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} isp_processor_t;
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@ -92,6 +94,7 @@ typedef enum {
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ISP_SUBMODULE_AE,
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ISP_SUBMODULE_AWB,
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ISP_SUBMODULE_SHARPEN,
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ISP_SUBMODULE_HIST,
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} isp_submodule_t;
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/*---------------------------------------------------------------
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@ -103,6 +106,7 @@ bool esp_isp_af_isr(isp_proc_handle_t proc, uint32_t af_events);
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bool esp_isp_ae_isr(isp_proc_handle_t proc, uint32_t ae_events);
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bool esp_isp_awb_isr(isp_proc_handle_t proc, uint32_t awb_events);
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bool esp_isp_sharpen_isr(isp_proc_handle_t proc, uint32_t sharp_events);
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bool esp_isp_hist_isr(isp_proc_handle_t proc, uint32_t hist_events);
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#ifdef __cplusplus
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}
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@ -231,6 +231,7 @@ static void IRAM_ATTR s_isp_isr_dispatcher(void *arg)
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uint32_t awb_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_AWB_MASK);
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uint32_t ae_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_AE_MASK);
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uint32_t sharp_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_SHARP_MASK);
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uint32_t hist_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_HIST_MASK);
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bool do_dispatch = false;
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//Deal with hw events
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@ -274,7 +275,16 @@ static void IRAM_ATTR s_isp_isr_dispatcher(void *arg)
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}
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do_dispatch = false;
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}
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if (hist_events) {
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portENTER_CRITICAL_ISR(&proc->spinlock);
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do_dispatch = proc->isr_users.hist_isr_added;
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portEXIT_CRITICAL_ISR(&proc->spinlock);
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if (do_dispatch) {
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need_yield |= esp_isp_hist_isr(proc, hist_events);
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}
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do_dispatch = false;
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}
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if (need_yield) {
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portYIELD_FROM_ISR();
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}
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@ -306,6 +316,9 @@ esp_err_t esp_isp_register_isr(isp_proc_handle_t proc, isp_submodule_t submodule
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case ISP_SUBMODULE_SHARPEN:
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proc->isr_users.sharp_isr_added = true;
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break;
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case ISP_SUBMODULE_HIST:
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proc->isr_users.hist_isr_added = true;
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break;
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default:
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assert(false);
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}
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@ -314,7 +327,7 @@ esp_err_t esp_isp_register_isr(isp_proc_handle_t proc, isp_submodule_t submodule
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if (do_alloc) {
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uint32_t intr_st_reg_addr = isp_ll_get_intr_status_reg_addr(proc->hal.hw);
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uint32_t intr_st_mask = ISP_LL_EVENT_AF_MASK | ISP_LL_EVENT_AE_MASK | ISP_LL_EVENT_AWB_MASK;
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uint32_t intr_st_mask = ISP_LL_EVENT_AF_MASK | ISP_LL_EVENT_AE_MASK | ISP_LL_EVENT_AWB_MASK | ISP_LL_EVENT_HIST_MASK;
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ret = esp_intr_alloc_intrstatus(isp_hw_info.instances[proc->proc_id].irq, ISP_INTR_ALLOC_FLAGS | proc->intr_priority, intr_st_reg_addr, intr_st_mask,
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s_isp_isr_dispatcher, (void *)proc, &proc->intr_hdl);
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if (ret != ESP_OK) {
|
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@ -354,6 +367,9 @@ esp_err_t esp_isp_deregister_isr(isp_proc_handle_t proc, isp_submodule_t submodu
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case ISP_SUBMODULE_SHARPEN:
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proc->isr_users.sharp_isr_added = false;
|
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break;
|
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case ISP_SUBMODULE_HIST:
|
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proc->isr_users.hist_isr_added = false;
|
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break;
|
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default:
|
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assert(false);
|
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}
|
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|
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278
components/esp_driver_isp/src/isp_hist.c
Normal file
278
components/esp_driver_isp/src/isp_hist.c
Normal file
@ -0,0 +1,278 @@
|
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/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
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*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
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*/
|
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|
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#include <esp_types.h>
|
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#include <sys/lock.h>
|
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#include <stdatomic.h>
|
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#include "freertos/FreeRTOS.h"
|
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#include "sdkconfig.h"
|
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#include "esp_log.h"
|
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#include "esp_check.h"
|
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#include "esp_heap_caps.h"
|
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#include "driver/isp_hist.h"
|
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#include "esp_private/isp_private.h"
|
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|
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typedef struct isp_hist_controller_t {
|
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_Atomic isp_fsm_t fsm;
|
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portMUX_TYPE spinlock;
|
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intr_handle_t intr_handle;
|
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isp_proc_handle_t isp_proc;
|
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QueueHandle_t evt_que;
|
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esp_isp_hist_cbs_t cbs;
|
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void *user_data;
|
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} isp_hist_controller_t;
|
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|
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static const char *TAG = "ISP_hist";
|
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|
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/*---------------------------------------------
|
||||
hist
|
||||
----------------------------------------------*/
|
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static esp_err_t s_isp_claim_hist_controller(isp_proc_handle_t isp_proc, isp_hist_ctlr_t hist_ctlr)
|
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{
|
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assert(isp_proc && hist_ctlr);
|
||||
|
||||
bool found = false;
|
||||
portENTER_CRITICAL(&isp_proc->spinlock);
|
||||
if (!isp_proc->hist_ctlr) {
|
||||
isp_proc->hist_ctlr = hist_ctlr;
|
||||
found = true;
|
||||
}
|
||||
portEXIT_CRITICAL(&isp_proc->spinlock);
|
||||
|
||||
if (!found) {
|
||||
return ESP_ERR_NOT_FOUND;
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static void s_isp_declaim_hist_controller(isp_hist_ctlr_t hist_ctlr)
|
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{
|
||||
if (hist_ctlr && hist_ctlr->isp_proc) {
|
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portENTER_CRITICAL(&hist_ctlr->isp_proc->spinlock);
|
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hist_ctlr->isp_proc->hist_ctlr = NULL;
|
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portEXIT_CRITICAL(&hist_ctlr->isp_proc->spinlock);
|
||||
}
|
||||
}
|
||||
|
||||
static void s_isp_hist_free_controller(isp_hist_ctlr_t hist_ctlr)
|
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{
|
||||
if (hist_ctlr) {
|
||||
if (hist_ctlr->intr_handle) {
|
||||
esp_intr_free(hist_ctlr->intr_handle);
|
||||
}
|
||||
if (hist_ctlr->evt_que) {
|
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vQueueDeleteWithCaps(hist_ctlr->evt_que);
|
||||
}
|
||||
free(hist_ctlr);
|
||||
}
|
||||
}
|
||||
|
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static esp_err_t s_esp_isp_hist_config_hardware(isp_proc_handle_t isp_proc, const esp_isp_hist_config_t *hist_cfg)
|
||||
{
|
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for (int i = 0; i < SOC_ISP_HIST_INTERVAL_NUMS; i++) {
|
||||
ESP_RETURN_ON_FALSE((hist_cfg->segment_threshold[i] > 0 && hist_cfg->segment_threshold[i] < 256), ESP_ERR_INVALID_ARG, TAG, "invalid segment threshold");
|
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}
|
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ESP_RETURN_ON_FALSE(hist_cfg->rgb_coefficient.coeff_r.integer == 0 && hist_cfg->rgb_coefficient.coeff_g.integer == 0 && hist_cfg->rgb_coefficient.coeff_b.integer == 0, \
|
||||
ESP_ERR_INVALID_ARG, TAG, "The rgb_coefficient's integer value is bigger than 0");
|
||||
|
||||
int weight_sum = 0;
|
||||
for (int i = 0; i < SOC_ISP_HIST_BLOCK_X_NUMS * SOC_ISP_HIST_BLOCK_Y_NUMS; i++) {
|
||||
ESP_RETURN_ON_FALSE(hist_cfg->window_weight[i].integer == 0, ESP_ERR_INVALID_ARG, TAG, "The subwindow weight's integer value is bigger than -");
|
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weight_sum = weight_sum + hist_cfg->window_weight[i].decimal;
|
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}
|
||||
ESP_RETURN_ON_FALSE(weight_sum == 256, ESP_ERR_INVALID_ARG, TAG, "The sum of all subwindow weight's decimal value is not 256");
|
||||
|
||||
isp_ll_hist_set_mode(isp_proc->hal.hw, hist_cfg->hist_mode);
|
||||
isp_hal_hist_window_config(&isp_proc->hal, &hist_cfg->window);
|
||||
|
||||
isp_ll_hist_set_subwindow_weight(isp_proc->hal.hw, hist_cfg->window_weight);
|
||||
|
||||
isp_ll_hist_set_segment_threshold(isp_proc->hal.hw, hist_cfg->segment_threshold);
|
||||
if (hist_cfg->hist_mode == ISP_HIST_SAMPLING_RGB) {
|
||||
isp_ll_hist_set_rgb_coefficient(isp_proc->hal.hw, &hist_cfg->rgb_coefficient);
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_hist_config_t *hist_cfg, isp_hist_ctlr_t *ret_hdl)
|
||||
{
|
||||
esp_err_t ret = ESP_FAIL;
|
||||
ESP_RETURN_ON_FALSE(isp_proc && hist_cfg && ret_hdl, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
|
||||
isp_hist_ctlr_t hist_ctlr = heap_caps_calloc(1, sizeof(isp_hist_controller_t), ISP_MEM_ALLOC_CAPS);
|
||||
ESP_RETURN_ON_FALSE(hist_ctlr, ESP_ERR_NO_MEM, TAG, "no mem for hist controller");
|
||||
hist_ctlr->evt_que = xQueueCreateWithCaps(1, sizeof(isp_hist_result_t), ISP_MEM_ALLOC_CAPS);
|
||||
ESP_GOTO_ON_FALSE(hist_ctlr->evt_que, ESP_ERR_NO_MEM, err1, TAG, "no mem for hist event queue");
|
||||
|
||||
atomic_init(&hist_ctlr->fsm, ISP_FSM_INIT);
|
||||
hist_ctlr->fsm = ISP_FSM_INIT;
|
||||
hist_ctlr->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
|
||||
hist_ctlr->isp_proc = isp_proc;
|
||||
|
||||
// Configure the hardware
|
||||
ESP_GOTO_ON_ERROR(s_esp_isp_hist_config_hardware(isp_proc, hist_cfg), err1, TAG, "configure HIST hardware failed");
|
||||
|
||||
// Claim an hist controller
|
||||
ESP_GOTO_ON_ERROR(s_isp_claim_hist_controller(isp_proc, hist_ctlr), err1, TAG, "no available controller");
|
||||
|
||||
// Register the HIGT ISR
|
||||
ESP_GOTO_ON_ERROR(esp_isp_register_isr(hist_ctlr->isp_proc, ISP_SUBMODULE_HIST), err2, TAG, "fail to register ISR");
|
||||
|
||||
*ret_hdl = hist_ctlr;
|
||||
|
||||
return ESP_OK;
|
||||
|
||||
err2:
|
||||
s_isp_declaim_hist_controller(hist_ctlr);
|
||||
err1:
|
||||
s_isp_hist_free_controller(hist_ctlr);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(hist_ctlr->isp_proc->hist_ctlr == hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "controller isn't in use");
|
||||
|
||||
ESP_RETURN_ON_FALSE(atomic_load(&hist_ctlr->fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller not in init state");
|
||||
|
||||
// Deregister the HIST ISR
|
||||
ESP_RETURN_ON_FALSE(esp_isp_deregister_isr(hist_ctlr->isp_proc, ISP_SUBMODULE_HIST) == ESP_OK, ESP_FAIL, TAG, "fail to deregister ISR");
|
||||
|
||||
s_isp_declaim_hist_controller(hist_ctlr);
|
||||
s_isp_hist_free_controller(hist_ctlr);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_hist_controller_enable(isp_hist_ctlr_t hist_ctlr)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
|
||||
isp_fsm_t expected_fsm = ISP_FSM_INIT;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ENABLE),
|
||||
ESP_ERR_INVALID_STATE, TAG, "controller not in init state");
|
||||
|
||||
isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, true);
|
||||
isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, true);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_hist_controller_disable(isp_hist_ctlr_t hist_ctlr)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_INIT),
|
||||
ESP_ERR_INVALID_STATE, TAG, "controller not in enable state");
|
||||
|
||||
isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, false);
|
||||
isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, false);
|
||||
esp_intr_disable(hist_ctlr->intr_handle);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_hist_controller_get_oneshot_statistics(isp_hist_ctlr_t hist_ctlr, int timeout_ms, isp_hist_result_t *out_res)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr && (out_res || timeout_ms == 0), ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
|
||||
esp_err_t ret = ESP_OK;
|
||||
TickType_t ticks = timeout_ms < 0 ? portMAX_DELAY : pdMS_TO_TICKS(timeout_ms);
|
||||
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE_ISR(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ONESHOT), ESP_ERR_INVALID_STATE, TAG, "controller is not enabled yet");
|
||||
|
||||
// Reset the queue in case receiving the legacy data in the queue
|
||||
xQueueReset(hist_ctlr->evt_que);
|
||||
// Start the histogram reference statistics and waiting it done
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true);
|
||||
// Wait the statistics to finish and receive the result from the queue
|
||||
if (xQueueReceive(hist_ctlr->evt_que, out_res, ticks) != pdTRUE) {
|
||||
ret = ESP_ERR_TIMEOUT;
|
||||
}
|
||||
// Stop the histogram reference statistics
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false);
|
||||
|
||||
atomic_store(&hist_ctlr->fsm, ISP_FSM_ENABLE);
|
||||
return ret;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_hist_controller_start_continuous_statistics(isp_hist_ctlr_t hist_ctlr)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE_ISR(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_CONTINUOUS), ESP_ERR_INVALID_STATE, TAG, "controller is not enabled yet");
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_hist_controller_stop_continuous_statistics(isp_hist_ctlr_t hist_ctlr)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
|
||||
isp_fsm_t expected_fsm = ISP_FSM_CONTINUOUS;
|
||||
ESP_RETURN_ON_FALSE_ISR(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ENABLE),
|
||||
ESP_ERR_INVALID_STATE, TAG, "controller is not running");
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
INTR
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
bool IRAM_ATTR esp_isp_hist_isr(isp_proc_handle_t proc, uint32_t hist_events)
|
||||
{
|
||||
bool need_yield = false;
|
||||
|
||||
if (hist_events & ISP_LL_EVENT_HIST_FDONE) {
|
||||
isp_hist_ctlr_t hist_ctlr = proc->hist_ctlr;
|
||||
uint32_t hist_value[ISP_HIST_SEGMENT_NUMS] = {};
|
||||
isp_ll_hist_get_histogram_value(proc->hal.hw, hist_value);
|
||||
// Get the statistics result
|
||||
esp_isp_hist_evt_data_t edata = {};
|
||||
for (int i = 0; i < ISP_HIST_SEGMENT_NUMS; i++) {
|
||||
edata.hist_result.hist_value[i] = hist_value[i];
|
||||
}
|
||||
// Invoke the callback if the callback is registered
|
||||
if (hist_ctlr->cbs.on_statistics_done) {
|
||||
need_yield |= hist_ctlr->cbs.on_statistics_done(hist_ctlr, &edata, hist_ctlr->user_data);
|
||||
}
|
||||
BaseType_t high_task_awake = false;
|
||||
// Send the event data to the queue, overwrite the legacy one if exist
|
||||
xQueueOverwriteFromISR(hist_ctlr->evt_que, &edata.hist_result, &high_task_awake);
|
||||
need_yield |= high_task_awake == pdTRUE;
|
||||
|
||||
}
|
||||
|
||||
return need_yield;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_hist_register_event_callbacks(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_cbs_t *cbs, void *user_data)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(hist_ctlr && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
|
||||
|
||||
ESP_RETURN_ON_FALSE(atomic_load(&hist_ctlr->fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller not in init state");
|
||||
#if CONFIG_ISP_ISR_IRAM_SAFE
|
||||
if (cbs->on_statistics_done) {
|
||||
ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_env_change), ESP_ERR_INVALID_ARG, TAG, "on_statistics_done callback not in IRAM");
|
||||
}
|
||||
if (user_data) {
|
||||
ESP_RETURN_ON_FALSE(esp_ptr_internal(user_data), ESP_ERR_INVALID_ARG, TAG, "user context not in internal RAM");
|
||||
}
|
||||
#endif
|
||||
hist_ctlr->cbs.on_statistics_done = cbs->on_statistics_done;
|
||||
hist_ctlr->user_data = user_data;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -327,3 +327,124 @@ TEST_CASE("ISP AE controller exhausted allocation", "[isp]")
|
||||
}
|
||||
TEST_ESP_OK(esp_isp_del_processor(isp_proc));
|
||||
}
|
||||
|
||||
static bool test_isp_hist_default_on_statistics_done_cb(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_evt_data_t *edata, void *user_data)
|
||||
{
|
||||
(void) hist_ctlr;
|
||||
(void) edata;
|
||||
(void) user_data;
|
||||
// Do nothing
|
||||
return false;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
HIST
|
||||
---------------------------------------------------------------*/
|
||||
TEST_CASE("ISP HIST driver basic function", "[isp]")
|
||||
{
|
||||
esp_isp_processor_cfg_t isp_config = {
|
||||
.clk_hz = 80 * 1000 * 1000,
|
||||
.input_data_source = ISP_INPUT_DATA_SOURCE_CSI,
|
||||
.input_data_color_type = ISP_COLOR_RAW8,
|
||||
.output_data_color_type = ISP_COLOR_RGB565,
|
||||
};
|
||||
isp_proc_handle_t isp_proc = NULL;
|
||||
TEST_ESP_OK(esp_isp_new_processor(&isp_config, &isp_proc));
|
||||
TEST_ESP_OK(esp_isp_enable(isp_proc));
|
||||
|
||||
isp_hist_ctlr_t hist_ctlr = NULL;
|
||||
isp_hist_result_t hist_res = {};
|
||||
|
||||
/* Test when sum of weight is not 256 */
|
||||
esp_isp_hist_config_t hist_config_error = {
|
||||
.segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240},
|
||||
.hist_mode = ISP_HIST_SAMPLING_RGB,
|
||||
.rgb_coefficient.coeff_r = {{86, 0}},
|
||||
.rgb_coefficient.coeff_g = {{85, 0}},
|
||||
.rgb_coefficient.coeff_b = {{85, 0}},
|
||||
.window_weight = {
|
||||
{{15, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
},
|
||||
};
|
||||
TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_isp_new_hist_controller(isp_proc, &hist_config_error, &hist_ctlr));
|
||||
|
||||
esp_isp_hist_config_t hist_config = {
|
||||
.segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240},
|
||||
.hist_mode = ISP_HIST_SAMPLING_RGB,
|
||||
.rgb_coefficient.coeff_r = {{86, 0}},
|
||||
.rgb_coefficient.coeff_g = {{85, 0}},
|
||||
.rgb_coefficient.coeff_b = {{85, 0}},
|
||||
.window_weight = {
|
||||
{{16, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
},
|
||||
};
|
||||
TEST_ESP_OK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr));
|
||||
|
||||
/* Register HIST callback */
|
||||
esp_isp_hist_cbs_t hist_cb = {
|
||||
.on_statistics_done = test_isp_hist_default_on_statistics_done_cb,
|
||||
};
|
||||
TEST_ESP_OK(esp_isp_hist_register_event_callbacks(hist_ctlr, &hist_cb, NULL));
|
||||
/* Enabled the hist controller */
|
||||
TEST_ESP_OK(esp_isp_hist_controller_enable(hist_ctlr));
|
||||
/* Start continuous HIST statistics */
|
||||
TEST_ESP_OK(esp_isp_hist_controller_start_continuous_statistics(hist_ctlr));
|
||||
TEST_ESP_ERR(ESP_ERR_INVALID_STATE, esp_isp_hist_controller_get_oneshot_statistics(hist_ctlr, 0, &hist_res));
|
||||
/* Stop continuous HIST statistics */
|
||||
TEST_ESP_OK(esp_isp_hist_controller_stop_continuous_statistics(hist_ctlr));
|
||||
TEST_ESP_ERR(ESP_ERR_TIMEOUT, esp_isp_hist_controller_get_oneshot_statistics(hist_ctlr, 1, &hist_res));
|
||||
/* Disable the hist controller */
|
||||
TEST_ESP_OK(esp_isp_hist_controller_disable(hist_ctlr));
|
||||
/* Delete the hist controller and free the resources */
|
||||
TEST_ESP_OK(esp_isp_del_hist_controller(hist_ctlr));
|
||||
|
||||
TEST_ESP_OK(esp_isp_disable(isp_proc));
|
||||
TEST_ESP_OK(esp_isp_del_processor(isp_proc));
|
||||
}
|
||||
|
||||
TEST_CASE("ISP HIST controller exhausted allocation", "[isp]")
|
||||
{
|
||||
esp_isp_processor_cfg_t isp_config = {
|
||||
.clk_hz = 80 * 1000 * 1000,
|
||||
.input_data_source = ISP_INPUT_DATA_SOURCE_CSI,
|
||||
.input_data_color_type = ISP_COLOR_RAW8,
|
||||
.output_data_color_type = ISP_COLOR_RGB565,
|
||||
};
|
||||
isp_proc_handle_t isp_proc = NULL;
|
||||
TEST_ESP_OK(esp_isp_new_processor(&isp_config, &isp_proc));
|
||||
|
||||
esp_isp_hist_config_t hist_config = {
|
||||
.segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240},
|
||||
.hist_mode = ISP_HIST_SAMPLING_RGB,
|
||||
.rgb_coefficient.coeff_r = {{86, 0}},
|
||||
.rgb_coefficient.coeff_g = {{85, 0}},
|
||||
.rgb_coefficient.coeff_b = {{85, 0}},
|
||||
.window_weight = {
|
||||
{{16, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
},
|
||||
};
|
||||
|
||||
isp_hist_ctlr_t hist_ctlr[SOC_ISP_HIST_CTLR_NUMS + 1] = {};
|
||||
for (int i = 0; i < SOC_ISP_HIST_CTLR_NUMS; i++) {
|
||||
TEST_ESP_OK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr[i]));
|
||||
}
|
||||
|
||||
TEST_ASSERT(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr[SOC_ISP_HIST_CTLR_NUMS]) == ESP_ERR_NOT_FOUND);
|
||||
|
||||
for (int i = 0; i < SOC_ISP_HIST_CTLR_NUMS; i++) {
|
||||
TEST_ESP_OK(esp_isp_del_hist_controller(hist_ctlr[i]));
|
||||
}
|
||||
TEST_ESP_OK(esp_isp_del_processor(isp_proc));
|
||||
}
|
||||
|
||||
@ -68,6 +68,7 @@ extern "C" {
|
||||
#define ISP_LL_EVENT_AE_MASK (ISP_LL_EVENT_AE_FDONE | ISP_LL_EVENT_AE_ENV)
|
||||
#define ISP_LL_EVENT_AWB_MASK (ISP_LL_EVENT_AWB_FDONE)
|
||||
#define ISP_LL_EVENT_SHARP_MASK (ISP_LL_EVENT_SHARP_FRAME)
|
||||
#define ISP_LL_EVENT_HIST_MASK (ISP_LL_EVENT_HIST_FDONE)
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
AF
|
||||
@ -1614,6 +1615,113 @@ static inline void isp_ll_gamma_set_correction_curve(isp_dev_t *hw, color_compon
|
||||
while (hw->gamma_ctrl.gamma_update);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
HIST
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief enable histogram clock
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] enable true: enable the clock. false: disable the clock
|
||||
*/
|
||||
static inline void isp_ll_hist_clk_enable(isp_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->clk_en.clk_hist_force_on = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram subwindow weight
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] window_weight array for window weight
|
||||
*/
|
||||
static inline void isp_ll_hist_set_subwindow_weight(isp_dev_t *hw, const isp_hist_weight_t hist_window_weight[SOC_ISP_HIST_BLOCK_X_NUMS * SOC_ISP_HIST_BLOCK_Y_NUMS])
|
||||
{
|
||||
for (int i = 0; i < SOC_ISP_HIST_BLOCK_X_NUMS * SOC_ISP_HIST_BLOCK_Y_NUMS; i++) {
|
||||
// On ESP32P4, hist_weight [7,0] are decimal
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight[i / 4], hist_weight_b[3 - (i % 4)], hist_window_weight[i].decimal);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram segment threshold
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] segment_threshold array for segment threshold
|
||||
*/
|
||||
static inline void isp_ll_hist_set_segment_threshold(isp_dev_t *hw, const uint32_t segment_threshold[SOC_ISP_HIST_INTERVAL_NUMS])
|
||||
{
|
||||
for (int i = 0; i < SOC_ISP_HIST_INTERVAL_NUMS; i++) {
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg[i / 4], hist_seg_b[3 - (i % 4)], segment_threshold[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram window range
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] x_start Top left pixel x axis value
|
||||
* @param[in] x_bsize Block size on x axis
|
||||
* @param[in] y_start Top left pixel y axis value
|
||||
* @param[in] y_bsize Block size on y axis
|
||||
*/
|
||||
static inline void isp_ll_hist_set_window_range(isp_dev_t *hw, int x_start, int x_bsize, int y_start, int y_bsize)
|
||||
{
|
||||
hw->hist_offs.hist_x_offs = x_start;
|
||||
hw->hist_offs.hist_y_offs = y_start;
|
||||
hw->hist_size.hist_x_size = x_bsize;
|
||||
hw->hist_size.hist_y_size = y_bsize;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable / Disable histogram statistic
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] enable enable/disable
|
||||
*/
|
||||
static inline void isp_ll_hist_enable(isp_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->cntl.hist_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get histogram value
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[out] histogram_value pointer to histogram result
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void isp_ll_hist_get_histogram_value(isp_dev_t *hw, uint32_t *histogram_value)
|
||||
{
|
||||
for (int i = 0; i < SOC_ISP_HIST_SEGMENT_NUMS; i++) {
|
||||
histogram_value[i] = hw->hist_binn[i].hist_bin_n;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram sampling mode
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] hist_mode histogram mode
|
||||
*/
|
||||
static inline void isp_ll_hist_set_mode(isp_dev_t *hw, isp_hist_sampling_mode_t hist_mode)
|
||||
{
|
||||
hw->hist_mode.hist_mode = hist_mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram RGB coefficients, only effect when hist_mode is ISP_HIST_SAMPLING_RGB
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] rgb_coeff RGB coefficients
|
||||
*/
|
||||
static inline void isp_ll_hist_set_rgb_coefficient(isp_dev_t *hw, const isp_hist_rgb_coefficient_t *rgb_coeff)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_r, rgb_coeff->coeff_r.decimal);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_g, rgb_coeff->coeff_g.decimal);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_b, rgb_coeff->coeff_b.decimal);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -188,6 +188,17 @@ uint32_t isp_hal_check_clear_intr_event(const isp_hal_context_t *hal, uint32_t m
|
||||
*/
|
||||
void isp_hal_sharpen_config(isp_hal_context_t *hal, isp_hal_sharpen_cfg_t *config);
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Histogram
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Configure Histogram window
|
||||
*
|
||||
* @param[in] hal Context of the HAL layer
|
||||
* @param[in] window Window info, see `isp_window_t`
|
||||
*/
|
||||
void isp_hal_hist_window_config(isp_hal_context_t *hal, const isp_window_t *window);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -23,6 +23,19 @@ typedef soc_periph_isp_clk_src_t isp_clk_src_t; ///< Clock source type of
|
||||
typedef int isp_clk_src_t; ///< Default type
|
||||
#endif
|
||||
|
||||
/*
|
||||
ISP window and subwindow
|
||||
+----------------------------------------------------------+
|
||||
| <-- top left point coordinate |
|
||||
| | subwindow[0][0] |......| subwindow[0][Y_NUM]| |
|
||||
| . |
|
||||
| . |
|
||||
| . |
|
||||
| | subwindow[X_NUM][0] |......| subwindow[X_NUM][Y_NUM]| |
|
||||
| bottom right point coordinate --> |
|
||||
+----------------------------------------------------------+
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ISP coordinate type
|
||||
*
|
||||
@ -33,8 +46,7 @@ typedef struct {
|
||||
} isp_coordinate_t;
|
||||
|
||||
/**
|
||||
* @brief ISP window type
|
||||
*
|
||||
* @brief The top left and bottom right coordinates of ISP full window
|
||||
*/
|
||||
typedef struct {
|
||||
isp_coordinate_t top_left; ///< The top left point coordinate
|
||||
@ -181,14 +193,13 @@ typedef enum {
|
||||
#define ISP_SHARPEN_M_FREQ_COEF_RES_BITS 16
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief High freq pixel sharpeness coeff
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t decimal:ISP_SHARPEN_H_FREQ_COEF_DEC_BITS; ///< Integer part
|
||||
uint32_t integer:ISP_SHARPEN_H_FREQ_COEF_INT_BITS; ///< Decimal part
|
||||
uint32_t decimal:ISP_SHARPEN_H_FREQ_COEF_DEC_BITS; ///< Decimal part
|
||||
uint32_t integer:ISP_SHARPEN_H_FREQ_COEF_INT_BITS; ///< Integer part
|
||||
uint32_t reserved:ISP_SHARPEN_H_FREQ_COEF_RES_BITS; ///< Reserved
|
||||
};
|
||||
uint32_t val; ///< 32-bit high freq pixel sharpeness coeff register value
|
||||
@ -199,8 +210,8 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t decimal:ISP_SHARPEN_M_FREQ_COEF_DEC_BITS; ///< Integer part
|
||||
uint32_t integer:ISP_SHARPEN_M_FREQ_COEF_INT_BITS; ///< Decimal part
|
||||
uint32_t decimal:ISP_SHARPEN_M_FREQ_COEF_DEC_BITS; ///< Decimal part
|
||||
uint32_t integer:ISP_SHARPEN_M_FREQ_COEF_INT_BITS; ///< Integer part
|
||||
uint32_t reserved:ISP_SHARPEN_M_FREQ_COEF_RES_BITS; ///< Reserved
|
||||
};
|
||||
uint32_t val; ///< 32-bit medium freq pixel sharpeness coeff register value
|
||||
@ -235,6 +246,87 @@ typedef struct {
|
||||
} pt[ISP_GAMMA_CURVE_POINTS_NUM]; ///< Point (x, y)
|
||||
} isp_gamma_curve_points_t;
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
HIST
|
||||
---------------------------------------------------------------*/
|
||||
#if (SOC_ISP_HIST_BLOCK_X_NUMS && SOC_ISP_HIST_BLOCK_Y_NUMS)
|
||||
#define ISP_HIST_BLOCK_X_NUM SOC_ISP_HIST_BLOCK_X_NUMS // The AF window number for sampling
|
||||
#define ISP_HIST_BLOCK_Y_NUM SOC_ISP_HIST_BLOCK_Y_NUMS // The AF window number for sampling
|
||||
#else
|
||||
#define ISP_HIST_BLOCK_X_NUM 0
|
||||
#define ISP_HIST_BLOCK_Y_NUM 0
|
||||
#endif
|
||||
|
||||
#if (SOC_ISP_HIST_SEGMENT_NUMS && SOC_ISP_HIST_INTERVAL_NUMS)
|
||||
#define ISP_HIST_SEGMENT_NUMS SOC_ISP_HIST_SEGMENT_NUMS // The segment of histogram
|
||||
#define ISP_HIST_INTERVAL_NUMS SOC_ISP_HIST_INTERVAL_NUMS // The interval of histogram
|
||||
#else
|
||||
#define ISP_HIST_SEGMENT_NUMS 0
|
||||
#define ISP_HIST_INTERVAL_NUMS 0
|
||||
#endif
|
||||
|
||||
#define ISP_HIST_WEIGHT_INT_BITS 8
|
||||
#define ISP_HIST_WEIGHT_DEC_BITS 7
|
||||
#define ISP_HIST_WEIGHT_RES_BITS 17
|
||||
#define ISP_HIST_COEFF_INT_BITS 8
|
||||
#define ISP_HIST_COEFF_DEC_BITS 7
|
||||
#define ISP_HIST_COEFF_RES_BITS 17
|
||||
|
||||
/**
|
||||
* @brief ISP histogram mode.
|
||||
*/
|
||||
typedef enum {
|
||||
ISP_HIST_SAMPLING_RAW_B, ///< histogram mode for B component of raw image
|
||||
ISP_HIST_SAMPLING_RAW_GB, ///< histogram mode for GB component of raw image
|
||||
ISP_HIST_SAMPLING_RAW_GR, ///< histogram mode for GR component of raw image
|
||||
ISP_HIST_SAMPLING_RAW_R, ///< histogram mode for R component of raw image
|
||||
ISP_HIST_SAMPLING_RGB, ///< histogram mode for RGB
|
||||
ISP_HIST_SAMPLING_YUV_Y, ///< histogram mode for Y component for YUV
|
||||
ISP_HIST_SAMPLING_YUV_U, ///< histogram mode for U component for YUV
|
||||
ISP_HIST_SAMPLING_YUV_V, ///< histogram mode for V component for YUV
|
||||
} isp_hist_sampling_mode_t;
|
||||
|
||||
/**
|
||||
* @brief ISP histogram weight value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t decimal:ISP_HIST_WEIGHT_DEC_BITS; ///< Decimal part
|
||||
uint32_t integer:ISP_HIST_WEIGHT_INT_BITS; ///< Integer part
|
||||
uint32_t reserved:ISP_HIST_WEIGHT_RES_BITS; ///< Reserved
|
||||
};
|
||||
uint32_t val; ///< 32-bit histogram weight value
|
||||
} isp_hist_weight_t;
|
||||
|
||||
/**
|
||||
* @brief ISP histogram coefficient value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t decimal:ISP_HIST_COEFF_DEC_BITS; ///< Decimal part
|
||||
uint32_t integer:ISP_HIST_COEFF_INT_BITS; ///< Integer part
|
||||
uint32_t reserved:ISP_HIST_COEFF_RES_BITS; ///< Reserved
|
||||
};
|
||||
uint32_t val; ///< 32-bit histogram coefficient value
|
||||
} isp_hist_coeff_t;
|
||||
|
||||
/**
|
||||
* @brief ISP histogram r,g,b coefficient
|
||||
*/
|
||||
typedef struct {
|
||||
isp_hist_coeff_t coeff_r; ///< R coefficient
|
||||
isp_hist_coeff_t coeff_g; ///< G coefficient
|
||||
isp_hist_coeff_t coeff_b; ///< B coefficient
|
||||
} isp_hist_rgb_coefficient_t;
|
||||
|
||||
/**
|
||||
* @brief ISP histogram result.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t hist_value[ISP_HIST_SEGMENT_NUMS]; ///< Histogram value, represents the number of pixels that the histogram window's brightness results fall into the segment X.
|
||||
} isp_hist_result_t;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -169,17 +169,18 @@ bool isp_hal_ccm_set_matrix(const isp_hal_context_t *hal, bool saturation, const
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
INTR, put in iram
|
||||
Histogram
|
||||
---------------------------------------------------------------*/
|
||||
uint32_t isp_hal_check_clear_intr_event(const isp_hal_context_t *hal, uint32_t mask)
|
||||
void isp_hal_hist_window_config(isp_hal_context_t *hal, const isp_window_t *window)
|
||||
{
|
||||
uint32_t triggered_events = isp_ll_get_intr_status(hal->hw) & mask;
|
||||
uint32_t hist_x_start = window->top_left.x;
|
||||
uint32_t hist_x_bsize = (window->btm_right.x - window-> top_left.x) / SOC_ISP_HIST_BLOCK_X_NUMS;
|
||||
|
||||
if (triggered_events) {
|
||||
isp_ll_clear_intr(hal->hw, triggered_events);
|
||||
}
|
||||
uint32_t hist_y_start = window->top_left.y;
|
||||
uint32_t hist_y_bsize = (window->btm_right.y - window->top_left.y) / SOC_ISP_HIST_BLOCK_Y_NUMS;
|
||||
|
||||
isp_ll_hist_set_window_range(hal->hw, hist_x_start, hist_x_bsize, hist_y_start, hist_y_bsize);
|
||||
|
||||
return triggered_events;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
@ -213,3 +214,17 @@ void isp_hal_sharpen_config(isp_hal_context_t *hal, isp_hal_sharpen_cfg_t *confi
|
||||
isp_ll_sharp_set_template(hal->hw, default_template);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
INTR, put in iram
|
||||
---------------------------------------------------------------*/
|
||||
uint32_t isp_hal_check_clear_intr_event(const isp_hal_context_t *hal, uint32_t mask)
|
||||
{
|
||||
uint32_t triggered_events = isp_ll_get_intr_status(hal->hw) & mask;
|
||||
|
||||
if (triggered_events) {
|
||||
isp_ll_clear_intr(hal->hw, triggered_events);
|
||||
}
|
||||
|
||||
return triggered_events;
|
||||
}
|
||||
|
||||
@ -927,6 +927,26 @@ config SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS
|
||||
int
|
||||
default 24
|
||||
|
||||
config SOC_ISP_HIST_CTLR_NUMS
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_ISP_HIST_BLOCK_X_NUMS
|
||||
int
|
||||
default 5
|
||||
|
||||
config SOC_ISP_HIST_BLOCK_Y_NUMS
|
||||
int
|
||||
default 5
|
||||
|
||||
config SOC_ISP_HIST_SEGMENT_NUMS
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_ISP_HIST_INTERVAL_NUMS
|
||||
int
|
||||
default 15
|
||||
|
||||
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -1821,6 +1821,25 @@ typedef union {
|
||||
uint32_t val;
|
||||
} isp_hist_size_reg_t;
|
||||
|
||||
/** Type of hist_seg register
|
||||
* histogram bin control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_seg: R/W;
|
||||
* default:
|
||||
* 16, 32, 48, 64,
|
||||
* 80, 96, 112, 128,
|
||||
* 144, 160, 176, 192,
|
||||
* 208, 224, 240
|
||||
* this field configures threshold of histogram
|
||||
*/
|
||||
uint8_t hist_seg_b[4];
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_seg_reg_t;
|
||||
|
||||
|
||||
/** Type of hist_seg0 register
|
||||
* histogram bin control register 0
|
||||
*/
|
||||
@ -1918,6 +1937,20 @@ typedef union {
|
||||
uint32_t val;
|
||||
} isp_hist_seg3_reg_t;
|
||||
|
||||
/** Type of hist_weight register
|
||||
* histogram sub-window weight register 0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** histogram weight : RO; bitpos: [31:0];
|
||||
* weight[12] default 232, others default 1
|
||||
* this field represents the weight of histogram subwindow, sum of all weight should be 256
|
||||
*/
|
||||
uint8_t hist_weight_b[4];
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_weight_reg_t;
|
||||
|
||||
/** Type of hist_weight0 register
|
||||
* histogram sub-window weight register 0
|
||||
*/
|
||||
@ -2584,229 +2617,19 @@ typedef union {
|
||||
uint32_t val;
|
||||
} isp_blc_mean_reg_t;
|
||||
|
||||
/** Type of hist_bin0 register
|
||||
* result of histogram bin 0
|
||||
/** Type of hist_bin register
|
||||
* result of histogram bin n
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_0 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 0
|
||||
/** hist_bin_n : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin n
|
||||
*/
|
||||
uint32_t hist_bin_0:17;
|
||||
uint32_t hist_bin_n:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin0_reg_t;
|
||||
|
||||
/** Type of hist_bin1 register
|
||||
* result of histogram bin 1
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_1 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 1
|
||||
*/
|
||||
uint32_t hist_bin_1:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin1_reg_t;
|
||||
|
||||
/** Type of hist_bin2 register
|
||||
* result of histogram bin 2
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_2 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 2
|
||||
*/
|
||||
uint32_t hist_bin_2:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin2_reg_t;
|
||||
|
||||
/** Type of hist_bin3 register
|
||||
* result of histogram bin 3
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_3 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 3
|
||||
*/
|
||||
uint32_t hist_bin_3:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin3_reg_t;
|
||||
|
||||
/** Type of hist_bin4 register
|
||||
* result of histogram bin 4
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_4 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 4
|
||||
*/
|
||||
uint32_t hist_bin_4:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin4_reg_t;
|
||||
|
||||
/** Type of hist_bin5 register
|
||||
* result of histogram bin 5
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_5 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 5
|
||||
*/
|
||||
uint32_t hist_bin_5:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin5_reg_t;
|
||||
|
||||
/** Type of hist_bin6 register
|
||||
* result of histogram bin 6
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_6 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 6
|
||||
*/
|
||||
uint32_t hist_bin_6:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin6_reg_t;
|
||||
|
||||
/** Type of hist_bin7 register
|
||||
* result of histogram bin 7
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_7 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 7
|
||||
*/
|
||||
uint32_t hist_bin_7:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin7_reg_t;
|
||||
|
||||
/** Type of hist_bin8 register
|
||||
* result of histogram bin 8
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_8 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 8
|
||||
*/
|
||||
uint32_t hist_bin_8:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin8_reg_t;
|
||||
|
||||
/** Type of hist_bin9 register
|
||||
* result of histogram bin 9
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_9 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 9
|
||||
*/
|
||||
uint32_t hist_bin_9:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin9_reg_t;
|
||||
|
||||
/** Type of hist_bin10 register
|
||||
* result of histogram bin 10
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_10 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 10
|
||||
*/
|
||||
uint32_t hist_bin_10:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin10_reg_t;
|
||||
|
||||
/** Type of hist_bin11 register
|
||||
* result of histogram bin 11
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_11 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 11
|
||||
*/
|
||||
uint32_t hist_bin_11:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin11_reg_t;
|
||||
|
||||
/** Type of hist_bin12 register
|
||||
* result of histogram bin 12
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_12 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 12
|
||||
*/
|
||||
uint32_t hist_bin_12:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin12_reg_t;
|
||||
|
||||
/** Type of hist_bin13 register
|
||||
* result of histogram bin 13
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_13 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 13
|
||||
*/
|
||||
uint32_t hist_bin_13:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin13_reg_t;
|
||||
|
||||
/** Type of hist_bin14 register
|
||||
* result of histogram bin 14
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_14 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 14
|
||||
*/
|
||||
uint32_t hist_bin_14:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin14_reg_t;
|
||||
|
||||
/** Type of hist_bin15 register
|
||||
* result of histogram bin 15
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_15 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 15
|
||||
*/
|
||||
uint32_t hist_bin_15:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin15_reg_t;
|
||||
} isp_hist_binn_reg_t;
|
||||
|
||||
/** Type of rdn_eco_cs register
|
||||
* rdn eco cs register
|
||||
@ -3437,33 +3260,9 @@ typedef struct {
|
||||
volatile isp_hist_coeff_reg_t hist_coeff;
|
||||
volatile isp_hist_offs_reg_t hist_offs;
|
||||
volatile isp_hist_size_reg_t hist_size;
|
||||
volatile isp_hist_seg0_reg_t hist_seg0;
|
||||
volatile isp_hist_seg1_reg_t hist_seg1;
|
||||
volatile isp_hist_seg2_reg_t hist_seg2;
|
||||
volatile isp_hist_seg3_reg_t hist_seg3;
|
||||
volatile isp_hist_weight0_reg_t hist_weight0;
|
||||
volatile isp_hist_weight1_reg_t hist_weight1;
|
||||
volatile isp_hist_weight2_reg_t hist_weight2;
|
||||
volatile isp_hist_weight3_reg_t hist_weight3;
|
||||
volatile isp_hist_weight4_reg_t hist_weight4;
|
||||
volatile isp_hist_weight5_reg_t hist_weight5;
|
||||
volatile isp_hist_weight6_reg_t hist_weight6;
|
||||
volatile isp_hist_bin0_reg_t hist_bin0;
|
||||
volatile isp_hist_bin1_reg_t hist_bin1;
|
||||
volatile isp_hist_bin2_reg_t hist_bin2;
|
||||
volatile isp_hist_bin3_reg_t hist_bin3;
|
||||
volatile isp_hist_bin4_reg_t hist_bin4;
|
||||
volatile isp_hist_bin5_reg_t hist_bin5;
|
||||
volatile isp_hist_bin6_reg_t hist_bin6;
|
||||
volatile isp_hist_bin7_reg_t hist_bin7;
|
||||
volatile isp_hist_bin8_reg_t hist_bin8;
|
||||
volatile isp_hist_bin9_reg_t hist_bin9;
|
||||
volatile isp_hist_bin10_reg_t hist_bin10;
|
||||
volatile isp_hist_bin11_reg_t hist_bin11;
|
||||
volatile isp_hist_bin12_reg_t hist_bin12;
|
||||
volatile isp_hist_bin13_reg_t hist_bin13;
|
||||
volatile isp_hist_bin14_reg_t hist_bin14;
|
||||
volatile isp_hist_bin15_reg_t hist_bin15;
|
||||
volatile isp_hist_seg_reg_t hist_seg[4];
|
||||
volatile isp_hist_weight_reg_t hist_weight[7];
|
||||
volatile isp_hist_binn_reg_t hist_binn[16];
|
||||
volatile isp_mem_aux_ctrl_0_reg_t mem_aux_ctrl_0;
|
||||
volatile isp_mem_aux_ctrl_1_reg_t mem_aux_ctrl_1;
|
||||
volatile isp_mem_aux_ctrl_2_reg_t mem_aux_ctrl_2;
|
||||
|
||||
@ -357,6 +357,11 @@
|
||||
#define SOC_ISP_SHARPEN_M_FREQ_COEF_INT_BITS 3
|
||||
#define SOC_ISP_SHARPEN_M_FREQ_COEF_DEC_BITS 5
|
||||
#define SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS 24
|
||||
#define SOC_ISP_HIST_CTLR_NUMS 1U
|
||||
#define SOC_ISP_HIST_BLOCK_X_NUMS 5
|
||||
#define SOC_ISP_HIST_BLOCK_Y_NUMS 5
|
||||
#define SOC_ISP_HIST_SEGMENT_NUMS 16
|
||||
#define SOC_ISP_HIST_INTERVAL_NUMS 15
|
||||
|
||||
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
||||
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
|
||||
|
||||
@ -36,6 +36,7 @@ INPUT += \
|
||||
$(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_sharpen.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_core.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_gamma.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_hist.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_jpeg/include/driver/jpeg_decode.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_jpeg/include/driver/jpeg_encode.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_ppa/include/driver/ppa.h \
|
||||
|
||||
@ -62,8 +62,9 @@ The ISP driver offers following services:
|
||||
- `Get AF statistics in one shot or continuous way <#isp-af-statistics>`__ - covers how to get AF statistics one-shot or continuously.
|
||||
- `Get AE statistics in one shot or continuous way <#isp-ae-statistics>`__ - covers how to get AE statistics one-shot or continuously.
|
||||
- `Get AWB statistics in one shot or continuous way <#isp-awb-statistics>`__ - covers how to get AWB white patches statistics one-shot or continuously.
|
||||
- `Enable BF function <#isp-bf>`__ - covers how to enable and configure BF function.
|
||||
- `Configure CCM <#isp-ccm-config>`__ - covers how to config the Color Correction Matrix.
|
||||
- `Get histogram statistics in one shot or continuous way <#isp-hist-statistics>`__ - covers how to get histogram statistics one-shot or continuously.
|
||||
- `Enable BF function <#isp_bf>`__ - covers how to enable and configure BF function.
|
||||
- `Configure CCM <#isp-ccm-config>`__ - covers how to configure the Color Correction Matrix.
|
||||
- `Enable Gamma Correction <#isp-gamma-correction>`__ - covers how to enable and configure gamma correction.
|
||||
- `Configure Sharpen <#isp-sharpen>`__ - covers how to config the Sharpen function.
|
||||
- `Register callback <#isp-callback>`__ - covers how to hook user specific code to ISP driver event callback function.
|
||||
@ -152,6 +153,49 @@ If the configurations in :cpp:type:`esp_isp_ae_config_t` is specified, users can
|
||||
|
||||
You can use the created handle to do driver enable / disable the ISP AE driver and ISP AE environment detector setup.
|
||||
|
||||
Install ISP histogram (HIST) Driver
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
ISP histogram (HIST) driver requires the configuration that specified by :cpp:type:`esp_isp_hist_config_t`.
|
||||
|
||||
If the configurations in :cpp:type:`esp_isp_hist_config_t` is specified, users can call :cpp:func:`esp_isp_new_hist_controller` to allocate and initialize an ISP Histogram processor. This function will return an ISP HIST processor handle if it runs correctly. You can take following code as reference.
|
||||
|
||||
.. list::
|
||||
|
||||
- The sum of all subwindows weight's decimal value should be 256 or the statistics will be small, and integer value should be 0.
|
||||
- The sum of all RGB coefficients' decimal value should be 256 or the statistics will be small, and integer value should be 0.
|
||||
- The segment_threshold must be 0 ~ 255 and in order
|
||||
|
||||
.. code:: c
|
||||
|
||||
esp_isp_hist_config_t hist_cfg = {
|
||||
.segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240},
|
||||
.hist_mode = ISP_HIST_SAMPLING_RGB,
|
||||
.rgb_coefficient.coeff_r = {
|
||||
.integer = 0,
|
||||
.decimal = 86,
|
||||
},
|
||||
.rgb_coefficient.coeff_g = {
|
||||
.integer = 0,
|
||||
.decimal = 85,
|
||||
},
|
||||
.rgb_coefficient.coeff_b = {
|
||||
.integer = 0,
|
||||
.decimal = 85,
|
||||
},
|
||||
.window_weight = {
|
||||
{{16, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
{{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
|
||||
},
|
||||
};
|
||||
isp_hist_ctlr_t hist_ctlr_ctlr = NULL;
|
||||
ESP_ERROR_CHECK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr));
|
||||
|
||||
You can use the created handle to do driver enable / disable the ISP HIST driver setup.
|
||||
|
||||
Uninstall ISP Driver
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
@ -172,6 +216,11 @@ UnInstall ISP AE Driver
|
||||
|
||||
If a previously installed ISP AE processor is no longer needed, it's recommended to free the resource by calling :cpp:func:`esp_isp_del_ae_controller`, it will also release the underlying hardware.
|
||||
|
||||
UnInstall ISP HIST Driver
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
If a previously installed ISP HIST processor is no longer needed, it's recommended to free the resource by calling :cpp:func:`esp_isp_del_hist_controller`, it will also release the underlying hardware.
|
||||
|
||||
|
||||
.. _isp-enable-disable:
|
||||
|
||||
@ -394,7 +443,47 @@ Note that if you want to use the continuous statistics, you need to register the
|
||||
/* Delete the awb controller and free the resources */
|
||||
ESP_ERROR_CHECK(esp_isp_del_awb_controller(awb_ctlr));
|
||||
|
||||
.. _isp-bf:
|
||||
.. _isp-hist:
|
||||
|
||||
ISP histogram Processor
|
||||
-----------------------
|
||||
|
||||
Before doing ISP histogram statistics, you need to enable the ISP histogram processor first, by calling :cpp:func:`esp_isp_hist_controller_enable`. This function:
|
||||
|
||||
* Switches the driver state from **init** to **enable**.
|
||||
|
||||
Calling :cpp:func:`esp_isp_hist_controller_disable` does the opposite, that is, put the driver back to the **init** state.
|
||||
|
||||
.. _isp-hist-statistics:
|
||||
|
||||
Histogram One-shot and Continuous Statistics
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Calling :cpp:func:`esp_isp_hist_controller_get_oneshot_statistics` to get oneshot histogram statistics result. You can take following code as reference.
|
||||
|
||||
Aside from the above oneshot API, the ISP histogram driver also provides a way to start histogram statistics continuously. Calling :cpp:func:`esp_isp_hist_controller_start_continuous_statistics` starts the continuous statistics and :cpp:func:`esp_isp_hist_controller_stop_continuous_statistics` stops it.
|
||||
|
||||
Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` callback to get the statistics result. See how to register it in `Register Event Callbacks <#isp-callback>`__
|
||||
|
||||
.. code:: c
|
||||
|
||||
static bool s_hist_scheme_on_statistics_done_callback(isp_hist_ctlr_t awb_ctrlr, const esp_isp_hist_evt_data_t *edata, void *user_data)
|
||||
{
|
||||
for(int i = 0; i < 16; i++) {
|
||||
esp_rom_printf(DRAM_STR("val %d is %x\n"), i, edata->hist_result.hist_value[i]); // get the histogram statistic value
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
esp_isp_hist_cbs_t hist_cbs = {
|
||||
.on_statistics_done = s_hist_scheme_on_statistics_done_callback,
|
||||
};
|
||||
|
||||
esp_isp_hist_register_event_callbacks(hist_ctlr, &hist_cbs, hist_ctlr);
|
||||
esp_isp_hist_controller_enable(hist_ctlr);
|
||||
|
||||
|
||||
.. _isp_bf:
|
||||
|
||||
ISP BF Processor
|
||||
~~~~~~~~~~~~~~~~
|
||||
@ -537,6 +626,8 @@ Calling :cpp:func:`esp_isp_sharpen_disable` does the opposite, that is, put the
|
||||
|
||||
Register Event Callbacks
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
After an ISP module starts up, it can generate a specific event dynamically.
|
||||
You can save your own context to callback function as well, via the parameter ``user_data``. The user data will be directly passed to the callback function.
|
||||
|
||||
.. note::
|
||||
|
||||
@ -549,8 +640,6 @@ After the ISP processor is enabled, it can generate multiple events of multiple
|
||||
|
||||
- :cpp:member:`esp_isp_evt_cbs_t::on_sharpen_frame_done`. sets a callback function for sharpen frame done. It will be called after the ISP sharpen submodule finishes its operation for one frame. The function prototype is declared in :cpp:type:`esp_isp_sharpen_callback_t`.
|
||||
|
||||
You can save your own context to :cpp:func:`esp_isp_register_event_callbacks` as well, via the parameter ``user_data``. The user data will be directly passed to the callback function.
|
||||
|
||||
Register ISP AF Environment Detector Event Callbacks
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
@ -559,8 +648,6 @@ After the ISP AF environment detector starts up, it can generate a specific even
|
||||
- :cpp:member:`esp_isp_af_env_detector_evt_cbs_t::on_env_statistics_done` sets a callback function for environment statistics done. The function prototype is declared in :cpp:type:`esp_isp_af_env_detector_callback_t`.
|
||||
- :cpp:member:`esp_isp_af_env_detector_evt_cbs_t::on_env_change` sets a callback function for environment change. The function prototype is declared in :cpp:type:`esp_isp_af_env_detector_callback_t`.
|
||||
|
||||
You can save your own context to :cpp:func:`esp_isp_af_env_detector_register_event_callbacks` as well, via the parameter ``user_data``. The user data will be directly passed to the callback function.
|
||||
|
||||
Register ISP AWB Statistics Done Event Callbacks
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
@ -568,7 +655,22 @@ After the ISP AWB controller finished statistics of white patches, it can genera
|
||||
|
||||
- :cpp:member:`esp_isp_awb_cbs_t::on_statistics_done` sets a callback function when finished statistics of the white patches. The function prototype is declared in :cpp:type:`esp_isp_awb_callback_t`.
|
||||
|
||||
You can save your own context via the parameter ``user_data`` of :cpp:func:`esp_isp_awb_register_event_callbacks`. The user data will be directly passed to the callback function.
|
||||
|
||||
Register ISP AE Environment Detector Event Callbacks
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
After the ISP AE environment detector starts up, it can generate a specific event dynamically. If you have some functions that should be called when the event happens, please hook your function to the interrupt service routine by calling :cpp:func:`esp_isp_ae_env_detector_register_event_callbacks`. All supported event callbacks are listed in :cpp:type:`esp_isp_ae_env_detector_evt_cbs_t`:
|
||||
|
||||
- :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_statistics_done` sets a callback function for environment statistics done. . The function prototype is declared in :cpp:type:`esp_isp_ae_env_detector_callback_t`.
|
||||
- :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_change` sets a callback function for environment change. . The function prototype is declared in :cpp:type:`esp_isp_ae_env_detector_callback_t`.
|
||||
|
||||
|
||||
Register ISP HIST Statistics Done Event Callbacks
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
After the ISP HIST controller finished statistics of brightness, it can generate a specific event dynamically. If you want to be informed when the statistics done event takes place, please hook your function to the interrupt service routine by calling :cpp:func:`esp_isp_hist_register_event_callbacks`. All supported event callbacks are listed in :cpp:type:`esp_isp_hist_cbs_t`:
|
||||
|
||||
- :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` sets a callback function when finished statistics of the brightness. . The function prototype is declared in :cpp:type:`esp_isp_hist_callback_t`.
|
||||
|
||||
.. _isp-thread-safety:
|
||||
|
||||
@ -621,3 +723,4 @@ API Reference
|
||||
.. include-build-file:: inc/isp_ccm.inc
|
||||
.. include-build-file:: inc/isp_sharpen.inc
|
||||
.. include-build-file:: inc/isp_gamma.inc
|
||||
.. include-build-file:: inc/isp_hist.inc
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user