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efuse(esp32-c6): Update efuse_table and rs coding error func

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KonstantinKondrashov 2022-11-18 19:26:58 +08:00
parent 4867928160
commit 0eee228700
4 changed files with 65 additions and 60 deletions
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81
components/efuse/esp32c6/esp_efuse_table.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 5b3b6e026d28aacca6dc3b96be8bd280
// md5_digest_table e3b1264d26cc94f387d58e4ba9a3677c
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -191,6 +191,10 @@ static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
{EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function,
};
static const esp_efuse_desc_t DIS_SPI_DOWNLOAD_MSPI[] = {
{EFUSE_BLK0, 45, 1}, // Represents whether the SPI0 controller is disabled in boot_mode_download,
};
static const esp_efuse_desc_t DIS_TWAI[] = {
{EFUSE_BLK0, 46, 1}, // Disable TWAI function,
};
@ -200,25 +204,17 @@ static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
};
static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
{EFUSE_BLK0, 48, 3}, // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.,
{EFUSE_BLK0, 48, 3}, // Set these bits to soft disable JTAG (odd number 1 means disable). JTAG can be enabled in HMAC module.,
};
static const esp_efuse_desc_t DIS_PAD_JTAG[] = {
{EFUSE_BLK0, 51, 1}, // Disable JTAG in the hard way. JTAG is disabled permanently.,
{EFUSE_BLK0, 51, 1}, // Hard disable JTAG. JTAG is disabled permanently.,
};
static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
{EFUSE_BLK0, 52, 1}, // Disable flash encryption when in download boot modes.,
};
static const esp_efuse_desc_t USB_DREFH[] = {
{EFUSE_BLK0, 53, 2}, // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.,
};
static const esp_efuse_desc_t USB_DREFL[] = {
{EFUSE_BLK0, 55, 2}, // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.,
};
static const esp_efuse_desc_t USB_EXCHG_PINS[] = {
{EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins,
};
@ -272,7 +268,11 @@ static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
};
static const esp_efuse_desc_t SEC_DPA_LEVEL[] = {
{EFUSE_BLK0, 112, 2}, // Configures the clock random divide mode to determine the spa secure level,
{EFUSE_BLK0, 112, 2}, // Configures the clock random divide mode to determine the DPA security level,
};
static const esp_efuse_desc_t CRYPT_DPA_ENABLE[] = {
{EFUSE_BLK0, 115, 1}, // Represents whether defense against DPA attack is enabled,
};
static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
@ -295,16 +295,16 @@ static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = {
{EFUSE_BLK0, 129, 1}, // Disable direct boot mode,
};
static const esp_efuse_desc_t DIS_USB_PRINT[] = {
{EFUSE_BLK0, 130, 1}, // Disable USB Print,
static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
{EFUSE_BLK0, 130, 1}, // Represents whether print from USB-Serial-JTAG during ROM boot is disabled,
};
static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = {
{EFUSE_BLK0, 132, 1}, // Disable download through USB,
static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
{EFUSE_BLK0, 132, 1}, // Represents whether the USB-Serial-JTAG download func- tion is disabled,
};
static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
{EFUSE_BLK0, 133, 1}, // Enable security download mode,
{EFUSE_BLK0, 133, 1}, // Enable secure download mode,
};
static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
@ -319,6 +319,10 @@ static const esp_efuse_desc_t SECURE_VERSION[] = {
{EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback,
};
static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = {
{EFUSE_BLK0, 158, 1}, // Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled,
};
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK0, 160, 1}, // Disables check of wafer version major,
};
@ -729,6 +733,11 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_SPI_DOWNLOAD_MSPI[] = {
&DIS_SPI_DOWNLOAD_MSPI[0], // Represents whether the SPI0 controller is disabled in boot_mode_download
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = {
&DIS_TWAI[0], // Disable TWAI function
NULL
@ -740,12 +749,12 @@ const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
};
const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
&SOFT_DIS_JTAG[0], // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
&SOFT_DIS_JTAG[0], // Set these bits to soft disable JTAG (odd number 1 means disable). JTAG can be enabled in HMAC module.
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
&DIS_PAD_JTAG[0], // Disable JTAG in the hard way. JTAG is disabled permanently.
&DIS_PAD_JTAG[0], // Hard disable JTAG. JTAG is disabled permanently.
NULL
};
@ -754,16 +763,6 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = {
&USB_DREFH[0], // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = {
&USB_DREFL[0], // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
&USB_EXCHG_PINS[0], // Exchange D+ D- pins
NULL
@ -830,7 +829,12 @@ const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
};
const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = {
&SEC_DPA_LEVEL[0], // Configures the clock random divide mode to determine the spa secure level
&SEC_DPA_LEVEL[0], // Configures the clock random divide mode to determine the DPA security level
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[] = {
&CRYPT_DPA_ENABLE[0], // Represents whether defense against DPA attack is enabled
NULL
};
@ -859,18 +863,18 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_PRINT[] = {
&DIS_USB_PRINT[0], // Disable USB Print
const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
&DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // Represents whether print from USB-Serial-JTAG during ROM boot is disabled
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = {
&DIS_USB_DOWNLOAD_MODE[0], // Disable download through USB
const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
&DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // Represents whether the USB-Serial-JTAG download func- tion is disabled
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
&ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode
&ENABLE_SECURITY_DOWNLOAD[0], // Enable secure download mode
NULL
};
@ -889,6 +893,11 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
&SECURE_BOOT_DISABLE_FAST_WAKE[0], // Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
&DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major
NULL

17
components/efuse/esp32c6/esp_efuse_table.csv
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@ -59,13 +59,12 @@
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode
DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, Disable USB_SERIAL_JTAG
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
DIS_SPI_DOWNLOAD_MSPI, EFUSE_BLK0, 45, 1, Represents whether the SPI0 controller is disabled in boot_mode_download
DIS_TWAI, EFUSE_BLK0, 46, 1, Disable TWAI function
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently.
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to soft disable JTAG (odd number 1 means disable). JTAG can be enabled in HMAC module.
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Hard disable JTAG. JTAG is disabled permanently.
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes.
USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins
VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio
@ -84,7 +83,8 @@
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose
SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, Configures the clock random divide mode to determine the spa secure level
SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, Configures the clock random divide mode to determine the DPA security level
CRYPT_DPA_ENABLE, EFUSE_BLK0, 115, 1, Represents whether defense against DPA attack is enabled
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke
FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
@ -92,12 +92,13 @@
# EFUSE_RD_REPEAT_DATA3_REG #
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode
DIS_USB_PRINT, EFUSE_BLK0, 130, 1, Disable USB Print
DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Disable download through USB
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Represents whether print from USB-Serial-JTAG during ROM boot is disabled
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Represents whether the USB-Serial-JTAG download func- tion is disabled
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable secure download mode
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 158, 1, Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled
# EFUSE_RD_REPEAT_DATA4_REG #
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major

Can't render this file because it contains an unexpected character in line 7 and column 87.

13
components/efuse/esp32c6/include/esp_efuse_table.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,7 +10,7 @@ extern "C" {
#include "esp_efuse.h"
// md5_digest_table 5b3b6e026d28aacca6dc3b96be8bd280
// md5_digest_table e3b1264d26cc94f387d58e4ba9a3677c
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -61,13 +61,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SPI_DOWNLOAD_MSPI[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[];
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
@ -82,17 +81,19 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_PRINT[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];

14
components/hal/esp32c6/efuse_hal.c
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@ -78,17 +78,11 @@ bool efuse_hal_is_coding_error_in_block(unsigned block)
}
}
} else if (block <= 10) {
// The order of error in these regs is different only for the C3 chip.
// Fail bit (mask=0x8):
// EFUSE_RD_RS_ERR0_REG: (hi) BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1, ------ (low)
// EFUSE_RD_RS_ERR1_REG: BLOCK9, BLOCK8
// Error num bits (mask=0x7):
// EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
// EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
// BLOCK10 is not presented in the error regs.
uint32_t err_fail_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
uint32_t err_num_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + ((block - 1) / 8) * 4);
return (ESP_EFUSE_BLOCK_ERROR_BITS(err_fail_reg, block % 8) != 0) || (ESP_EFUSE_BLOCK_ERROR_NUM_BITS(err_num_reg, (block - 1) % 8) != 0);
// EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
block--;
uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
}
return false;
}