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rename APB_CTRL ro SYS_CON

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This commit is contained in:
Wu Zheng Hui 2021-09-16 20:57:57 +08:00 committed by Jiang Jiang Jian
parent b59902f4d1
commit 1080e4f6a2
35 changed files with 467 additions and 1381 deletions
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6
components/bootloader_support/src/bootloader_efuse_esp32.c
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@ -7,14 +7,14 @@
#include "bootloader_common.h"
#include "bootloader_clock.h"
#include "soc/efuse_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
uint8_t bootloader_common_get_chip_revision(void)
{
uint8_t eco_bit0, eco_bit1, eco_bit2;
eco_bit0 = (REG_READ(EFUSE_BLK0_RDATA3_REG) & 0xF000) >> 15;
eco_bit1 = (REG_READ(EFUSE_BLK0_RDATA5_REG) & 0x100000) >> 20;
eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 0x80000000) >> 31;
eco_bit2 = (REG_READ(SYSCON_DATE_REG) & 0x80000000) >> 31;
uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
uint8_t chip_ver = 0;
switch (combine_value) {
@ -28,7 +28,7 @@ uint8_t bootloader_common_get_chip_revision(void)
chip_ver = 2;
break;
#if CONFIG_IDF_ENV_FPGA
case 4: /* Empty efuses, but APB_CTRL_DATE_REG bit is set */
case 4: /* Empty efuses, but SYSCON_DATE_REG bit is set */
chip_ver = 3;
break;
#endif

4
components/driver/test/adc_dma_test/test_esp32s2.c
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@ -41,8 +41,8 @@ static const char *TAG = "test_adc";
#define PLATFORM_SELECT (1) //0: pxp; 1: chip
#if (PLATFORM_SELECT == 0) //PXP platform
#include "soc/apb_ctrl_reg.h"
#define SET_BREAK_POINT(flag) REG_WRITE(APB_CTRL_DATE_REG, flag)
#include "soc/syscon_reg.h"
#define SET_BREAK_POINT(flag) REG_WRITE(SYSCON_DATE_REG, flag)
//PXP clk is slower.
#define SYS_DELAY_TIME_MOM (1/40)
#define RTC_SLOW_CLK_FLAG 1 // Slow clock is 32KHz.

4
components/driver/test/dac_dma_test/test_esp32s2.c
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@ -40,8 +40,8 @@ static const char *TAG = "test_adc";
#define PLATFORM_SELECT (1) //0: pxp; 1: chip
#if (PLATFORM_SELECT == 0) //PXP platform
#include "soc/apb_ctrl_reg.h"
#define SET_BREAK_POINT(flag) REG_WRITE(APB_CTRL_DATE_REG, flag)
#include "soc/syscon_reg.h"
#define SET_BREAK_POINT(flag) REG_WRITE(SYSCON_DATE_REG, flag)
//PXP clk is slower.
#define SYS_DELAY_TIME_MOM (1/40)
#define RTC_SLOW_CLK_FLAG 1 // Slow clock is 32KHz.

4
components/driver/test/touch_sensor_test/test_esp32s2.c
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@ -29,7 +29,7 @@
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/rtc_io_struct.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "driver/rtc_io.h"
#include "esp_rom_sys.h"
@ -37,7 +37,7 @@ static const char *TAG = "test_touch";
#define PLATFORM_SELECT (1) //0: pxp; 1: chip
#if (PLATFORM_SELECT == 0) //PXP platform
#define SET_BREAK_POINT(flag) REG_WRITE(APB_CTRL_DATE_REG, flag)
#define SET_BREAK_POINT(flag) REG_WRITE(SYSCON_DATE_REG, flag)
//PXP clk is slower.
#define SYS_DELAY_TIME_MOM (1/40)
#define RTC_SLOW_CLK_FLAG 1 // Slow clock is 32KHz.

4
components/efuse/esp32/esp_efuse_fields.c
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@ -15,7 +15,7 @@
#include "soc/efuse_periph.h"
#include "bootloader_random.h"
#include "sys/param.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
const static char *TAG = "efuse";
@ -27,7 +27,7 @@ uint8_t esp_efuse_get_chip_ver(void)
uint8_t eco_bit0, eco_bit1, eco_bit2;
esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1, &eco_bit0, 1);
esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV2, &eco_bit1, 1);
eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 0x80000000) >> 31;
eco_bit2 = (REG_READ(SYSCON_DATE_REG) & 0x80000000) >> 31;
uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
uint8_t chip_ver = 0;
switch (combine_value) {

2
components/efuse/src/esp_efuse_fields.c
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@ -15,7 +15,7 @@
#include "esp_log.h"
#include "soc/efuse_periph.h"
#include "bootloader_random.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "sys/param.h"
static __attribute__((unused)) const char *TAG = "efuse";

10
components/esp_hw_support/port/esp32/rtc_clk.c
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@ -17,7 +17,7 @@
#include "soc/sens_periph.h"
#include "soc/dport_reg.h"
#include "soc/efuse_periph.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "soc/gpio_struct.h"
#include "hal/cpu_hal.h"
#include "hal/gpio_ll.h"
@ -455,9 +455,9 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div)
{
ets_update_cpu_frequency(freq);
/* set divider from XTAL to APB clock */
REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, div - 1);
REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, div - 1);
/* adjust ref_tick */
REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, freq * MHZ / REF_CLK_FREQ - 1);
REG_WRITE(SYSCON_XTAL_TICK_CONF_REG, freq * MHZ / REF_CLK_FREQ - 1);
/* switch clock source */
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
rtc_clk_apb_freq_update(freq * MHZ);
@ -473,7 +473,7 @@ static void rtc_clk_cpu_freq_to_8m(void)
{
ets_update_cpu_frequency(8);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, 0);
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M);
rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
}
@ -676,7 +676,7 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config)
switch (soc_clk_sel) {
case RTC_CNTL_SOC_CLK_SEL_XTL: {
source = RTC_CPU_FREQ_SRC_XTAL;
div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT) + 1;
div = REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT) + 1;
source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
freq_mhz = source_freq_mhz / div;
}

6
components/esp_hw_support/port/esp32/rtc_clk_init.c
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@ -14,7 +14,7 @@
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
#include "soc/efuse_periph.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "hal/cpu_hal.h"
#include "regi2c_ctrl.h"
#include "soc_log.h"
@ -112,8 +112,8 @@ void rtc_clk_init(rtc_clk_config_t cfg)
rtc_clk_cpu_freq_set_config(&new_config);
/* Configure REF_TICK */
REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, xtal_freq - 1);
REG_WRITE(APB_CTRL_PLL_TICK_CONF_REG, APB_CLK_FREQ / MHZ - 1); /* Under PLL, APB frequency is always 80MHz */
REG_WRITE(SYSCON_XTAL_TICK_CONF_REG, xtal_freq - 1);
REG_WRITE(SYSCON_PLL_TICK_CONF_REG, APB_CLK_FREQ / MHZ - 1); /* Under PLL, APB frequency is always 80MHz */
/* Re-calculate the ccount to make time calculation correct. */
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );

2
components/esp_hw_support/port/esp32c3/rtc_clk_init.c
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@ -14,7 +14,7 @@
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/efuse_periph.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "hal/cpu_hal.h"
#include "regi2c_ctrl.h"
#include "soc_log.h"

2
components/esp_hw_support/port/esp32c3/rtc_pm.c
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@ -8,7 +8,7 @@
#include <assert.h>
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
typedef enum {
PM_LIGHT_SLEEP = BIT(2), /*!< WiFi PD, memory in light sleep */

16
components/esp_hw_support/port/esp32c3/rtc_sleep.c
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@ -9,7 +9,7 @@
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "soc/rtc.h"
#include "soc/i2s_reg.h"
#include "soc/bb_reg.h"
@ -31,9 +31,9 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
{
REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
@ -42,14 +42,14 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
if (cfg.sram_fpu) {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, APB_CTRL_SRAM_POWER_UP);
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
} else {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, 0);
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0);
}
if (cfg.rom_ram_fpu) {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_ROM_POWER_UP, APB_CTRL_ROM_POWER_UP);
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, SYSCON_ROM_POWER_UP);
} else {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_ROM_POWER_UP, 0);
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0);
}
}

2
components/esp_hw_support/port/esp32h2/rtc_clk_init.c
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@ -17,7 +17,7 @@
#include "soc/rtc_periph.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/efuse_periph.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "hal/cpu_hal.h"
#include "regi2c_ctrl.h"
#include "soc_log.h"

2
components/esp_hw_support/port/esp32h2/rtc_pm.c
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@ -8,7 +8,7 @@
#include <assert.h>
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
typedef enum {
PM_LIGHT_SLEEP = BIT(2), /*!< WiFi PD, memory in light sleep */

16
components/esp_hw_support/port/esp32h2/rtc_sleep.c
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@ -9,7 +9,7 @@
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "soc/i2s_reg.h"
#include "soc/bb_reg.h"
#include "soc/nrx_reg.h"
@ -34,9 +34,9 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
{
REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
@ -45,14 +45,14 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
if (cfg.sram_fpu) {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, APB_CTRL_SRAM_POWER_UP);
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
} else {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, 0);
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0);
}
if (cfg.rom_ram_fpu) {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_ROM_POWER_UP, APB_CTRL_ROM_POWER_UP);
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, SYSCON_ROM_POWER_UP);
} else {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_ROM_POWER_UP, 0);
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0);
}
}

4
components/esp_hw_support/port/esp32s2/regi2c_ctrl.c
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@ -5,11 +5,11 @@
*/
#include "soc/soc.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "regi2c_ctrl.h"
#include "regi2c_brownout.h"
#define I2C_RTC_WIFI_CLK_EN (APB_CTRL_WIFI_CLK_EN_REG)
#define I2C_RTC_WIFI_CLK_EN (SYSCON_WIFI_CLK_EN_REG)
#define I2C_RTC_CLK_GATE_EN (BIT(18))
#define I2C_RTC_CLK_GATE_EN_M (BIT(18))

2
components/esp_hw_support/port/esp32s2/rtc_clk_init.c
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@ -14,7 +14,7 @@
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
#include "soc/efuse_periph.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "hal/cpu_hal.h"
#include "regi2c_ctrl.h"
#include "soc_log.h"

2
components/esp_hw_support/port/esp32s2/rtc_pm.c
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@ -8,7 +8,7 @@
#include <assert.h>
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
typedef enum {
PM_LIGHT_SLEEP = BIT(2), /*!< WiFi PD, memory in light sleep */

8
components/esp_hw_support/port/esp32s2/rtc_sleep.c
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@ -8,7 +8,7 @@
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "soc/dport_reg.h"
#include "soc/rtc.h"
#include "soc/i2s_reg.h"
@ -32,9 +32,9 @@ void rtc_sleep_pd(rtc_sleep_pd_config_t cfg)
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_PLC_MEM_FORCE_PU, cfg.i2s_fpu);
REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_FIFO_FORCE_PU, cfg.i2s_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);

2
components/esp_hw_support/port/esp32s2/spiram_psram.c
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@ -25,7 +25,7 @@
#include "soc/efuse_periph.h"
#include "soc/soc_caps.h"
#include "soc/io_mux_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "soc/efuse_reg.h"
#include "soc/soc.h"
#include "driver/gpio.h"

2
components/esp_hw_support/port/esp32s3/opiram_psram.c
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@ -18,7 +18,7 @@
#include "esp32s3/rom/cache.h"
#include "soc/io_mux_reg.h"
#include "soc/dport_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/efuse_reg.h"
#include "driver/gpio.h"

2
components/esp_hw_support/port/esp32s3/rtc_clk_init.c
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@ -12,7 +12,7 @@
#include "esp32s3/rom/rtc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "hal/cpu_hal.h"
#include "regi2c_ctrl.h"
#include "soc_log.h"

4
components/esp_hw_support/port/esp32s3/rtc_init.c
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@ -10,7 +10,7 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/dport_reg.h"
#include "soc/gpio_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "soc/spi_mem_reg.h"
#include "soc/extmem_reg.h"
#include "soc/syscon_reg.h"
@ -94,7 +94,7 @@ void rtc_init(rtc_config_t cfg)
//clear CMMU clock force on
CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON);
//clear clkgate force on
REG_WRITE(APB_CTRL_CLKGATE_FORCE_ON_REG, 0);
REG_WRITE(SYSCON_CLKGATE_FORCE_ON_REG, 0);
//clear tag clock force on
CLEAR_PERI_REG_MASK(EXTMEM_DCACHE_TAG_POWER_CTRL_REG, EXTMEM_DCACHE_TAG_MEM_FORCE_ON);
CLEAR_PERI_REG_MASK(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_ICACHE_TAG_MEM_FORCE_ON);

2
components/esp_hw_support/port/esp32s3/rtc_pm.c
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@ -8,7 +8,7 @@
#include <assert.h>
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
typedef enum {
PM_LIGHT_SLEEP = BIT(2), /*!< WiFi PD, memory in light sleep */

16
components/esp_hw_support/port/esp32s3/rtc_sleep.c
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@ -8,7 +8,7 @@
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "soc/dport_reg.h"
#include "soc/rtc.h"
#include "soc/i2s_reg.h"
@ -32,9 +32,9 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
@ -44,14 +44,14 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
#endif
if (cfg.sram_fpu) {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, APB_CTRL_SRAM_POWER_UP);
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
} else {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, 0);
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0);
}
if (cfg.rom_ram_fpu) {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_ROM_POWER_UP, APB_CTRL_ROM_POWER_UP);
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, SYSCON_ROM_POWER_UP);
} else {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_ROM_POWER_UP, 0);
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0);
}
}

2
components/esp_hw_support/port/esp32s3/spiram_psram.c
View File

@ -26,7 +26,7 @@
#include "soc/efuse_periph.h"
#include "soc/soc_caps.h"
#include "soc/io_mux_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#include "soc/efuse_reg.h"
#include "soc/soc.h"
#include "soc/io_mux_reg.h"

4
components/hal/esp32c3/include/hal/rtc_cntl_ll.h
View File

@ -17,7 +17,7 @@
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#ifdef __cplusplus
extern "C" {
@ -49,7 +49,7 @@ static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void)
static inline void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr)
{
REG_SET_FIELD(APB_CTRL_RETENTION_CTRL_REG, APB_CTRL_RETENTION_LINK_ADDR, (uint32_t)addr);
REG_SET_FIELD(SYSCON_RETENTION_CTRL_REG, SYSCON_RETENTION_LINK_ADDR, (uint32_t)addr);
}
static inline void rtc_cntl_ll_enable_cpu_retention_clock(void)

2
components/hal/esp32h2/include/hal/rtc_cntl_ll.h
View File

@ -17,7 +17,7 @@
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/syscon_reg.h"
#ifdef __cplusplus
extern "C" {

28
components/soc/esp32c3/include/soc/syscon_struct.h
View File

@ -20,23 +20,23 @@ extern "C" {
typedef volatile struct syscon_dev_s {
union {
struct {
uint32_t apb_ctrl_pre_div_cnt: 10;
uint32_t apb_ctrl_clk_320m_en: 1;
uint32_t clk_en: 1;
uint32_t apb_ctrl_rst_tick_cnt: 1;
uint32_t reserved13: 19;
uint32_t pre_div_cnt: 10;
uint32_t clk_320m_en: 1;
uint32_t clk_en: 1;
uint32_t rst_tick_cnt: 1;
uint32_t reserved13: 19;
};
uint32_t val;
} apb_ctrl_sysclk_conf;
} sysclk_conf;
union {
struct {
uint32_t apb_ctrl_xtal_tick_num: 8;
uint32_t apb_ctrl_ck8m_tick_num: 8;
uint32_t apb_ctrl_tick_enable: 1;
uint32_t reserved17: 15;
uint32_t xtal_tick_num: 8;
uint32_t ck8m_tick_num: 8;
uint32_t tick_enable: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} apb_ctrl_tick_conf;
} tick_conf;
union {
struct {
uint32_t clk20_oen: 1;
@ -53,7 +53,7 @@ typedef volatile struct syscon_dev_s {
uint32_t reserved11: 21;
};
uint32_t val;
} apb_ctrl_clk_out_en;
} clk_out_en;
uint32_t wifi_bb_cfg; /**/
uint32_t wifi_bb_cfg_2; /**/
uint32_t wifi_clk_en; /**/
@ -161,7 +161,7 @@ typedef volatile struct syscon_dev_s {
uint32_t reserved1: 31;
};
uint32_t val;
} apb_ctrl_sdio_ctrl;
} sdio_ctrl;
union {
struct {
uint32_t redcy_sig0: 31;
@ -472,7 +472,7 @@ typedef volatile struct syscon_dev_s {
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t apb_ctrl_date; /*Version control*/
uint32_t date; /*Version control*/
} syscon_dev_t;
extern syscon_dev_t SYSCON;
#ifdef __cplusplus

486
components/soc/esp32h2/include/soc/apb_ctrl_reg.h
View File

@ -1,486 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_APB_CTRL_REG_H_
#define _SOC_APB_CTRL_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x00C)
/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_S 0
#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x010)
/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_2_S 0
#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x01C)
/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define APB_CTRL_PERI_IO_SWAP 0x000000FF
#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
#define APB_CTRL_PERI_IO_SWAP_V 0xFF
#define APB_CTRL_PERI_IO_SWAP_S 0
#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x020)
/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0))
#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0))
#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1
#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0
#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x028)
/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
/*description: */
#define APB_CTRL_FLASH_ACE0_ATTR 0x00000003
#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
#define APB_CTRL_FLASH_ACE0_ATTR_V 0x3
#define APB_CTRL_FLASH_ACE0_ATTR_S 0
#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x02C)
/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
/*description: */
#define APB_CTRL_FLASH_ACE1_ATTR 0x00000003
#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
#define APB_CTRL_FLASH_ACE1_ATTR_V 0x3
#define APB_CTRL_FLASH_ACE1_ATTR_S 0
#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x030)
/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
/*description: */
#define APB_CTRL_FLASH_ACE2_ATTR 0x00000003
#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
#define APB_CTRL_FLASH_ACE2_ATTR_V 0x3
#define APB_CTRL_FLASH_ACE2_ATTR_S 0
#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x034)
/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
/*description: */
#define APB_CTRL_FLASH_ACE3_ATTR 0x00000003
#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
#define APB_CTRL_FLASH_ACE3_ATTR_V 0x3
#define APB_CTRL_FLASH_ACE3_ATTR_S 0
#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x038)
/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x03C)
/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x040)
/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x044)
/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x048)
/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
/*description: */
#define APB_CTRL_FLASH_ACE0_SIZE 0x00001FFF
#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
#define APB_CTRL_FLASH_ACE0_SIZE_V 0x1FFF
#define APB_CTRL_FLASH_ACE0_SIZE_S 0
#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x04C)
/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
/*description: */
#define APB_CTRL_FLASH_ACE1_SIZE 0x00001FFF
#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
#define APB_CTRL_FLASH_ACE1_SIZE_V 0x1FFF
#define APB_CTRL_FLASH_ACE1_SIZE_S 0
#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x050)
/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
/*description: */
#define APB_CTRL_FLASH_ACE2_SIZE 0x00001FFF
#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
#define APB_CTRL_FLASH_ACE2_SIZE_V 0x1FFF
#define APB_CTRL_FLASH_ACE2_SIZE_S 0
#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x054)
/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
/*description: */
#define APB_CTRL_FLASH_ACE3_SIZE 0x00001FFF
#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
#define APB_CTRL_FLASH_ACE3_SIZE_V 0x1FFF
#define APB_CTRL_FLASH_ACE3_SIZE_S 0
#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x088)
/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F
#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F
#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2
/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1))
#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1))
#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1
#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1
/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0))
#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0))
#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1
#define APB_CTRL_SPI_MEM_REJECT_INT_S 0
#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x08C)
/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0
#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x090)
/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0))
#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0))
#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1
#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x094)
/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define APB_CTRL_REDCY_ANDOR (BIT(31))
#define APB_CTRL_REDCY_ANDOR_M (BIT(31))
#define APB_CTRL_REDCY_ANDOR_V 0x1
#define APB_CTRL_REDCY_ANDOR_S 31
/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: */
#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG0_S 0
#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x098)
/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define APB_CTRL_REDCY_NANDOR (BIT(31))
#define APB_CTRL_REDCY_NANDOR_M (BIT(31))
#define APB_CTRL_REDCY_NANDOR_V 0x1
#define APB_CTRL_REDCY_NANDOR_S 31
/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: */
#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_S 0
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x09C)
/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5))
#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5))
#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1
#define APB_CTRL_DC_MEM_FORCE_PD_S 5
/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_DC_MEM_FORCE_PU_S 4
/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3))
#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3))
#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1
#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3
/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2))
#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2))
#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1
#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2
/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1))
#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1))
#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1
#define APB_CTRL_AGC_MEM_FORCE_PD_S 1
/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
#define APB_CTRL_RETENTION_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0A0)
/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27))
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27))
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27
#define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_APB_CTRL_BASE + 0x0A4)
/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
/*description: */
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x0000000F
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0xF
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 2
/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
/*description: */
#define APB_CTRL_ROM_CLKGATE_FORCE_ON 0x00000003
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V 0x3
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S 0
#define APB_CTRL_MEM_POWER_DOWN_REG (DR_REG_APB_CTRL_BASE + 0x0A8)
/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */
/*description: */
#define APB_CTRL_SRAM_POWER_DOWN 0x0000000F
#define APB_CTRL_SRAM_POWER_DOWN_M ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
#define APB_CTRL_SRAM_POWER_DOWN_V 0xF
#define APB_CTRL_SRAM_POWER_DOWN_S 2
/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: */
#define APB_CTRL_ROM_POWER_DOWN 0x00000003
#define APB_CTRL_ROM_POWER_DOWN_M ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
#define APB_CTRL_ROM_POWER_DOWN_V 0x3
#define APB_CTRL_ROM_POWER_DOWN_S 0
#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_APB_CTRL_BASE + 0x0AC)
/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
/*description: */
#define APB_CTRL_SRAM_POWER_UP 0x0000000F
#define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
#define APB_CTRL_SRAM_POWER_UP_V 0xF
#define APB_CTRL_SRAM_POWER_UP_S 2
/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
/*description: */
#define APB_CTRL_ROM_POWER_UP 0x00000003
#define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
#define APB_CTRL_ROM_POWER_UP_V 0x3
#define APB_CTRL_ROM_POWER_UP_S 0
#define APB_CTRL_RND_DATA_REG (DR_REG_APB_CTRL_BASE + 0x0B0)
/* APB_CTRL_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define APB_CTRL_RND_DATA 0xFFFFFFFF
#define APB_CTRL_RND_DATA_M ((APB_CTRL_RND_DATA_V)<<(APB_CTRL_RND_DATA_S))
#define APB_CTRL_RND_DATA_V 0xFFFFFFFF
#define APB_CTRL_RND_DATA_S 0
#define APB_CTRL_PERI_BACKUP_CONFIG_REG (DR_REG_APB_CTRL_BASE + 0x0B4)
/* APB_CTRL_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_ENA (BIT(31))
#define APB_CTRL_PERI_BACKUP_ENA_M (BIT(31))
#define APB_CTRL_PERI_BACKUP_ENA_V 0x1
#define APB_CTRL_PERI_BACKUP_ENA_S 31
/* APB_CTRL_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_TO_MEM (BIT(30))
#define APB_CTRL_PERI_BACKUP_TO_MEM_M (BIT(30))
#define APB_CTRL_PERI_BACKUP_TO_MEM_V 0x1
#define APB_CTRL_PERI_BACKUP_TO_MEM_S 30
/* APB_CTRL_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_START (BIT(29))
#define APB_CTRL_PERI_BACKUP_START_M (BIT(29))
#define APB_CTRL_PERI_BACKUP_START_V 0x1
#define APB_CTRL_PERI_BACKUP_START_S 29
/* APB_CTRL_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_SIZE 0x000003FF
#define APB_CTRL_PERI_BACKUP_SIZE_M ((APB_CTRL_PERI_BACKUP_SIZE_V)<<(APB_CTRL_PERI_BACKUP_SIZE_S))
#define APB_CTRL_PERI_BACKUP_SIZE_V 0x3FF
#define APB_CTRL_PERI_BACKUP_SIZE_S 19
/* APB_CTRL_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_TOUT_THRES 0x000003FF
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_M ((APB_CTRL_PERI_BACKUP_TOUT_THRES_V)<<(APB_CTRL_PERI_BACKUP_TOUT_THRES_S))
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_V 0x3FF
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_S 9
/* APB_CTRL_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT 0x0000001F
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S))
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V 0x1F
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S 4
/* APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE (BIT(3))
#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE_M (BIT(3))
#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE_V 0x1
#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE_S 3
/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:0] ;default: 3'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_FLOW_ERR 0x00000007
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_M ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S))
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V 0x7
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S 0
#define APB_CTRL_PERI_BACKUP_APB_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0B8)
/* APB_CTRL_PERI_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_APB_START_ADDR 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_APB_START_ADDR_M ((APB_CTRL_PERI_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_PERI_BACKUP_APB_START_ADDR_S))
#define APB_CTRL_PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_APB_START_ADDR_S 0
#define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0BC)
/* APB_CTRL_PERI_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR_M ((APB_CTRL_PERI_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_PERI_BACKUP_MEM_START_ADDR_S))
#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR_S 0
#define APB_CTRL_PERI_BACKUP_MAP0_REG (DR_REG_APB_CTRL_BASE + 0x0C0)
/* APB_CTRL_PERI_BACKUP_MAP0 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_MAP0 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP0_M ((APB_CTRL_PERI_BACKUP_MAP0_V)<<(APB_CTRL_PERI_BACKUP_MAP0_S))
#define APB_CTRL_PERI_BACKUP_MAP0_V 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP0_S 0
#define APB_CTRL_PERI_BACKUP_MAP1_REG (DR_REG_APB_CTRL_BASE + 0x0C4)
/* APB_CTRL_PERI_BACKUP_MAP1 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_MAP1 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP1_M ((APB_CTRL_PERI_BACKUP_MAP1_V)<<(APB_CTRL_PERI_BACKUP_MAP1_S))
#define APB_CTRL_PERI_BACKUP_MAP1_V 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP1_S 0
#define APB_CTRL_PERI_BACKUP_MAP2_REG (DR_REG_APB_CTRL_BASE + 0x0C8)
/* APB_CTRL_PERI_BACKUP_MAP2 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_MAP2 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP2_M ((APB_CTRL_PERI_BACKUP_MAP2_V)<<(APB_CTRL_PERI_BACKUP_MAP2_S))
#define APB_CTRL_PERI_BACKUP_MAP2_V 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP2_S 0
#define APB_CTRL_PERI_BACKUP_MAP3_REG (DR_REG_APB_CTRL_BASE + 0x0CC)
/* APB_CTRL_PERI_BACKUP_MAP3 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_MAP3 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP3_M ((APB_CTRL_PERI_BACKUP_MAP3_V)<<(APB_CTRL_PERI_BACKUP_MAP3_S))
#define APB_CTRL_PERI_BACKUP_MAP3_V 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP3_S 0
#define APB_CTRL_PERI_BACKUP_INT_RAW_REG (DR_REG_APB_CTRL_BASE + 0x0D0)
/* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_M (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_V 0x1
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_S 1
/* APB_CTRL_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_M (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V 0x1
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S 0
#define APB_CTRL_PERI_BACKUP_INT_ST_REG (DR_REG_APB_CTRL_BASE + 0x0D4)
/* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_M (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_V 0x1
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_S 1
/* APB_CTRL_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_M (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V 0x1
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S 0
#define APB_CTRL_PERI_BACKUP_INT_ENA_REG (DR_REG_APB_CTRL_BASE + 0x0D8)
/* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_M (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_V 0x1
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_S 1
/* APB_CTRL_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_M (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V 0x1
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S 0
#define APB_CTRL_PERI_BACKUP_INT_CLR_REG (DR_REG_APB_CTRL_BASE + 0x0DC)
/* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_M (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_V 0x1
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_S 1
/* APB_CTRL_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_M (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V 0x1
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S 0
#define APB_CTRL_CLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0E0)
/* APB_CTRL_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_CLK_EN (BIT(0))
#define APB_CTRL_CLK_EN_M (BIT(0))
#define APB_CTRL_CLK_EN_V 0x1
#define APB_CTRL_CLK_EN_S 0
#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC)
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101050 ; */
/*description: Version control*/
#define APB_CTRL_DATE 0xFFFFFFFF
#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
#define APB_CTRL_DATE_V 0xFFFFFFFF
#define APB_CTRL_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_CTRL_REG_H_ */

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components/soc/esp32h2/include/soc/apb_ctrl_struct.h
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@ -1,454 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_APB_CTRL_STRUCT_H_
#define _SOC_APB_CTRL_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct apb_ctrl_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
uint32_t wifi_bb_cfg; /**/
uint32_t wifi_bb_cfg_2; /**/
uint32_t reserved_14;
uint32_t reserved_18;
union {
struct {
uint32_t peri_io_swap: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} host_inf_sel;
union {
struct {
uint32_t ext_mem_pms_lock: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} ext_mem_pms_lock;
uint32_t reserved_24;
union {
struct {
uint32_t flash_ace0_attr: 2;
uint32_t reserved2: 30;
};
uint32_t val;
} flash_ace0_attr;
union {
struct {
uint32_t flash_ace1_attr: 2;
uint32_t reserved2: 30;
};
uint32_t val;
} flash_ace1_attr;
union {
struct {
uint32_t flash_ace2_attr: 2;
uint32_t reserved2: 30;
};
uint32_t val;
} flash_ace2_attr;
union {
struct {
uint32_t flash_ace3_attr: 2;
uint32_t reserved2: 30;
};
uint32_t val;
} flash_ace3_attr;
uint32_t flash_ace0_addr; /**/
uint32_t flash_ace1_addr; /**/
uint32_t flash_ace2_addr; /**/
uint32_t flash_ace3_addr; /**/
union {
struct {
uint32_t flash_ace0_size:13;
uint32_t reserved13: 19;
};
uint32_t val;
} flash_ace0_size;
union {
struct {
uint32_t flash_ace1_size:13;
uint32_t reserved13: 19;
};
uint32_t val;
} flash_ace1_size;
union {
struct {
uint32_t flash_ace2_size:13;
uint32_t reserved13: 19;
};
uint32_t val;
} flash_ace2_size;
union {
struct {
uint32_t flash_ace3_size:13;
uint32_t reserved13: 19;
};
uint32_t val;
} flash_ace3_size;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
union {
struct {
uint32_t spi_mem_reject_int: 1;
uint32_t spi_mem_reject_clr: 1;
uint32_t spi_mem_reject_cde: 5;
uint32_t reserved7: 25;
};
uint32_t val;
} spi_mem_pms_ctrl;
uint32_t spi_mem_reject_addr; /**/
union {
struct {
uint32_t sdio_win_access_en: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} sdio_ctrl;
union {
struct {
uint32_t redcy_sig0: 31;
uint32_t redcy_andor: 1;
};
uint32_t val;
} redcy_sig0;
union {
struct {
uint32_t redcy_sig1: 31;
uint32_t redcy_nandor: 1;
};
uint32_t val;
} redcy_sig1;
union {
struct {
uint32_t agc_mem_force_pu: 1;
uint32_t agc_mem_force_pd: 1;
uint32_t pbus_mem_force_pu: 1;
uint32_t pbus_mem_force_pd: 1;
uint32_t dc_mem_force_pu: 1;
uint32_t dc_mem_force_pd: 1;
uint32_t reserved6: 26;
};
uint32_t val;
} front_end_mem_pd;
union {
struct {
uint32_t reserved0: 27;
uint32_t nobypass_cpu_iso_rst: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} retention_ctrl;
union {
struct {
uint32_t rom_clkgate_force_on: 2;
uint32_t sram_clkgate_force_on: 4;
uint32_t reserved6: 26;
};
uint32_t val;
} clkgate_force_on;
union {
struct {
uint32_t rom_power_down: 2;
uint32_t sram_power_down: 4;
uint32_t reserved6: 26;
};
uint32_t val;
} mem_power_down;
union {
struct {
uint32_t rom_power_up: 2;
uint32_t sram_power_up: 4;
uint32_t reserved6: 26;
};
uint32_t val;
} mem_power_up;
uint32_t rnd_data; /**/
union {
struct {
uint32_t peri_backup_flow_err: 3;
uint32_t peri_backup_addr_map_mode: 1;
uint32_t peri_backup_burst_limit: 5;
uint32_t peri_backup_tout_thres: 10;
uint32_t peri_backup_size: 10;
uint32_t peri_backup_start: 1;
uint32_t peri_backup_to_mem: 1;
uint32_t peri_backup_ena: 1;
};
uint32_t val;
} peri_backup_config;
uint32_t peri_backup_addr; /**/
uint32_t peri_backup_mem_addr; /**/
uint32_t peri_backup_map0; /**/
uint32_t peri_backup_map1; /**/
uint32_t peri_backup_map2; /**/
uint32_t peri_backup_map3; /**/
union {
struct {
uint32_t peri_backup_done: 1;
uint32_t peri_backup_err: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} peri_backup_int_raw;
union {
struct {
uint32_t peri_backup_done: 1;
uint32_t peri_backup_err: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} peri_backup_int_st;
union {
struct {
uint32_t peri_backup_done: 1;
uint32_t peri_backup_err: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} peri_backup_int_ena;
union {
struct {
uint32_t peri_backup_done: 1;
uint32_t peri_backup_err: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} peri_backup_int_clr;
union {
struct {
uint32_t clk_en: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} ctrlclk_conf;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t date; /*Version control*/
} apb_ctrl_dev_t;
extern apb_ctrl_dev_t APB_CTRL;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_APB_CTRL_STRUCT_H_ */

1
components/soc/esp32h2/include/soc/soc.h
View File

@ -79,7 +79,6 @@
#define DR_REG_SPI2_BASE 0x60024000
#define DR_REG_SPI3_BASE 0x60025000
#define DR_REG_SYSCON_BASE 0x60026000
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
#define DR_REG_I2C1_EXT_BASE 0x60027000
#define DR_REG_SDMMC_BASE 0x60028000
#define DR_REG_CAN_BASE 0x6002B000

6
components/soc/esp32h2/include/soc/syscon_struct.h
View File

@ -128,7 +128,7 @@ typedef volatile struct syscon_dev_s {
uint32_t reserved1: 31;
};
uint32_t val;
} apb_ctrl_sdio_ctrl;
} sdio_ctrl;
union {
struct {
uint32_t redcy_sig0: 31;
@ -245,7 +245,7 @@ typedef volatile struct syscon_dev_s {
uint32_t reserved1: 31;
};
uint32_t val;
} apb_ctrlclk_conf;
} clk_conf;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
@ -444,7 +444,7 @@ typedef volatile struct syscon_dev_s {
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t apb_ctrl_date; /*Version control*/
uint32_t date; /*Version control*/
} syscon_dev_t;
extern syscon_dev_t SYSCON;
#ifdef __cplusplus

6
components/soc/esp32s2/include/soc/syscon_struct.h
View File

@ -29,7 +29,7 @@ typedef volatile struct syscon_dev_s {
uint32_t reserved16: 16;
};
uint32_t val;
} apb_ctrl_sysclk_conf;
} sysclk_conf;
union {
struct {
uint32_t xtal_tick: 8;
@ -38,7 +38,7 @@ typedef volatile struct syscon_dev_s {
uint32_t reserved17: 15;
};
uint32_t val;
} apb_ctrl_tick_conf;
} tick_conf;
union {
struct {
uint32_t clk20_oen: 1;
@ -55,7 +55,7 @@ typedef volatile struct syscon_dev_s {
uint32_t reserved11: 21;
};
uint32_t val;
} apb_ctrl_clk_out_en;
} clk_out_en;
union {
struct {
uint32_t peri_io_swap: 8;

465
components/soc/esp32s3/include/soc/syscon_reg.h
View File

@ -20,148 +20,148 @@
extern "C" {
#endif
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000)
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define SYSCON_RST_TICK_CNT (BIT(12))
/*description: .*/
#define SYSCON_RST_TICK_CNT (BIT(12))
#define SYSCON_RST_TICK_CNT_M (BIT(12))
#define SYSCON_RST_TICK_CNT_V 0x1
#define SYSCON_RST_TICK_CNT_S 12
/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define SYSCON_CLK_EN (BIT(11))
/*description: .*/
#define SYSCON_CLK_EN (BIT(11))
#define SYSCON_CLK_EN_M (BIT(11))
#define SYSCON_CLK_EN_V 0x1
#define SYSCON_CLK_EN_S 11
/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define SYSCON_CLK_320M_EN (BIT(10))
/*description: .*/
#define SYSCON_CLK_320M_EN (BIT(10))
#define SYSCON_CLK_320M_EN_M (BIT(10))
#define SYSCON_CLK_320M_EN_V 0x1
#define SYSCON_CLK_320M_EN_S 10
/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
/*description: */
#define SYSCON_PRE_DIV_CNT 0x000003FF
/*description: .*/
#define SYSCON_PRE_DIV_CNT 0x000003FF
#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
#define SYSCON_PRE_DIV_CNT_V 0x3FF
#define SYSCON_PRE_DIV_CNT_S 0
#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004)
#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4)
/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
/*description: */
#define SYSCON_TICK_ENABLE (BIT(16))
/*description: .*/
#define SYSCON_TICK_ENABLE (BIT(16))
#define SYSCON_TICK_ENABLE_M (BIT(16))
#define SYSCON_TICK_ENABLE_V 0x1
#define SYSCON_TICK_ENABLE_S 16
/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
/*description: */
#define SYSCON_CK8M_TICK_NUM 0x000000FF
/*description: .*/
#define SYSCON_CK8M_TICK_NUM 0x000000FF
#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
#define SYSCON_CK8M_TICK_NUM_V 0xFF
#define SYSCON_CK8M_TICK_NUM_S 8
/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
/*description: */
#define SYSCON_XTAL_TICK_NUM 0x000000FF
/*description: .*/
#define SYSCON_XTAL_TICK_NUM 0x000000FF
#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
#define SYSCON_XTAL_TICK_NUM_V 0xFF
#define SYSCON_XTAL_TICK_NUM_S 0
#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008)
#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x8)
/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_XTAL_OEN (BIT(10))
/*description: .*/
#define SYSCON_CLK_XTAL_OEN (BIT(10))
#define SYSCON_CLK_XTAL_OEN_M (BIT(10))
#define SYSCON_CLK_XTAL_OEN_V 0x1
#define SYSCON_CLK_XTAL_OEN_S 10
/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK40X_BB_OEN (BIT(9))
/*description: .*/
#define SYSCON_CLK40X_BB_OEN (BIT(9))
#define SYSCON_CLK40X_BB_OEN_M (BIT(9))
#define SYSCON_CLK40X_BB_OEN_V 0x1
#define SYSCON_CLK40X_BB_OEN_S 9
/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_DAC_CPU_OEN (BIT(8))
/*description: .*/
#define SYSCON_CLK_DAC_CPU_OEN (BIT(8))
#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8))
#define SYSCON_CLK_DAC_CPU_OEN_V 0x1
#define SYSCON_CLK_DAC_CPU_OEN_S 8
/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_ADC_INF_OEN (BIT(7))
/*description: .*/
#define SYSCON_CLK_ADC_INF_OEN (BIT(7))
#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7))
#define SYSCON_CLK_ADC_INF_OEN_V 0x1
#define SYSCON_CLK_ADC_INF_OEN_S 7
/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_320M_OEN (BIT(6))
/*description: .*/
#define SYSCON_CLK_320M_OEN (BIT(6))
#define SYSCON_CLK_320M_OEN_M (BIT(6))
#define SYSCON_CLK_320M_OEN_V 0x1
#define SYSCON_CLK_320M_OEN_S 6
/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK160_OEN (BIT(5))
/*description: .*/
#define SYSCON_CLK160_OEN (BIT(5))
#define SYSCON_CLK160_OEN_M (BIT(5))
#define SYSCON_CLK160_OEN_V 0x1
#define SYSCON_CLK160_OEN_S 5
/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK80_OEN (BIT(4))
/*description: .*/
#define SYSCON_CLK80_OEN (BIT(4))
#define SYSCON_CLK80_OEN_M (BIT(4))
#define SYSCON_CLK80_OEN_V 0x1
#define SYSCON_CLK80_OEN_S 4
/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_BB_OEN (BIT(3))
/*description: .*/
#define SYSCON_CLK_BB_OEN (BIT(3))
#define SYSCON_CLK_BB_OEN_M (BIT(3))
#define SYSCON_CLK_BB_OEN_V 0x1
#define SYSCON_CLK_BB_OEN_S 3
/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK44_OEN (BIT(2))
/*description: .*/
#define SYSCON_CLK44_OEN (BIT(2))
#define SYSCON_CLK44_OEN_M (BIT(2))
#define SYSCON_CLK44_OEN_V 0x1
#define SYSCON_CLK44_OEN_S 2
/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK22_OEN (BIT(1))
/*description: .*/
#define SYSCON_CLK22_OEN (BIT(1))
#define SYSCON_CLK22_OEN_M (BIT(1))
#define SYSCON_CLK22_OEN_V 0x1
#define SYSCON_CLK22_OEN_S 1
/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK20_OEN (BIT(0))
/*description: .*/
#define SYSCON_CLK20_OEN (BIT(0))
#define SYSCON_CLK20_OEN_M (BIT(0))
#define SYSCON_CLK20_OEN_V 0x1
#define SYSCON_CLK20_OEN_S 0
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C)
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xC)
/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF
/*description: .*/
#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_S 0
#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x010)
#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10)
/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF
/*description: .*/
#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_2_S 0
#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x014)
#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x14)
/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF
/*description: .*/
#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_S 0
#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x018)
#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x18)
/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_WIFI_RST 0xFFFFFFFF
/*description: .*/
#define SYSCON_WIFI_RST 0xFFFFFFFF
#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
#define SYSCON_WIFI_RST_V 0xFFFFFFFF
#define SYSCON_WIFI_RST_S 0
@ -222,477 +222,494 @@ extern "C" {
#define SYSTEM_FE_RST (BIT(1))
#define SYSTEM_BB_RST (BIT(0))
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C)
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C)
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define SYSCON_PERI_IO_SWAP 0x000000FF
/*description: .*/
#define SYSCON_PERI_IO_SWAP 0x000000FF
#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
#define SYSCON_PERI_IO_SWAP_V 0xFF
#define SYSCON_PERI_IO_SWAP_S 0
#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x020)
#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20)
/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0))
/*description: .*/
#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0))
#define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0))
#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1
#define SYSCON_EXT_MEM_PMS_LOCK_S 0
#define SYSCON_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_SYSCON_BASE + 0x024)
#define SYSCON_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_SYSCON_BASE + 0x24)
/* SYSCON_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set 1 to bypass cache writeback request to external memory so
that spi will not check its attribute.*/
#define SYSCON_WRITEBACK_BYPASS (BIT(0))
/*description: Set 1 to bypass cache writeback request to external memory so that spi will not
check its attribute..*/
#define SYSCON_WRITEBACK_BYPASS (BIT(0))
#define SYSCON_WRITEBACK_BYPASS_M (BIT(0))
#define SYSCON_WRITEBACK_BYPASS_V 0x1
#define SYSCON_WRITEBACK_BYPASS_S 0
#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x028)
#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x28)
/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_FLASH_ACE0_ATTR 0x000001FF
/*description: .*/
#define SYSCON_FLASH_ACE0_ATTR 0x000001FF
#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
#define SYSCON_FLASH_ACE0_ATTR_V 0x1FF
#define SYSCON_FLASH_ACE0_ATTR_S 0
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C)
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2C)
/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_FLASH_ACE1_ATTR 0x000001FF
/*description: .*/
#define SYSCON_FLASH_ACE1_ATTR 0x000001FF
#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
#define SYSCON_FLASH_ACE1_ATTR_V 0x1FF
#define SYSCON_FLASH_ACE1_ATTR_S 0
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x030)
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30)
/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_FLASH_ACE2_ATTR 0x000001FF
/*description: .*/
#define SYSCON_FLASH_ACE2_ATTR 0x000001FF
#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
#define SYSCON_FLASH_ACE2_ATTR_V 0x1FF
#define SYSCON_FLASH_ACE2_ATTR_S 0
#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x034)
#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x34)
/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_FLASH_ACE3_ATTR 0x000001FF
/*description: .*/
#define SYSCON_FLASH_ACE3_ATTR 0x000001FF
#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
#define SYSCON_FLASH_ACE3_ATTR_V 0x1FF
#define SYSCON_FLASH_ACE3_ATTR_S 0
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x038)
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38)
/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF
/*description: .*/
#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE0_ADDR_S_S 0
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C)
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3C)
/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF
/*description: .*/
#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE1_ADDR_S_S 0
#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x040)
#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x40)
/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF
/*description: .*/
#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE2_ADDR_S_S 0
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x044)
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44)
/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF
/*description: .*/
#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE3_ADDR_S_S 0
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x048)
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48)
/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF
/*description: .*/
#define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
#define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE0_SIZE_S 0
#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x04C)
#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x4C)
/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF
/*description: .*/
#define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
#define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE1_SIZE_S 0
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x050)
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50)
/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF
/*description: .*/
#define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
#define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE2_SIZE_S 0
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x054)
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54)
/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF
/*description: .*/
#define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
#define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE3_SIZE_S 0
#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x058)
#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x58)
/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_SRAM_ACE0_ATTR 0x000001FF
/*description: .*/
#define SYSCON_SRAM_ACE0_ATTR 0x000001FF
#define SYSCON_SRAM_ACE0_ATTR_M ((SYSCON_SRAM_ACE0_ATTR_V)<<(SYSCON_SRAM_ACE0_ATTR_S))
#define SYSCON_SRAM_ACE0_ATTR_V 0x1FF
#define SYSCON_SRAM_ACE0_ATTR_S 0
#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x05C)
#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x5C)
/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_SRAM_ACE1_ATTR 0x000001FF
/*description: .*/
#define SYSCON_SRAM_ACE1_ATTR 0x000001FF
#define SYSCON_SRAM_ACE1_ATTR_M ((SYSCON_SRAM_ACE1_ATTR_V)<<(SYSCON_SRAM_ACE1_ATTR_S))
#define SYSCON_SRAM_ACE1_ATTR_V 0x1FF
#define SYSCON_SRAM_ACE1_ATTR_S 0
#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x060)
#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x60)
/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_SRAM_ACE2_ATTR 0x000001FF
/*description: .*/
#define SYSCON_SRAM_ACE2_ATTR 0x000001FF
#define SYSCON_SRAM_ACE2_ATTR_M ((SYSCON_SRAM_ACE2_ATTR_V)<<(SYSCON_SRAM_ACE2_ATTR_S))
#define SYSCON_SRAM_ACE2_ATTR_V 0x1FF
#define SYSCON_SRAM_ACE2_ATTR_S 0
#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x064)
#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x64)
/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_SRAM_ACE3_ATTR 0x000001FF
/*description: .*/
#define SYSCON_SRAM_ACE3_ATTR 0x000001FF
#define SYSCON_SRAM_ACE3_ATTR_M ((SYSCON_SRAM_ACE3_ATTR_V)<<(SYSCON_SRAM_ACE3_ATTR_S))
#define SYSCON_SRAM_ACE3_ATTR_V 0x1FF
#define SYSCON_SRAM_ACE3_ATTR_S 0
#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x068)
#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x68)
/* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF
/*description: .*/
#define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE0_ADDR_S_M ((SYSCON_SRAM_ACE0_ADDR_S_V)<<(SYSCON_SRAM_ACE0_ADDR_S_S))
#define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE0_ADDR_S_S 0
#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x06C)
#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x6C)
/* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF
/*description: .*/
#define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE1_ADDR_S_M ((SYSCON_SRAM_ACE1_ADDR_S_V)<<(SYSCON_SRAM_ACE1_ADDR_S_S))
#define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE1_ADDR_S_S 0
#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x070)
#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x70)
/* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF
/*description: .*/
#define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE2_ADDR_S_M ((SYSCON_SRAM_ACE2_ADDR_S_V)<<(SYSCON_SRAM_ACE2_ADDR_S_S))
#define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE2_ADDR_S_S 0
#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x074)
#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x74)
/* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF
/*description: .*/
#define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE3_ADDR_S_M ((SYSCON_SRAM_ACE3_ADDR_S_V)<<(SYSCON_SRAM_ACE3_ADDR_S_S))
#define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE3_ADDR_S_S 0
#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x078)
#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x78)
/* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF
/*description: .*/
#define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE0_SIZE_M ((SYSCON_SRAM_ACE0_SIZE_V)<<(SYSCON_SRAM_ACE0_SIZE_S))
#define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE0_SIZE_S 0
#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x07C)
#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x7C)
/* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF
/*description: .*/
#define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE1_SIZE_M ((SYSCON_SRAM_ACE1_SIZE_V)<<(SYSCON_SRAM_ACE1_SIZE_S))
#define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE1_SIZE_S 0
#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x080)
#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x80)
/* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF
/*description: .*/
#define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE2_SIZE_M ((SYSCON_SRAM_ACE2_SIZE_V)<<(SYSCON_SRAM_ACE2_SIZE_S))
#define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE2_SIZE_S 0
#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x084)
#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x84)
/* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF
/*description: .*/
#define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE3_SIZE_M ((SYSCON_SRAM_ACE3_SIZE_V)<<(SYSCON_SRAM_ACE3_SIZE_S))
#define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE3_SIZE_S 0
#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x088)
#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x88)
/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F
/*description: .*/
#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F
#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F
#define SYSCON_SPI_MEM_REJECT_CDE_S 2
/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1))
/*description: .*/
#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1))
#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1))
#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1
#define SYSCON_SPI_MEM_REJECT_CLR_S 1
/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI_MEM_REJECT_INT (BIT(0))
/*description: .*/
#define SYSCON_SPI_MEM_REJECT_INT (BIT(0))
#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0))
#define SYSCON_SPI_MEM_REJECT_INT_V 0x1
#define SYSCON_SPI_MEM_REJECT_INT_S 0
#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x08C)
#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x8C)
/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
/*description: .*/
#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
#define SYSCON_SPI_MEM_REJECT_ADDR_S 0
#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x090)
#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x90)
/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0))
/*description: .*/
#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1
#define SYSCON_SDIO_WIN_ACCESS_EN_S 0
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x094)
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94)
/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define SYSCON_REDCY_ANDOR (BIT(31))
/*description: .*/
#define SYSCON_REDCY_ANDOR (BIT(31))
#define SYSCON_REDCY_ANDOR_M (BIT(31))
#define SYSCON_REDCY_ANDOR_V 0x1
#define SYSCON_REDCY_ANDOR_S 31
/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: */
#define SYSCON_REDCY_SIG0 0x7FFFFFFF
/*description: .*/
#define SYSCON_REDCY_SIG0 0x7FFFFFFF
#define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG0_S 0
#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x098)
#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x98)
/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define SYSCON_REDCY_NANDOR (BIT(31))
/*description: .*/
#define SYSCON_REDCY_NANDOR (BIT(31))
#define SYSCON_REDCY_NANDOR_M (BIT(31))
#define SYSCON_REDCY_NANDOR_V 0x1
#define SYSCON_REDCY_NANDOR_S 31
/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: */
#define SYSCON_REDCY_SIG1 0x7FFFFFFF
/*description: .*/
#define SYSCON_REDCY_SIG1 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_S 0
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x09C)
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9C)
/* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define SYSCON_FREQ_MEM_FORCE_PD (BIT(7))
/*description: .*/
#define SYSCON_FREQ_MEM_FORCE_PD (BIT(7))
#define SYSCON_FREQ_MEM_FORCE_PD_M (BIT(7))
#define SYSCON_FREQ_MEM_FORCE_PD_V 0x1
#define SYSCON_FREQ_MEM_FORCE_PD_S 7
/* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define SYSCON_FREQ_MEM_FORCE_PU (BIT(6))
/*description: .*/
#define SYSCON_FREQ_MEM_FORCE_PU (BIT(6))
#define SYSCON_FREQ_MEM_FORCE_PU_M (BIT(6))
#define SYSCON_FREQ_MEM_FORCE_PU_V 0x1
#define SYSCON_FREQ_MEM_FORCE_PU_S 6
/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define SYSCON_DC_MEM_FORCE_PD (BIT(5))
/*description: .*/
#define SYSCON_DC_MEM_FORCE_PD (BIT(5))
#define SYSCON_DC_MEM_FORCE_PD_M (BIT(5))
#define SYSCON_DC_MEM_FORCE_PD_V 0x1
#define SYSCON_DC_MEM_FORCE_PD_S 5
/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define SYSCON_DC_MEM_FORCE_PU (BIT(4))
/*description: .*/
#define SYSCON_DC_MEM_FORCE_PU (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_V 0x1
#define SYSCON_DC_MEM_FORCE_PU_S 4
/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3))
/*description: .*/
#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3))
#define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3))
#define SYSCON_PBUS_MEM_FORCE_PD_V 0x1
#define SYSCON_PBUS_MEM_FORCE_PD_S 3
/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2))
/*description: .*/
#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2))
#define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2))
#define SYSCON_PBUS_MEM_FORCE_PU_V 0x1
#define SYSCON_PBUS_MEM_FORCE_PU_S 2
/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYSCON_AGC_MEM_FORCE_PD (BIT(1))
/*description: .*/
#define SYSCON_AGC_MEM_FORCE_PD (BIT(1))
#define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1))
#define SYSCON_AGC_MEM_FORCE_PD_V 0x1
#define SYSCON_AGC_MEM_FORCE_PD_S 1
/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define SYSCON_AGC_MEM_FORCE_PU (BIT(0))
/*description: .*/
#define SYSCON_AGC_MEM_FORCE_PU (BIT(0))
#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0))
#define SYSCON_AGC_MEM_FORCE_PU_V 0x1
#define SYSCON_AGC_MEM_FORCE_PU_S 0
#define SYSCON_SPI_MEM_ECC_CTRL_REG (DR_REG_SYSCON_BASE + 0x0A0)
#define SYSCON_SPI_MEM_ECC_CTRL_REG (DR_REG_SYSCON_BASE + 0xA0)
/* SYSCON_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */
/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes.
1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
#define SYSCON_SRAM_PAGE_SIZE 0x00000003
/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2:
1024 bytes. 3: 2048 bytes..*/
#define SYSCON_SRAM_PAGE_SIZE 0x00000003
#define SYSCON_SRAM_PAGE_SIZE_M ((SYSCON_SRAM_PAGE_SIZE_V)<<(SYSCON_SRAM_PAGE_SIZE_S))
#define SYSCON_SRAM_PAGE_SIZE_V 0x3
#define SYSCON_SRAM_PAGE_SIZE_S 20
/* SYSCON_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512
bytes. 2: 1024 bytes. 3: 2048 bytes.*/
#define SYSCON_FLASH_PAGE_SIZE 0x00000003
/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 by
tes. 3: 2048 bytes..*/
#define SYSCON_FLASH_PAGE_SIZE 0x00000003
#define SYSCON_FLASH_PAGE_SIZE_M ((SYSCON_FLASH_PAGE_SIZE_V)<<(SYSCON_FLASH_PAGE_SIZE_S))
#define SYSCON_FLASH_PAGE_SIZE_V 0x3
#define SYSCON_FLASH_PAGE_SIZE_S 18
#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0x0A8)
#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0xA8)
/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
/*description: */
#define SYSCON_SRAM_CLKGATE_FORCE_ON 0x000007FF
/*description: .*/
#define SYSCON_SRAM_CLKGATE_FORCE_ON 0x000007FF
#define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
#define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0x7FF
#define SYSCON_SRAM_CLKGATE_FORCE_ON_S 3
/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
/*description: */
#define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000007
/*description: .*/
#define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000007
#define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
#define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x7
#define SYSCON_ROM_CLKGATE_FORCE_ON_S 0
#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0x0AC)
#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xAC)
/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */
/*description: */
#define SYSCON_SRAM_POWER_DOWN 0x000007FF
/*description: .*/
#define SYSCON_SRAM_POWER_DOWN 0x000007FF
#define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
#define SYSCON_SRAM_POWER_DOWN_V 0x7FF
#define SYSCON_SRAM_POWER_DOWN_S 3
/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: */
#define SYSCON_ROM_POWER_DOWN 0x00000007
/*description: .*/
#define SYSCON_ROM_POWER_DOWN 0x00000007
#define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
#define SYSCON_ROM_POWER_DOWN_V 0x7
#define SYSCON_ROM_POWER_DOWN_S 0
#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0x0B0)
#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xB0)
/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
/*description: */
#define SYSCON_SRAM_POWER_UP 0x000007FF
/*description: .*/
#define SYSCON_SRAM_POWER_UP 0x000007FF
#define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
#define SYSCON_SRAM_POWER_UP_V 0x7FF
#define SYSCON_SRAM_POWER_UP_S 3
/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
/*description: */
#define SYSCON_ROM_POWER_UP 0x00000007
/*description: .*/
#define SYSCON_ROM_POWER_UP 0x00000007
#define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
#define SYSCON_ROM_POWER_UP_V 0x7
#define SYSCON_ROM_POWER_UP_S 0
#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0x0B4)
#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xB4)
/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: */
#define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27))
/*description: .*/
#define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27))
#define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27))
#define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1
#define SYSCON_NOBYPASS_CPU_ISO_RST_S 27
/* SYSCON_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
/*description: */
#define SYSCON_RETENTION_CPU_LINK_ADDR 0x07FFFFFF
/*description: .*/
#define SYSCON_RETENTION_CPU_LINK_ADDR 0x07FFFFFF
#define SYSCON_RETENTION_CPU_LINK_ADDR_M ((SYSCON_RETENTION_CPU_LINK_ADDR_V)<<(SYSCON_RETENTION_CPU_LINK_ADDR_S))
#define SYSCON_RETENTION_CPU_LINK_ADDR_V 0x7FFFFFF
#define SYSCON_RETENTION_CPU_LINK_ADDR_S 0
#define SYSCON_RETENTION_CTRL1_REG (DR_REG_SYSCON_BASE + 0x0B8)
#define SYSCON_RETENTION_CTRL1_REG (DR_REG_SYSCON_BASE + 0xB8)
/* SYSCON_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
/*description: */
#define SYSCON_RETENTION_TAG_LINK_ADDR 0x07FFFFFF
/*description: .*/
#define SYSCON_RETENTION_TAG_LINK_ADDR 0x07FFFFFF
#define SYSCON_RETENTION_TAG_LINK_ADDR_M ((SYSCON_RETENTION_TAG_LINK_ADDR_V)<<(SYSCON_RETENTION_TAG_LINK_ADDR_S))
#define SYSCON_RETENTION_TAG_LINK_ADDR_V 0x7FFFFFF
#define SYSCON_RETENTION_TAG_LINK_ADDR_S 0
#define SYSCON_RETENTION_CTRL2_REG (DR_REG_SYSCON_BASE + 0x0BC)
#define SYSCON_RETENTION_CTRL2_REG (DR_REG_SYSCON_BASE + 0xBC)
/* SYSCON_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define SYSCON_RET_ICACHE_ENABLE (BIT(31))
/*description: .*/
#define SYSCON_RET_ICACHE_ENABLE (BIT(31))
#define SYSCON_RET_ICACHE_ENABLE_M (BIT(31))
#define SYSCON_RET_ICACHE_ENABLE_V 0x1
#define SYSCON_RET_ICACHE_ENABLE_S 31
/* SYSCON_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */
/*description: */
#define SYSCON_RET_ICACHE_START_POINT 0x000000FF
/*description: .*/
#define SYSCON_RET_ICACHE_START_POINT 0x000000FF
#define SYSCON_RET_ICACHE_START_POINT_M ((SYSCON_RET_ICACHE_START_POINT_V)<<(SYSCON_RET_ICACHE_START_POINT_S))
#define SYSCON_RET_ICACHE_START_POINT_V 0xFF
#define SYSCON_RET_ICACHE_START_POINT_S 22
/* SYSCON_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */
/*description: */
#define SYSCON_RET_ICACHE_VLD_SIZE 0x000000FF
/*description: .*/
#define SYSCON_RET_ICACHE_VLD_SIZE 0x000000FF
#define SYSCON_RET_ICACHE_VLD_SIZE_M ((SYSCON_RET_ICACHE_VLD_SIZE_V)<<(SYSCON_RET_ICACHE_VLD_SIZE_S))
#define SYSCON_RET_ICACHE_VLD_SIZE_V 0xFF
#define SYSCON_RET_ICACHE_VLD_SIZE_S 13
/* SYSCON_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */
/*description: */
#define SYSCON_RET_ICACHE_SIZE 0x000000FF
/*description: .*/
#define SYSCON_RET_ICACHE_SIZE 0x000000FF
#define SYSCON_RET_ICACHE_SIZE_M ((SYSCON_RET_ICACHE_SIZE_V)<<(SYSCON_RET_ICACHE_SIZE_S))
#define SYSCON_RET_ICACHE_SIZE_V 0xFF
#define SYSCON_RET_ICACHE_SIZE_S 4
#define SYSCON_RETENTION_CTRL3_REG (DR_REG_SYSCON_BASE + 0x0C0)
#define SYSCON_RETENTION_CTRL3_REG (DR_REG_SYSCON_BASE + 0xC0)
/* SYSCON_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define SYSCON_RET_DCACHE_ENABLE (BIT(31))
/*description: .*/
#define SYSCON_RET_DCACHE_ENABLE (BIT(31))
#define SYSCON_RET_DCACHE_ENABLE_M (BIT(31))
#define SYSCON_RET_DCACHE_ENABLE_V 0x1
#define SYSCON_RET_DCACHE_ENABLE_S 31
/* SYSCON_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */
/*description: */
#define SYSCON_RET_DCACHE_START_POINT 0x000001FF
/*description: .*/
#define SYSCON_RET_DCACHE_START_POINT 0x000001FF
#define SYSCON_RET_DCACHE_START_POINT_M ((SYSCON_RET_DCACHE_START_POINT_V)<<(SYSCON_RET_DCACHE_START_POINT_S))
#define SYSCON_RET_DCACHE_START_POINT_V 0x1FF
#define SYSCON_RET_DCACHE_START_POINT_S 22
/* SYSCON_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */
/*description: */
#define SYSCON_RET_DCACHE_VLD_SIZE 0x000001FF
/*description: .*/
#define SYSCON_RET_DCACHE_VLD_SIZE 0x000001FF
#define SYSCON_RET_DCACHE_VLD_SIZE_M ((SYSCON_RET_DCACHE_VLD_SIZE_V)<<(SYSCON_RET_DCACHE_VLD_SIZE_S))
#define SYSCON_RET_DCACHE_VLD_SIZE_V 0x1FF
#define SYSCON_RET_DCACHE_VLD_SIZE_S 13
/* SYSCON_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */
/*description: */
#define SYSCON_RET_DCACHE_SIZE 0x000001FF
/*description: .*/
#define SYSCON_RET_DCACHE_SIZE 0x000001FF
#define SYSCON_RET_DCACHE_SIZE_M ((SYSCON_RET_DCACHE_SIZE_V)<<(SYSCON_RET_DCACHE_SIZE_S))
#define SYSCON_RET_DCACHE_SIZE_V 0x1FF
#define SYSCON_RET_DCACHE_SIZE_S 4
#define SYSCON_RETENTION_CTRL4_REG (DR_REG_SYSCON_BASE + 0xC4)
/* SYSCON_RETENTION_INV_CFG : R/W ;bitpos:[31:0] ;default: ~32'h0 ; */
/*description: .*/
#define SYSCON_RETENTION_INV_CFG 0xFFFFFFFF
#define SYSCON_RETENTION_INV_CFG_M ((SYSCON_RETENTION_INV_CFG_V)<<(SYSCON_RETENTION_INV_CFG_S))
#define SYSCON_RETENTION_INV_CFG_V 0xFFFFFFFF
#define SYSCON_RETENTION_INV_CFG_S 0
#define SYSCON_RETENTION_CTRL5_REG (DR_REG_SYSCON_BASE + 0xC8)
/* SYSCON_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define SYSCON_RETENTION_DISABLE (BIT(0))
#define SYSCON_RETENTION_DISABLE_M (BIT(0))
#define SYSCON_RETENTION_DISABLE_V 0x1
#define SYSCON_RETENTION_DISABLE_S 0
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h21010400 ; */
/*description: Version control*/
#define SYSCON_DATE 0xFFFFFFFF
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */
/*description: Version control.*/
#define SYSCON_DATE 0xFFFFFFFF
#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
#define SYSCON_DATE_V 0xFFFFFFFF
#define SYSCON_DATE_S 0
#ifdef __cplusplus
}
#endif

270
components/soc/esp32s3/include/soc/syscon_struct.h
View File

@ -13,6 +13,8 @@
// limitations under the License.
#ifndef _SOC_SYSCON_STRUCT_H_
#define _SOC_SYSCON_STRUCT_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
@ -21,304 +23,310 @@ extern "C" {
typedef volatile struct syscon_dev_s {
union {
struct {
uint32_t apb_ctrl_pre_div_cnt: 10;
uint32_t apb_ctrl_clk_320m_en: 1;
uint32_t clk_en: 1;
uint32_t apb_ctrl_rst_tick_cnt: 1;
uint32_t reserved13: 19;
uint32_t pre_div : 10;
uint32_t clk_320m_en : 1;
uint32_t clk_en : 1;
uint32_t rst_tick : 1;
uint32_t reserved13 : 19;
};
uint32_t val;
} apb_ctrl_sysclk_conf;
} clk_conf;
union {
struct {
uint32_t apb_ctrl_xtal_tick_num: 8;
uint32_t apb_ctrl_ck8m_tick_num: 8;
uint32_t apb_ctrl_tick_enable: 1;
uint32_t reserved17: 15;
uint32_t xtal_tick : 8;
uint32_t ck8m_tick : 8;
uint32_t tick_enable : 1;
uint32_t reserved17 : 15;
};
uint32_t val;
} apb_ctrl_tick_conf;
} tick_conf;
union {
struct {
uint32_t clk20_oen: 1;
uint32_t clk22_oen: 1;
uint32_t clk44_oen: 1;
uint32_t clk_bb_oen: 1;
uint32_t clk80_oen: 1;
uint32_t clk160_oen: 1;
uint32_t clk_320m_oen: 1;
uint32_t clk_adc_inf_oen: 1;
uint32_t clk_dac_cpu_oen: 1;
uint32_t clk40x_bb_oen: 1;
uint32_t clk_xtal_oen: 1;
uint32_t reserved11: 21;
uint32_t clk20_oen : 1;
uint32_t clk22_oen : 1;
uint32_t clk44_oen : 1;
uint32_t clk_bb_oen : 1;
uint32_t clk80_oen : 1;
uint32_t clk160_oen : 1;
uint32_t clk_320m_oen : 1;
uint32_t clk_adc_inf_oen : 1;
uint32_t clk_dac_cpu_oen : 1;
uint32_t clk40x_bb_oen : 1;
uint32_t clk_xtal_oen : 1;
uint32_t reserved11 : 21;
};
uint32_t val;
} apb_ctrl_clk_out_en;
uint32_t wifi_bb_cfg; /**/
uint32_t wifi_bb_cfg_2; /**/
uint32_t wifi_clk_en; /**/
uint32_t wifi_rst_en; /**/
} clk_out_en;
uint32_t wifi_bb_cfg;
uint32_t wifi_bb_cfg_2;
uint32_t wifi_clk_en;
uint32_t wifi_rst_en;
union {
struct {
uint32_t peri_io_swap: 8;
uint32_t reserved8: 24;
uint32_t peri_io_swap : 8;
uint32_t reserved8 : 24;
};
uint32_t val;
} host_inf_sel;
union {
struct {
uint32_t ext_mem_pms_lock: 1;
uint32_t reserved1: 31;
uint32_t ext_mem_pms_lock : 1;
uint32_t reserved1 : 31;
};
uint32_t val;
} ext_mem_pms_lock;
union {
struct {
uint32_t writeback_bypass: 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/
uint32_t reserved1: 31;
uint32_t writeback_bypass : 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/
uint32_t reserved1 : 31;
};
uint32_t val;
} ext_mem_writeback_bypass;
union {
struct {
uint32_t flash_ace0_attr: 9;
uint32_t reserved9: 23;
uint32_t flash_ace0_attr : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} flash_ace0_attr;
union {
struct {
uint32_t flash_ace1_attr: 9;
uint32_t reserved9: 23;
uint32_t flash_ace1_attr : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} flash_ace1_attr;
union {
struct {
uint32_t flash_ace2_attr: 9;
uint32_t reserved9: 23;
uint32_t flash_ace2_attr : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} flash_ace2_attr;
union {
struct {
uint32_t flash_ace3_attr: 9;
uint32_t reserved9: 23;
uint32_t flash_ace3_attr : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} flash_ace3_attr;
uint32_t flash_ace0_addr; /**/
uint32_t flash_ace1_addr; /**/
uint32_t flash_ace2_addr; /**/
uint32_t flash_ace3_addr; /**/
uint32_t flash_ace0_addr;
uint32_t flash_ace1_addr;
uint32_t flash_ace2_addr;
uint32_t flash_ace3_addr;
union {
struct {
uint32_t flash_ace0_size:16;
uint32_t reserved16: 16;
uint32_t flash_ace0_size : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} flash_ace0_size;
union {
struct {
uint32_t flash_ace1_size:16;
uint32_t reserved16: 16;
uint32_t flash_ace1_size : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} flash_ace1_size;
union {
struct {
uint32_t flash_ace2_size:16;
uint32_t reserved16: 16;
uint32_t flash_ace2_size : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} flash_ace2_size;
union {
struct {
uint32_t flash_ace3_size:16;
uint32_t reserved16: 16;
uint32_t flash_ace3_size : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} flash_ace3_size;
union {
struct {
uint32_t sram_ace0_attr: 9;
uint32_t reserved9: 23;
uint32_t sram_ace0_attr : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} sram_ace0_attr;
union {
struct {
uint32_t sram_ace1_attr: 9;
uint32_t reserved9: 23;
uint32_t sram_ace1_attr : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} sram_ace1_attr;
union {
struct {
uint32_t sram_ace2_attr: 9;
uint32_t reserved9: 23;
uint32_t sram_ace2_attr : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} sram_ace2_attr;
union {
struct {
uint32_t sram_ace3_attr: 9;
uint32_t reserved9: 23;
uint32_t sram_ace3_attr : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} sram_ace3_attr;
uint32_t sram_ace0_addr; /**/
uint32_t sram_ace1_addr; /**/
uint32_t sram_ace2_addr; /**/
uint32_t sram_ace3_addr; /**/
uint32_t sram_ace0_addr;
uint32_t sram_ace1_addr;
uint32_t sram_ace2_addr;
uint32_t sram_ace3_addr;
union {
struct {
uint32_t sram_ace0_size:16;
uint32_t reserved16: 16;
uint32_t sram_ace0_size : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} sram_ace0_size;
union {
struct {
uint32_t sram_ace1_size:16;
uint32_t reserved16: 16;
uint32_t sram_ace1_size : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} sram_ace1_size;
union {
struct {
uint32_t sram_ace2_size:16;
uint32_t reserved16: 16;
uint32_t sram_ace2_size : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} sram_ace2_size;
union {
struct {
uint32_t sram_ace3_size:16;
uint32_t reserved16: 16;
uint32_t sram_ace3_size : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} sram_ace3_size;
union {
struct {
uint32_t spi_mem_reject_int: 1;
uint32_t spi_mem_reject_clr: 1;
uint32_t spi_mem_reject_cde: 5;
uint32_t reserved7: 25;
uint32_t spi_mem_reject_int : 1;
uint32_t spi_mem_reject_clr : 1;
uint32_t spi_mem_reject_cde : 5;
uint32_t reserved7 : 25;
};
uint32_t val;
} spi_mem_pms_ctrl;
uint32_t spi_mem_reject_addr; /**/
uint32_t spi_mem_reject_addr;
union {
struct {
uint32_t sdio_win_access_en: 1;
uint32_t reserved1: 31;
uint32_t sdio_win_access_en : 1;
uint32_t reserved1 : 31;
};
uint32_t val;
} apb_ctrl_sdio_ctrl;
} sdio_ctrl;
union {
struct {
uint32_t redcy_sig0: 31;
uint32_t redcy_andor: 1;
uint32_t redcy_sig0 : 31;
uint32_t redcy_andor : 1;
};
uint32_t val;
} redcy_sig0;
union {
struct {
uint32_t redcy_sig1: 31;
uint32_t redcy_nandor: 1;
uint32_t redcy_sig1 : 31;
uint32_t redcy_nandor : 1;
};
uint32_t val;
} redcy_sig1;
union {
struct {
uint32_t agc_mem_force_pu: 1;
uint32_t agc_mem_force_pd: 1;
uint32_t pbus_mem_force_pu: 1;
uint32_t pbus_mem_force_pd: 1;
uint32_t dc_mem_force_pu: 1;
uint32_t dc_mem_force_pd: 1;
uint32_t freq_mem_force_pu: 1;
uint32_t freq_mem_force_pd: 1;
uint32_t reserved8: 24;
uint32_t agc_mem_force_pu : 1;
uint32_t agc_mem_force_pd : 1;
uint32_t pbus_mem_force_pu : 1;
uint32_t pbus_mem_force_pd : 1;
uint32_t dc_mem_force_pu : 1;
uint32_t dc_mem_force_pd : 1;
uint32_t freq_mem_force_pu : 1;
uint32_t freq_mem_force_pd : 1;
uint32_t reserved8 : 24;
};
uint32_t val;
} front_end_mem_pd;
union {
struct {
uint32_t reserved0: 18; /*reserved*/
uint32_t flash_page_size: 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t sram_page_size: 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t reserved22: 10; /*reserved*/
uint32_t reserved0 : 18; /*reserved*/
uint32_t flash_page_size : 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t sram_page_size : 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t reserved22 : 10; /*reserved*/
};
uint32_t val;
} spi_mem_ecc_ctrl;
uint32_t reserved_a4;
union {
struct {
uint32_t rom_clkgate_force_on: 3;
uint32_t sram_clkgate_force_on:11;
uint32_t reserved14: 18;
uint32_t rom_clkgate_force_on : 3;
uint32_t sram_clkgate_force_on : 11;
uint32_t reserved14 : 18;
};
uint32_t val;
} clkgate_force_on;
union {
struct {
uint32_t rom_power_down: 3;
uint32_t sram_power_down:11;
uint32_t reserved14: 18;
uint32_t rom_power_down : 3;
uint32_t sram_power_down : 11;
uint32_t reserved14 : 18;
};
uint32_t val;
} mem_power_down;
union {
struct {
uint32_t rom_power_up: 3;
uint32_t sram_power_up:11;
uint32_t reserved14: 18;
uint32_t rom_power_up : 3;
uint32_t sram_power_up : 11;
uint32_t reserved14 : 18;
};
uint32_t val;
} mem_power_up;
union {
struct {
uint32_t retention_cpu_link_addr:27;
uint32_t nobypass_cpu_iso_rst: 1;
uint32_t reserved28: 4;
uint32_t retention_cpu_link_addr : 27;
uint32_t nobypass_cpu_iso_rst : 1;
uint32_t reserved28 : 4;
};
uint32_t val;
} retention_ctrl;
union {
struct {
uint32_t retention_tag_link_addr:27;
uint32_t reserved27: 5;
uint32_t retention_tag_link_addr : 27;
uint32_t reserved27 : 5;
};
uint32_t val;
} retention_ctrl1;
union {
struct {
uint32_t reserved0: 4;
uint32_t ret_icache_size: 8;
uint32_t reserved12: 1;
uint32_t ret_icache_vld_size: 8;
uint32_t reserved21: 1;
uint32_t ret_icache_start_point: 8;
uint32_t reserved30: 1;
uint32_t ret_icache_enable: 1;
uint32_t reserved0 : 4;
uint32_t ret_icache_size : 8;
uint32_t reserved12 : 1;
uint32_t ret_icache_vld_size : 8;
uint32_t reserved21 : 1;
uint32_t ret_icache_start_point : 8;
uint32_t reserved30 : 1;
uint32_t ret_icache_enable : 1;
};
uint32_t val;
} retention_ctrl2;
union {
struct {
uint32_t reserved0: 4;
uint32_t ret_dcache_size: 9;
uint32_t ret_dcache_vld_size: 9;
uint32_t ret_dcache_start_point: 9;
uint32_t ret_dcache_enable: 1;
uint32_t reserved0 : 4;
uint32_t ret_dcache_size : 9;
uint32_t ret_dcache_vld_size : 9;
uint32_t ret_dcache_start_point : 9;
uint32_t ret_dcache_enable : 1;
};
uint32_t val;
} retention_ctrl3;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t retention_ctrl4;
union {
struct {
uint32_t retention_disable : 1;
uint32_t reserved1 : 31;
};
uint32_t val;
} retention_ctrl5;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
@ -523,11 +531,13 @@ typedef volatile struct syscon_dev_s {
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t apb_ctrl_date; /*Version control*/
uint32_t date;
} syscon_dev_t;
extern syscon_dev_t SYSCON;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_SYSCON_STRUCT_H_ */
#endif /*_SOC_SYSCON_STRUCT_H_ */