From 113c8de0fcd41942e670179cbf827f2118fc27dc Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Thu, 13 Jun 2024 16:19:32 +0800 Subject: [PATCH] fix(rom): fixed esprv_int_set_threshold on C5/C61 --- components/esp_rom/CMakeLists.txt | 2 +- .../esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h | 1 + .../esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld | 1 - components/esp_rom/esp32c61/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32c61/esp_rom_caps.h | 1 + components/esp_rom/esp32c61/ld/esp32c61.rom.ld | 1 - components/esp_rom/patches/esp_rom_clic.c | 11 ++++++++++- 8 files changed, 21 insertions(+), 4 deletions(-) diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 76f70665f6..944999f154 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -70,7 +70,7 @@ if(CONFIG_HAL_WDT_USE_ROM_IMPL) list(APPEND sources "patches/esp_rom_wdt.c") endif() -if(CONFIG_ESP_ROM_CLIC_INT_TYPE_PATCH) +if(CONFIG_ESP_ROM_CLIC_INT_TYPE_PATCH OR CONFIG_ESP_ROM_CLIC_INT_THRESH_PATCH) list(APPEND sources "patches/esp_rom_clic.c") endif() diff --git a/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in index 688612fcdb..e3c3d9b6f1 100644 --- a/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in @@ -86,3 +86,7 @@ config ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB config ESP_ROM_HAS_OUTPUT_PUTC_FUNC bool default y + +config ESP_ROM_CLIC_INT_THRESH_PATCH + bool + default y diff --git a/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h index 9006d78b2f..5b1c3db40f 100644 --- a/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h +++ b/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h @@ -27,3 +27,4 @@ #define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) +#define ESP_ROM_CLIC_INT_THRESH_PATCH (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF diff --git a/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld b/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld index 3f5b833a29..8724419cc6 100644 --- a/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld +++ b/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld @@ -276,7 +276,6 @@ gpio_pad_hold = 0x40000740; /* Functions */ esprv_intc_int_set_priority = 0x40000744; -esprv_intc_int_set_threshold = 0x40000748; esprv_intc_int_enable = 0x4000074c; esprv_intc_int_disable = 0x40000750; esprv_intc_int_set_type = 0x40000754; diff --git a/components/esp_rom/esp32c61/Kconfig.soc_caps.in b/components/esp_rom/esp32c61/Kconfig.soc_caps.in index 67076708db..aa0401e081 100644 --- a/components/esp_rom/esp32c61/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c61/Kconfig.soc_caps.in @@ -90,3 +90,7 @@ config ESP_ROM_USB_OTG_NUM config ESP_ROM_HAS_OUTPUT_PUTC_FUNC bool default y + +config ESP_ROM_CLIC_INT_THRESH_PATCH + bool + default y diff --git a/components/esp_rom/esp32c61/esp_rom_caps.h b/components/esp_rom/esp32c61/esp_rom_caps.h index aea1da0391..27f71c271c 100644 --- a/components/esp_rom/esp32c61/esp_rom_caps.h +++ b/components/esp_rom/esp32c61/esp_rom_caps.h @@ -30,3 +30,4 @@ #define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions #define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage. #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) +#define ESP_ROM_CLIC_INT_THRESH_PATCH (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld index fae956570c..a90b5b65b7 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld @@ -278,7 +278,6 @@ gpio_pad_hold = 0x40000724; /* Functions */ esprv_intc_int_set_priority = 0x40000728; -esprv_intc_int_set_threshold = 0x4000072c; esprv_intc_int_enable = 0x40000730; esprv_intc_int_disable = 0x40000734; esprv_intc_int_set_type = 0x40000738; diff --git a/components/esp_rom/patches/esp_rom_clic.c b/components/esp_rom/patches/esp_rom_clic.c index d4643e3ef5..7160931c66 100644 --- a/components/esp_rom/patches/esp_rom_clic.c +++ b/components/esp_rom/patches/esp_rom_clic.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include "esp_rom_caps.h" #include "soc/clic_reg.h" #include "riscv/interrupt.h" +#include "riscv/rv_utils.h" #if ESP_ROM_CLIC_INT_TYPE_PATCH @@ -20,3 +21,11 @@ void esprv_int_set_type(int rv_int_num, enum intr_type type) REG_SET_FIELD(CLIC_INT_CTRL_REG(rv_int_num + CLIC_EXT_INTR_NUM_OFFSET), CLIC_INT_ATTR_TRIG, type); } #endif + +#if ESP_ROM_CLIC_INT_THRESH_PATCH +void esprv_int_set_threshold(int priority_threshold) +{ + /* ROM functions assume minimum MINTTHRESH is 0x1F, but it is actually 0xF */ + rv_utils_set_intlevel(priority_threshold); +} +#endif //ESP_ROM_CLIC_INT_THRESH_PATCH