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Merge branch 'feat/support_esp32h21_modem_clock' into 'master'

Browse Source 
feat(esp_hw_support): support esp32h21 modem clock

Closes PM-348

See merge request espressif/esp-idf!37082
This commit is contained in:
Wu Zheng Hui 2025-02-26 12:02:43 +08:00
commit 132444cd08
12 changed files with 1768 additions and 1 deletions
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74
components/hal/esp32h21/include/hal/lp_clkrst_ll.h Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-H21 LP CLKRST & LP PERI register operations
#pragma once
#include <stdbool.h>
#include <stdlib.h>
#include "soc/soc.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/lpperi_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inline void lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(lp_clkrst_dev_t *hw, bool en)
{
hw->lpperi.clkrst_lp_sel_osc_slow = en;
}
__attribute__((always_inline))
static inline void lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(lp_clkrst_dev_t *hw, bool en)
{
hw->lpperi.clkrst_lp_sel_osc_fast = en;
}
__attribute__((always_inline))
static inline void lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(lp_clkrst_dev_t *hw, bool en)
{
hw->lpperi.clkrst_lp_sel_xtal = en;
}
__attribute__((always_inline))
static inline void lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(lp_clkrst_dev_t *hw, bool en)
{
hw->lpperi.clkrst_lp_sel_xtal32k = en;
}
__attribute__((always_inline))
static inline void lp_clkrst_ll_set_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw, uint32_t value)
{
hw->lpperi.clkrst_lp_bletimer_div_num = value;
}
__attribute__((always_inline))
static inline uint32_t lp_clkrst_ll_get_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw)
{
return hw->lpperi.clkrst_lp_bletimer_div_num;
}
__attribute__((always_inline))
static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, uint32_t src)
{
hw->lpperi.clkrst_lp_bletimer_32k_sel = src;
}
__attribute__((always_inline))
static inline void _lp_clkrst_ll_enable_rng_clock(bool en)
{
LPPERI.clk_en.rng_ck_en = en;
}
/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
#define lp_clkrst_ll_enable_rng_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_clkrst_ll_enable_rng_clock(__VA_ARGS__)
#ifdef __cplusplus
}
#endif

110
components/hal/esp32h21/include/hal/modem_lpcon_ll.h Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-H21 MODEM LPCON register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "hal/assert.h"
#include "modem/modem_lpcon_struct.h"
#include "hal/modem_clock_types.h"
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en)
{
hw->test_conf.clk_en = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_coex_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en)
{
hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_slow = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_coex_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en)
{
hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_fast = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_coex_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en)
{
hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_coex_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en)
{
hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal32k = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_set_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value)
{
hw->coex_lp_clk_conf.clk_coex_lp_div_num = value;
}
__attribute__((always_inline))
static inline uint32_t modem_lpcon_ll_get_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw)
{
return hw->coex_lp_clk_conf.clk_coex_lp_div_num;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf.clk_coex_en = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_fe_mem_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf.clk_fe_mem_en = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf_force_on.clk_coex_fo = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_fe_mem_force_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf_force_on.clk_fe_mem_fo = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw)
{
hw->rst_conf.rst_coex = 1;
hw->rst_conf.rst_coex = 0;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw)
{
hw->rst_conf.val = 0xf;
hw->rst_conf.val = 0;
}
__attribute__((always_inline))
static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw)
{
return hw->date.val;
}
#ifdef __cplusplus
}
#endif

275
components/hal/esp32h21/include/hal/modem_syscon_ll.h Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-H21 MODEM SYSCON register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "hal/assert.h"
#include "modem/modem_syscon_struct.h"
#include "hal/modem_clock_types.h"
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en)
{
hw->test_conf.clk_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en)
{
// ESP32-H21 Not Support
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_etm_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_zb_apb_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_zb_mac_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_modem_sec_en = en;
hw->clk_conf.clk_modem_sec_ecb_en = en;
hw->clk_conf.clk_modem_sec_ccm_en = en;
hw->clk_conf.clk_modem_sec_bah_en = en;
hw->clk_conf.clk_modem_sec_apb_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_ble_timer_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_ble_timer_apb_en = en;
hw->clk_conf.clk_ble_timer_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_data_dump_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_data_dump_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw)
{
hw->clk_conf_force_on.clk_etm_fo = 1;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_modem_sec_force_clock(modem_syscon_dev_t *hw)
{
hw->clk_conf_force_on.clk_modem_sec_fo = 1;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_ble_timer_force_clock(modem_syscon_dev_t *hw)
{
hw->clk_conf_force_on.clk_ble_timer_fo = 1;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_data_dump_force_clock(modem_syscon_dev_t *hw)
{
hw->clk_conf_force_on.clk_data_dump_fo = 1;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_fe(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_fe = 1;
hw->modem_rst_conf.rst_fe = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_btmac_apb(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_btmac_apb = 1;
hw->modem_rst_conf.rst_btmac_apb = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_btmac(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_btmac = 1;
hw->modem_rst_conf.rst_btmac = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_btbb_apb(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_btbb_apb = 1;
hw->modem_rst_conf.rst_btbb_apb = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_btbb(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_btbb = 1;
hw->modem_rst_conf.rst_btbb = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_etm(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_etm = 1;
hw->modem_rst_conf.rst_etm = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_zbmac = 1;
hw->modem_rst_conf.rst_zbmac = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_zbmac_apb(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_zbmac_apb = 1;
hw->modem_rst_conf.rst_zbmac_apb = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_modem_ecb = 1;
hw->modem_rst_conf.rst_modem_ccm = 1;
hw->modem_rst_conf.rst_modem_bah = 1;
hw->modem_rst_conf.rst_modem_sec = 1;
hw->modem_rst_conf.rst_modem_ecb = 0;
hw->modem_rst_conf.rst_modem_ccm = 0;
hw->modem_rst_conf.rst_modem_bah = 0;
hw->modem_rst_conf.rst_modem_sec = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_ble_timer(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_ble_timer = 1;
hw->modem_rst_conf.rst_ble_timer = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_data_dump(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_data_dump = 1;
hw->modem_rst_conf.rst_data_dump = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.val = 0xffffffff;
hw->modem_rst_conf.val = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask)
{
if(en){
hw->clk_conf1.val = hw->clk_conf1.val | mask;
} else {
hw->clk_conf1.val = hw->clk_conf1.val & ~mask;
}
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_txlogain_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_txlogain_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_16m_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_16m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_32m_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_32m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_sdm_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_sdm_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_adc_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_adc_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_apb_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_apb_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_bt_apb_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_bt_apb_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_bt_mac_clock(modem_syscon_dev_t *hw, bool en)
{
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_bt_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_bt_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_force_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1_force_on.clk_fe_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_bt_force_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1_force_on.clk_bt_fo = en;
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_get_date(modem_syscon_dev_t *hw)
{
return hw->date.val;
}
#ifdef __cplusplus
}
#endif

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components/hal/esp32h21/modem_clock_hal.c Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The HAL layer for MODEM CLOCK (ESP32-H21 specific part)
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/soc.h"
#include "hal/modem_clock_hal.h"
#include "hal/lp_clkrst_ll.h"
#include "hal/modem_clock_types.h"
#include "hal/assert.h"
typedef enum {
MODEM_CLOCK_XTAL32K_CODE = 0,
MODEM_CLOCK_RC32K_CODE = 1,
MODEM_CLOCK_EXT32K_CODE = 2
} modem_clock_32k_clk_src_code_t;
void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
{
modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
modem_syscon_ll_enable_fe_32m_clock(hal->syscon_dev, enable);
}
void IRAM_ATTR modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_context_t *hal, bool enable)
{
modem_lpcon_ll_enable_fe_mem_clock(hal->lpcon_dev, enable);
modem_syscon_ll_enable_fe_sdm_clock(hal->syscon_dev, enable);
modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable);
modem_syscon_ll_enable_fe_txlogain_clock(hal->syscon_dev, enable);
modem_syscon_ll_enable_fe_16m_clock(hal->syscon_dev, enable);
}
void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider)
{
lp_clkrst_ll_set_ble_rtc_timer_divisor_value(&LP_CLKRST, divider);
}
void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable)
{
// BLE RTC Timer has bees moved to LP_AON domain, No clock gate on ESP32-H21
}
void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal)
{
lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, false);
lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, false);
lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, false);
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, false);
}
void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src)
{
HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX);
switch (src)
{
case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, true);
break;
case MODEM_CLOCK_LPCLK_SRC_RC_FAST:
lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, true);
break;
case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, true);
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
break;
default:
HAL_ASSERT(0);
}
}
void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal)
{
modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, false);
modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, false);
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, false);
modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, false);
}
void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src)
{
HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX);
switch (src)
{
case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true);
break;
case MODEM_CLOCK_LPCLK_SRC_RC_FAST:
modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, true);
break;
case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, true);
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
break;
default:
HAL_ASSERT(0);
}
}

252
components/soc/esp32h21/include/modem/modem_lpcon_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "modem/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MODEM_LPCON_TEST_CONF_REG register
* No description
*/
#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
/** MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0;
* No description
*/
#define MODEM_LPCON_CLK_EN (BIT(0))
#define MODEM_LPCON_CLK_EN_M (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S)
#define MODEM_LPCON_CLK_EN_V 0x00000001U
#define MODEM_LPCON_CLK_EN_S 0
/** MODEM_LPCON_COEX_LP_CLK_CONF_REG register
* No description
*/
#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4)
/** MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0;
* No description
*/
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0))
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S)
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0
/** MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0;
* No description
*/
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1))
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S)
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1
/** MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0;
* No description
*/
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2))
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S)
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2
/** MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0;
* No description
*/
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3))
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S)
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3
/** MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0;
* No description
*/
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFFU
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0x00000FFFU
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4
/** MODEM_LPCON_CLK_CONF_REG register
* No description
*/
#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8)
/** MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0;
* No description
*/
#define MODEM_LPCON_CLK_COEX_EN (BIT(1))
#define MODEM_LPCON_CLK_COEX_EN_M (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S)
#define MODEM_LPCON_CLK_COEX_EN_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_EN_S 1
/** MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0;
* No description
*/
#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2))
#define MODEM_LPCON_CLK_I2C_MST_EN_M (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S)
#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x00000001U
#define MODEM_LPCON_CLK_I2C_MST_EN_S 2
/** MODEM_LPCON_CLK_FE_MEM_EN : R/W; bitpos: [5]; default: 0;
* No description
*/
#define MODEM_LPCON_CLK_FE_MEM_EN (BIT(5))
#define MODEM_LPCON_CLK_FE_MEM_EN_M (MODEM_LPCON_CLK_FE_MEM_EN_V << MODEM_LPCON_CLK_FE_MEM_EN_S)
#define MODEM_LPCON_CLK_FE_MEM_EN_V 0x00000001U
#define MODEM_LPCON_CLK_FE_MEM_EN_S 5
/** MODEM_LPCON_CLK_CONF_FORCE_ON_REG register
* No description
*/
#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0xc)
/** MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0;
* No description
*/
#define MODEM_LPCON_CLK_COEX_FO (BIT(1))
#define MODEM_LPCON_CLK_COEX_FO_M (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S)
#define MODEM_LPCON_CLK_COEX_FO_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_FO_S 1
/** MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0;
* No description
*/
#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2))
#define MODEM_LPCON_CLK_I2C_MST_FO_M (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S)
#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x00000001U
#define MODEM_LPCON_CLK_I2C_MST_FO_S 2
/** MODEM_LPCON_CLK_FE_MEM_FO : R/W; bitpos: [5]; default: 0;
* No description
*/
#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(5))
#define MODEM_LPCON_CLK_FE_MEM_FO_M (MODEM_LPCON_CLK_FE_MEM_FO_V << MODEM_LPCON_CLK_FE_MEM_FO_S)
#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x00000001U
#define MODEM_LPCON_CLK_FE_MEM_FO_S 5
/** MODEM_LPCON_TICK_CONF_REG register
* No description
*/
#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10)
/** MODEM_LPCON_PWR_TICK_TARGET : RO; bitpos: [31:6]; default: 0;
* No description
*/
#define MODEM_LPCON_PWR_TICK_TARGET 0x03FFFFFFU
#define MODEM_LPCON_PWR_TICK_TARGET_M (MODEM_LPCON_PWR_TICK_TARGET_V << MODEM_LPCON_PWR_TICK_TARGET_S)
#define MODEM_LPCON_PWR_TICK_TARGET_V 0x03FFFFFFU
#define MODEM_LPCON_PWR_TICK_TARGET_S 6
/** MODEM_LPCON_RST_CONF_REG register
* No description
*/
#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
/** MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0;
* No description
*/
#define MODEM_LPCON_RST_COEX (BIT(1))
#define MODEM_LPCON_RST_COEX_M (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S)
#define MODEM_LPCON_RST_COEX_V 0x00000001U
#define MODEM_LPCON_RST_COEX_S 1
/** MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0;
* No description
*/
#define MODEM_LPCON_RST_I2C_MST (BIT(2))
#define MODEM_LPCON_RST_I2C_MST_M (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S)
#define MODEM_LPCON_RST_I2C_MST_V 0x00000001U
#define MODEM_LPCON_RST_I2C_MST_S 2
/** MODEM_LPCON_MEM_CONF_REG register
* No description
*/
#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18)
/** MODEM_LPCON_AGC_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
* No description
*/
#define MODEM_LPCON_AGC_MEM_FORCE_PU (BIT(2))
#define MODEM_LPCON_AGC_MEM_FORCE_PU_M (MODEM_LPCON_AGC_MEM_FORCE_PU_V << MODEM_LPCON_AGC_MEM_FORCE_PU_S)
#define MODEM_LPCON_AGC_MEM_FORCE_PU_V 0x00000001U
#define MODEM_LPCON_AGC_MEM_FORCE_PU_S 2
/** MODEM_LPCON_AGC_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0;
* No description
*/
#define MODEM_LPCON_AGC_MEM_FORCE_PD (BIT(3))
#define MODEM_LPCON_AGC_MEM_FORCE_PD_M (MODEM_LPCON_AGC_MEM_FORCE_PD_V << MODEM_LPCON_AGC_MEM_FORCE_PD_S)
#define MODEM_LPCON_AGC_MEM_FORCE_PD_V 0x00000001U
#define MODEM_LPCON_AGC_MEM_FORCE_PD_S 3
/** MODEM_LPCON_PBUS_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1;
* No description
*/
#define MODEM_LPCON_PBUS_MEM_FORCE_PU (BIT(4))
#define MODEM_LPCON_PBUS_MEM_FORCE_PU_M (MODEM_LPCON_PBUS_MEM_FORCE_PU_V << MODEM_LPCON_PBUS_MEM_FORCE_PU_S)
#define MODEM_LPCON_PBUS_MEM_FORCE_PU_V 0x00000001U
#define MODEM_LPCON_PBUS_MEM_FORCE_PU_S 4
/** MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
* No description
*/
#define MODEM_LPCON_PBUS_MEM_FORCE_PD (BIT(5))
#define MODEM_LPCON_PBUS_MEM_FORCE_PD_M (MODEM_LPCON_PBUS_MEM_FORCE_PD_V << MODEM_LPCON_PBUS_MEM_FORCE_PD_S)
#define MODEM_LPCON_PBUS_MEM_FORCE_PD_V 0x00000001U
#define MODEM_LPCON_PBUS_MEM_FORCE_PD_S 5
/** MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W; bitpos: [8]; default: 0;
* No description
*/
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU (BIT(8))
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_M (MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S)
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V 0x00000001U
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S 8
/** MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W; bitpos: [9]; default: 0;
* No description
*/
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD (BIT(9))
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_M (MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S)
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V 0x00000001U
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S 9
/** MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU : R/W; bitpos: [10]; default: 0;
* No description
*/
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU (BIT(10))
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S)
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V 0x00000001U
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S 10
/** MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD : R/W; bitpos: [11]; default: 0;
* No description
*/
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD (BIT(11))
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S)
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V 0x00000001U
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S 11
/** MODEM_LPCON_MODEM_PWR_MEM_WP : R/W; bitpos: [14:12]; default: 0;
* No description
*/
#define MODEM_LPCON_MODEM_PWR_MEM_WP 0x00000007U
#define MODEM_LPCON_MODEM_PWR_MEM_WP_M (MODEM_LPCON_MODEM_PWR_MEM_WP_V << MODEM_LPCON_MODEM_PWR_MEM_WP_S)
#define MODEM_LPCON_MODEM_PWR_MEM_WP_V 0x00000007U
#define MODEM_LPCON_MODEM_PWR_MEM_WP_S 12
/** MODEM_LPCON_MODEM_PWR_MEM_WA : R/W; bitpos: [17:15]; default: 5;
* No description
*/
#define MODEM_LPCON_MODEM_PWR_MEM_WA 0x00000007U
#define MODEM_LPCON_MODEM_PWR_MEM_WA_M (MODEM_LPCON_MODEM_PWR_MEM_WA_V << MODEM_LPCON_MODEM_PWR_MEM_WA_S)
#define MODEM_LPCON_MODEM_PWR_MEM_WA_V 0x00000007U
#define MODEM_LPCON_MODEM_PWR_MEM_WA_S 15
/** MODEM_LPCON_MODEM_PWR_MEM_RA : R/W; bitpos: [19:18]; default: 0;
* No description
*/
#define MODEM_LPCON_MODEM_PWR_MEM_RA 0x00000003U
#define MODEM_LPCON_MODEM_PWR_MEM_RA_M (MODEM_LPCON_MODEM_PWR_MEM_RA_V << MODEM_LPCON_MODEM_PWR_MEM_RA_S)
#define MODEM_LPCON_MODEM_PWR_MEM_RA_V 0x00000003U
#define MODEM_LPCON_MODEM_PWR_MEM_RA_S 18
/** MODEM_LPCON_MODEM_PWR_MEM_RM : R/W; bitpos: [23:20]; default: 2;
* No description
*/
#define MODEM_LPCON_MODEM_PWR_MEM_RM 0x0000000FU
#define MODEM_LPCON_MODEM_PWR_MEM_RM_M (MODEM_LPCON_MODEM_PWR_MEM_RM_V << MODEM_LPCON_MODEM_PWR_MEM_RM_S)
#define MODEM_LPCON_MODEM_PWR_MEM_RM_V 0x0000000FU
#define MODEM_LPCON_MODEM_PWR_MEM_RM_S 20
/** MODEM_LPCON_DATE_REG register
* No description
*/
#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x1c)
/** MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 35689088;
* No description
*/
#define MODEM_LPCON_DATE 0x0FFFFFFFU
#define MODEM_LPCON_DATE_M (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S)
#define MODEM_LPCON_DATE_V 0x0FFFFFFFU
#define MODEM_LPCON_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/include/modem/modem_lpcon_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of test_conf register
* No description
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* No description
*/
uint32_t clk_en: 1;
uint32_t reserved_1: 31;
};
uint32_t val;
} modem_lpcon_test_conf_reg_t;
/** Type of coex_lp_clk_conf register
* No description
*/
typedef union {
struct {
/** clk_coex_lp_sel_osc_slow : R/W; bitpos: [0]; default: 0;
* No description
*/
uint32_t clk_coex_lp_sel_osc_slow: 1;
/** clk_coex_lp_sel_osc_fast : R/W; bitpos: [1]; default: 0;
* No description
*/
uint32_t clk_coex_lp_sel_osc_fast: 1;
/** clk_coex_lp_sel_xtal : R/W; bitpos: [2]; default: 0;
* No description
*/
uint32_t clk_coex_lp_sel_xtal: 1;
/** clk_coex_lp_sel_xtal32k : R/W; bitpos: [3]; default: 0;
* No description
*/
uint32_t clk_coex_lp_sel_xtal32k: 1;
/** clk_coex_lp_div_num : R/W; bitpos: [15:4]; default: 0;
* No description
*/
uint32_t clk_coex_lp_div_num: 12;
uint32_t reserved_16: 16;
};
uint32_t val;
} modem_lpcon_coex_lp_clk_conf_reg_t;
/** Type of clk_conf register
* No description
*/
typedef union {
struct {
uint32_t reserved_0: 1;
/** clk_coex_en : R/W; bitpos: [1]; default: 0;
* No description
*/
uint32_t clk_coex_en: 1;
/** clk_i2c_mst_en : R/W; bitpos: [2]; default: 0;
* No description
*/
uint32_t clk_i2c_mst_en: 1;
uint32_t reserved_3: 2;
/** clk_fe_mem_en : R/W; bitpos: [5]; default: 0;
* No description
*/
uint32_t clk_fe_mem_en: 1;
uint32_t reserved_6: 26;
};
uint32_t val;
} modem_lpcon_clk_conf_reg_t;
/** Type of clk_conf_force_on register
* No description
*/
typedef union {
struct {
uint32_t reserved_0: 1;
/** clk_coex_fo : R/W; bitpos: [1]; default: 0;
* No description
*/
uint32_t clk_coex_fo: 1;
/** clk_i2c_mst_fo : R/W; bitpos: [2]; default: 0;
* No description
*/
uint32_t clk_i2c_mst_fo: 1;
uint32_t reserved_3: 2;
/** clk_fe_mem_fo : R/W; bitpos: [5]; default: 0;
* No description
*/
uint32_t clk_fe_mem_fo: 1;
uint32_t reserved_6: 26;
};
uint32_t val;
} modem_lpcon_clk_conf_force_on_reg_t;
/** Type of tick_conf register
* No description
*/
typedef union {
struct {
uint32_t reserved_0: 6;
/** pwr_tick_target : RO; bitpos: [31:6]; default: 0;
* No description
*/
uint32_t pwr_tick_target: 26;
};
uint32_t val;
} modem_lpcon_tick_conf_reg_t;
/** Type of rst_conf register
* No description
*/
typedef union {
struct {
uint32_t reserved_0: 1;
/** rst_coex : WO; bitpos: [1]; default: 0;
* No description
*/
uint32_t rst_coex: 1;
/** rst_i2c_mst : WO; bitpos: [2]; default: 0;
* No description
*/
uint32_t rst_i2c_mst: 1;
uint32_t reserved_3: 29;
};
uint32_t val;
} modem_lpcon_rst_conf_reg_t;
/** Type of mem_conf register
* No description
*/
typedef union {
struct {
uint32_t reserved_0: 2;
/** agc_mem_force_pu : R/W; bitpos: [2]; default: 1;
* No description
*/
uint32_t agc_mem_force_pu: 1;
/** agc_mem_force_pd : R/W; bitpos: [3]; default: 0;
* No description
*/
uint32_t agc_mem_force_pd: 1;
/** pbus_mem_force_pu : R/W; bitpos: [4]; default: 1;
* No description
*/
uint32_t pbus_mem_force_pu: 1;
/** pbus_mem_force_pd : R/W; bitpos: [5]; default: 0;
* No description
*/
uint32_t pbus_mem_force_pd: 1;
uint32_t reserved_6: 2;
/** i2c_mst_mem_force_pu : R/W; bitpos: [8]; default: 0;
* No description
*/
uint32_t i2c_mst_mem_force_pu: 1;
/** i2c_mst_mem_force_pd : R/W; bitpos: [9]; default: 0;
* No description
*/
uint32_t i2c_mst_mem_force_pd: 1;
/** chan_freq_mem_force_pu : R/W; bitpos: [10]; default: 0;
* No description
*/
uint32_t chan_freq_mem_force_pu: 1;
/** chan_freq_mem_force_pd : R/W; bitpos: [11]; default: 0;
* No description
*/
uint32_t chan_freq_mem_force_pd: 1;
/** modem_pwr_mem_wp : R/W; bitpos: [14:12]; default: 0;
* No description
*/
uint32_t modem_pwr_mem_wp: 3;
/** modem_pwr_mem_wa : R/W; bitpos: [17:15]; default: 5;
* No description
*/
uint32_t modem_pwr_mem_wa: 3;
/** modem_pwr_mem_ra : R/W; bitpos: [19:18]; default: 0;
* No description
*/
uint32_t modem_pwr_mem_ra: 2;
/** modem_pwr_mem_rm : R/W; bitpos: [23:20]; default: 2;
* No description
*/
uint32_t modem_pwr_mem_rm: 4;
uint32_t reserved_24: 8;
};
uint32_t val;
} modem_lpcon_mem_conf_reg_t;
/** Group: Version Register */
/** Type of date register
* No description
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35689088;
* No description
*/
uint32_t date: 28;
uint32_t reserved_28: 4;
};
uint32_t val;
} modem_lpcon_date_reg_t;
typedef struct {
volatile modem_lpcon_test_conf_reg_t test_conf;
volatile modem_lpcon_coex_lp_clk_conf_reg_t coex_lp_clk_conf;
volatile modem_lpcon_clk_conf_reg_t clk_conf;
volatile modem_lpcon_clk_conf_force_on_reg_t clk_conf_force_on;
volatile modem_lpcon_tick_conf_reg_t tick_conf;
volatile modem_lpcon_rst_conf_reg_t rst_conf;
volatile modem_lpcon_mem_conf_reg_t mem_conf;
volatile modem_lpcon_date_reg_t date;
} modem_lpcon_dev_t;
extern modem_lpcon_dev_t MODEM_LPCON;
#ifndef __cplusplus
_Static_assert(sizeof(modem_lpcon_dev_t) == 0x20, "Invalid size of modem_lpcon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

378
components/soc/esp32h21/include/modem/modem_syscon_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "modem/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MODEM_SYSCON_TEST_CONF_REG register
* No description
*/
#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0)
/** MODEM_SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_EN (BIT(0))
#define MODEM_SYSCON_CLK_EN_M (MODEM_SYSCON_CLK_EN_V << MODEM_SYSCON_CLK_EN_S)
#define MODEM_SYSCON_CLK_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_EN_S 0
/** MODEM_SYSCON_CLK_CONF_REG register
* No description
*/
#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4)
/** MODEM_SYSCON_CLK_ETM_EN : R/W; bitpos: [21]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_ETM_EN (BIT(21))
#define MODEM_SYSCON_CLK_ETM_EN_M (MODEM_SYSCON_CLK_ETM_EN_V << MODEM_SYSCON_CLK_ETM_EN_S)
#define MODEM_SYSCON_CLK_ETM_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_ETM_EN_S 21
/** MODEM_SYSCON_CLK_ZB_APB_EN : R/W; bitpos: [22]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(22))
#define MODEM_SYSCON_CLK_ZB_APB_EN_M (MODEM_SYSCON_CLK_ZB_APB_EN_V << MODEM_SYSCON_CLK_ZB_APB_EN_S)
#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_ZB_APB_EN_S 22
/** MODEM_SYSCON_CLK_ZB_MAC_EN : R/W; bitpos: [23]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_ZB_MAC_EN (BIT(23))
#define MODEM_SYSCON_CLK_ZB_MAC_EN_M (MODEM_SYSCON_CLK_ZB_MAC_EN_V << MODEM_SYSCON_CLK_ZB_MAC_EN_S)
#define MODEM_SYSCON_CLK_ZB_MAC_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_ZB_MAC_EN_S 23
/** MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W; bitpos: [24]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(24))
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 24
/** MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W; bitpos: [25]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(25))
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 25
/** MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W; bitpos: [26]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(26))
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 26
/** MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W; bitpos: [27]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(27))
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 27
/** MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W; bitpos: [28]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(28))
#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_EN_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 28
/** MODEM_SYSCON_CLK_BLE_TIMER_APB_EN : R/W; bitpos: [29]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN (BIT(29))
#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_M (MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_S)
#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_S 29
/** MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W; bitpos: [30]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30))
#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (MODEM_SYSCON_CLK_BLE_TIMER_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_EN_S)
#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30
/** MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W; bitpos: [31]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31))
#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (MODEM_SYSCON_CLK_DATA_DUMP_EN_V << MODEM_SYSCON_CLK_DATA_DUMP_EN_S)
#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31
/** MODEM_SYSCON_CLK_CONF_FORCE_ON_REG register
* No description
*/
#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8)
/** MODEM_SYSCON_CLK_ETM_FO : R/W; bitpos: [22]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_ETM_FO (BIT(22))
#define MODEM_SYSCON_CLK_ETM_FO_M (MODEM_SYSCON_CLK_ETM_FO_V << MODEM_SYSCON_CLK_ETM_FO_S)
#define MODEM_SYSCON_CLK_ETM_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_ETM_FO_S 22
/** MODEM_SYSCON_CLK_ZB_FO : R/W; bitpos: [24]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_ZB_FO (BIT(24))
#define MODEM_SYSCON_CLK_ZB_FO_M (MODEM_SYSCON_CLK_ZB_FO_V << MODEM_SYSCON_CLK_ZB_FO_S)
#define MODEM_SYSCON_CLK_ZB_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_ZB_FO_S 24
/** MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W; bitpos: [29]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29))
#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_FO_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29
/** MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W; bitpos: [30]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30))
#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (MODEM_SYSCON_CLK_BLE_TIMER_FO_V << MODEM_SYSCON_CLK_BLE_TIMER_FO_S)
#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30
/** MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W; bitpos: [31]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31))
#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (MODEM_SYSCON_CLK_DATA_DUMP_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_FO_S)
#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31
/** MODEM_SYSCON_MODEM_RST_CONF_REG register
* No description
*/
#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0xc)
/** MODEM_SYSCON_RST_FE : R/W; bitpos: [14]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_FE (BIT(14))
#define MODEM_SYSCON_RST_FE_M (MODEM_SYSCON_RST_FE_V << MODEM_SYSCON_RST_FE_S)
#define MODEM_SYSCON_RST_FE_V 0x00000001U
#define MODEM_SYSCON_RST_FE_S 14
/** MODEM_SYSCON_RST_BTMAC_APB : R/W; bitpos: [15]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15))
#define MODEM_SYSCON_RST_BTMAC_APB_M (MODEM_SYSCON_RST_BTMAC_APB_V << MODEM_SYSCON_RST_BTMAC_APB_S)
#define MODEM_SYSCON_RST_BTMAC_APB_V 0x00000001U
#define MODEM_SYSCON_RST_BTMAC_APB_S 15
/** MODEM_SYSCON_RST_BTMAC : R/W; bitpos: [16]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_BTMAC (BIT(16))
#define MODEM_SYSCON_RST_BTMAC_M (MODEM_SYSCON_RST_BTMAC_V << MODEM_SYSCON_RST_BTMAC_S)
#define MODEM_SYSCON_RST_BTMAC_V 0x00000001U
#define MODEM_SYSCON_RST_BTMAC_S 16
/** MODEM_SYSCON_RST_BTBB_APB : R/W; bitpos: [17]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_BTBB_APB (BIT(17))
#define MODEM_SYSCON_RST_BTBB_APB_M (MODEM_SYSCON_RST_BTBB_APB_V << MODEM_SYSCON_RST_BTBB_APB_S)
#define MODEM_SYSCON_RST_BTBB_APB_V 0x00000001U
#define MODEM_SYSCON_RST_BTBB_APB_S 17
/** MODEM_SYSCON_RST_BTBB : R/W; bitpos: [18]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_BTBB (BIT(18))
#define MODEM_SYSCON_RST_BTBB_M (MODEM_SYSCON_RST_BTBB_V << MODEM_SYSCON_RST_BTBB_S)
#define MODEM_SYSCON_RST_BTBB_V 0x00000001U
#define MODEM_SYSCON_RST_BTBB_S 18
/** MODEM_SYSCON_RST_ETM : R/W; bitpos: [22]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_ETM (BIT(22))
#define MODEM_SYSCON_RST_ETM_M (MODEM_SYSCON_RST_ETM_V << MODEM_SYSCON_RST_ETM_S)
#define MODEM_SYSCON_RST_ETM_V 0x00000001U
#define MODEM_SYSCON_RST_ETM_S 22
/** MODEM_SYSCON_RST_ZBMAC_APB : R/W; bitpos: [23]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_ZBMAC_APB (BIT(23))
#define MODEM_SYSCON_RST_ZBMAC_APB_M (MODEM_SYSCON_RST_ZBMAC_APB_V << MODEM_SYSCON_RST_ZBMAC_APB_S)
#define MODEM_SYSCON_RST_ZBMAC_APB_V 0x00000001U
#define MODEM_SYSCON_RST_ZBMAC_APB_S 23
/** MODEM_SYSCON_RST_ZBMAC : R/W; bitpos: [24]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_ZBMAC (BIT(24))
#define MODEM_SYSCON_RST_ZBMAC_M (MODEM_SYSCON_RST_ZBMAC_V << MODEM_SYSCON_RST_ZBMAC_S)
#define MODEM_SYSCON_RST_ZBMAC_V 0x00000001U
#define MODEM_SYSCON_RST_ZBMAC_S 24
/** MODEM_SYSCON_RST_MODEM_ECB : R/W; bitpos: [25]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25))
#define MODEM_SYSCON_RST_MODEM_ECB_M (MODEM_SYSCON_RST_MODEM_ECB_V << MODEM_SYSCON_RST_MODEM_ECB_S)
#define MODEM_SYSCON_RST_MODEM_ECB_V 0x00000001U
#define MODEM_SYSCON_RST_MODEM_ECB_S 25
/** MODEM_SYSCON_RST_MODEM_CCM : R/W; bitpos: [26]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26))
#define MODEM_SYSCON_RST_MODEM_CCM_M (MODEM_SYSCON_RST_MODEM_CCM_V << MODEM_SYSCON_RST_MODEM_CCM_S)
#define MODEM_SYSCON_RST_MODEM_CCM_V 0x00000001U
#define MODEM_SYSCON_RST_MODEM_CCM_S 26
/** MODEM_SYSCON_RST_MODEM_BAH : R/W; bitpos: [27]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27))
#define MODEM_SYSCON_RST_MODEM_BAH_M (MODEM_SYSCON_RST_MODEM_BAH_V << MODEM_SYSCON_RST_MODEM_BAH_S)
#define MODEM_SYSCON_RST_MODEM_BAH_V 0x00000001U
#define MODEM_SYSCON_RST_MODEM_BAH_S 27
/** MODEM_SYSCON_RST_MODEM_SEC : R/W; bitpos: [29]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29))
#define MODEM_SYSCON_RST_MODEM_SEC_M (MODEM_SYSCON_RST_MODEM_SEC_V << MODEM_SYSCON_RST_MODEM_SEC_S)
#define MODEM_SYSCON_RST_MODEM_SEC_V 0x00000001U
#define MODEM_SYSCON_RST_MODEM_SEC_S 29
/** MODEM_SYSCON_RST_BLE_TIMER : R/W; bitpos: [30]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30))
#define MODEM_SYSCON_RST_BLE_TIMER_M (MODEM_SYSCON_RST_BLE_TIMER_V << MODEM_SYSCON_RST_BLE_TIMER_S)
#define MODEM_SYSCON_RST_BLE_TIMER_V 0x00000001U
#define MODEM_SYSCON_RST_BLE_TIMER_S 30
/** MODEM_SYSCON_RST_DATA_DUMP : R/W; bitpos: [31]; default: 0;
* No description
*/
#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31))
#define MODEM_SYSCON_RST_DATA_DUMP_M (MODEM_SYSCON_RST_DATA_DUMP_V << MODEM_SYSCON_RST_DATA_DUMP_S)
#define MODEM_SYSCON_RST_DATA_DUMP_V 0x00000001U
#define MODEM_SYSCON_RST_DATA_DUMP_S 31
/** MODEM_SYSCON_CLK_CONF1_REG register
* No description
*/
#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x10)
/** MODEM_SYSCON_CLK_FE_TXLOGAIN_EN : R/W; bitpos: [11]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_FE_TXLOGAIN_EN (BIT(11))
#define MODEM_SYSCON_CLK_FE_TXLOGAIN_EN_M (MODEM_SYSCON_CLK_FE_TXLOGAIN_EN_V << MODEM_SYSCON_CLK_FE_TXLOGAIN_EN_S)
#define MODEM_SYSCON_CLK_FE_TXLOGAIN_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_TXLOGAIN_EN_S 11
/** MODEM_SYSCON_CLK_FE_16M_EN : R/W; bitpos: [12]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_FE_16M_EN (BIT(12))
#define MODEM_SYSCON_CLK_FE_16M_EN_M (MODEM_SYSCON_CLK_FE_16M_EN_V << MODEM_SYSCON_CLK_FE_16M_EN_S)
#define MODEM_SYSCON_CLK_FE_16M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_16M_EN_S 12
/** MODEM_SYSCON_CLK_FE_32M_EN : R/W; bitpos: [13]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_FE_32M_EN (BIT(13))
#define MODEM_SYSCON_CLK_FE_32M_EN_M (MODEM_SYSCON_CLK_FE_32M_EN_V << MODEM_SYSCON_CLK_FE_32M_EN_S)
#define MODEM_SYSCON_CLK_FE_32M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_32M_EN_S 13
/** MODEM_SYSCON_CLK_FE_SDM_EN : R/W; bitpos: [14]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_FE_SDM_EN (BIT(14))
#define MODEM_SYSCON_CLK_FE_SDM_EN_M (MODEM_SYSCON_CLK_FE_SDM_EN_V << MODEM_SYSCON_CLK_FE_SDM_EN_S)
#define MODEM_SYSCON_CLK_FE_SDM_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_SDM_EN_S 14
/** MODEM_SYSCON_CLK_FE_ADC_EN : R/W; bitpos: [15]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(15))
#define MODEM_SYSCON_CLK_FE_ADC_EN_M (MODEM_SYSCON_CLK_FE_ADC_EN_V << MODEM_SYSCON_CLK_FE_ADC_EN_S)
#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_ADC_EN_S 15
/** MODEM_SYSCON_CLK_FE_APB_EN : R/W; bitpos: [16]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(16))
#define MODEM_SYSCON_CLK_FE_APB_EN_M (MODEM_SYSCON_CLK_FE_APB_EN_V << MODEM_SYSCON_CLK_FE_APB_EN_S)
#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_APB_EN_S 16
/** MODEM_SYSCON_CLK_BT_APB_EN : R/W; bitpos: [17]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(17))
#define MODEM_SYSCON_CLK_BT_APB_EN_M (MODEM_SYSCON_CLK_BT_APB_EN_V << MODEM_SYSCON_CLK_BT_APB_EN_S)
#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_BT_APB_EN_S 17
/** MODEM_SYSCON_CLK_BT_EN : R/W; bitpos: [18]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_BT_EN (BIT(18))
#define MODEM_SYSCON_CLK_BT_EN_M (MODEM_SYSCON_CLK_BT_EN_V << MODEM_SYSCON_CLK_BT_EN_S)
#define MODEM_SYSCON_CLK_BT_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_BT_EN_S 18
/** MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG register
* No description
*/
#define MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x14)
/** MODEM_SYSCON_CLK_FE_FO : R/W; bitpos: [16]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_FE_FO (BIT(16))
#define MODEM_SYSCON_CLK_FE_FO_M (MODEM_SYSCON_CLK_FE_FO_V << MODEM_SYSCON_CLK_FE_FO_S)
#define MODEM_SYSCON_CLK_FE_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_FO_S 16
/** MODEM_SYSCON_CLK_BT_FO : R/W; bitpos: [18]; default: 0;
* No description
*/
#define MODEM_SYSCON_CLK_BT_FO (BIT(18))
#define MODEM_SYSCON_CLK_BT_FO_M (MODEM_SYSCON_CLK_BT_FO_V << MODEM_SYSCON_CLK_BT_FO_S)
#define MODEM_SYSCON_CLK_BT_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_BT_FO_S 18
/** MODEM_SYSCON_MEM_CONF_REG register
* No description
*/
#define MODEM_SYSCON_MEM_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x18)
/** MODEM_SYSCON_MODEM_MEM_WP : R/W; bitpos: [2:0]; default: 0;
* No description
*/
#define MODEM_SYSCON_MODEM_MEM_WP 0x00000007U
#define MODEM_SYSCON_MODEM_MEM_WP_M (MODEM_SYSCON_MODEM_MEM_WP_V << MODEM_SYSCON_MODEM_MEM_WP_S)
#define MODEM_SYSCON_MODEM_MEM_WP_V 0x00000007U
#define MODEM_SYSCON_MODEM_MEM_WP_S 0
/** MODEM_SYSCON_MODEM_MEM_WA : R/W; bitpos: [5:3]; default: 5;
* No description
*/
#define MODEM_SYSCON_MODEM_MEM_WA 0x00000007U
#define MODEM_SYSCON_MODEM_MEM_WA_M (MODEM_SYSCON_MODEM_MEM_WA_V << MODEM_SYSCON_MODEM_MEM_WA_S)
#define MODEM_SYSCON_MODEM_MEM_WA_V 0x00000007U
#define MODEM_SYSCON_MODEM_MEM_WA_S 3
/** MODEM_SYSCON_MODEM_MEM_RA : R/W; bitpos: [7:6]; default: 0;
* No description
*/
#define MODEM_SYSCON_MODEM_MEM_RA 0x00000003U
#define MODEM_SYSCON_MODEM_MEM_RA_M (MODEM_SYSCON_MODEM_MEM_RA_V << MODEM_SYSCON_MODEM_MEM_RA_S)
#define MODEM_SYSCON_MODEM_MEM_RA_V 0x00000003U
#define MODEM_SYSCON_MODEM_MEM_RA_S 6
/** MODEM_SYSCON_MODEM_MEM_RM : R/W; bitpos: [11:8]; default: 2;
* No description
*/
#define MODEM_SYSCON_MODEM_MEM_RM 0x0000000FU
#define MODEM_SYSCON_MODEM_MEM_RM_M (MODEM_SYSCON_MODEM_MEM_RM_V << MODEM_SYSCON_MODEM_MEM_RM_S)
#define MODEM_SYSCON_MODEM_MEM_RM_V 0x0000000FU
#define MODEM_SYSCON_MODEM_MEM_RM_S 8
/** MODEM_SYSCON_DATE_REG register
* No description
*/
#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x1c)
/** MODEM_SYSCON_DATE : R/W; bitpos: [27:0]; default: 37785904;
* No description
*/
#define MODEM_SYSCON_DATE 0x0FFFFFFFU
#define MODEM_SYSCON_DATE_M (MODEM_SYSCON_DATE_V << MODEM_SYSCON_DATE_S)
#define MODEM_SYSCON_DATE_V 0x0FFFFFFFU
#define MODEM_SYSCON_DATE_S 0
#ifdef __cplusplus
}
#endif

305
components/soc/esp32h21/include/modem/modem_syscon_struct.h Normal file
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@ -0,0 +1,305 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of test_conf register
* No description
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* No description
*/
uint32_t clk_en: 1;
uint32_t reserved_1: 31;
};
uint32_t val;
} modem_syscon_test_conf_reg_t;
/** Type of clk_conf register
* No description
*/
typedef union {
struct {
uint32_t reserved_0: 21;
/** clk_etm_en : R/W; bitpos: [21]; default: 0;
* No description
*/
uint32_t clk_etm_en: 1;
/** clk_zb_apb_en : R/W; bitpos: [22]; default: 0;
* No description
*/
uint32_t clk_zb_apb_en: 1;
/** clk_zb_mac_en : R/W; bitpos: [23]; default: 0;
* No description
*/
uint32_t clk_zb_mac_en: 1;
/** clk_modem_sec_ecb_en : R/W; bitpos: [24]; default: 0;
* No description
*/
uint32_t clk_modem_sec_ecb_en: 1;
/** clk_modem_sec_ccm_en : R/W; bitpos: [25]; default: 0;
* No description
*/
uint32_t clk_modem_sec_ccm_en: 1;
/** clk_modem_sec_bah_en : R/W; bitpos: [26]; default: 0;
* No description
*/
uint32_t clk_modem_sec_bah_en: 1;
/** clk_modem_sec_apb_en : R/W; bitpos: [27]; default: 0;
* No description
*/
uint32_t clk_modem_sec_apb_en: 1;
/** clk_modem_sec_en : R/W; bitpos: [28]; default: 0;
* No description
*/
uint32_t clk_modem_sec_en: 1;
/** clk_ble_timer_apb_en : R/W; bitpos: [29]; default: 0;
* No description
*/
uint32_t clk_ble_timer_apb_en: 1;
/** clk_ble_timer_en : R/W; bitpos: [30]; default: 0;
* No description
*/
uint32_t clk_ble_timer_en: 1;
/** clk_data_dump_en : R/W; bitpos: [31]; default: 0;
* No description
*/
uint32_t clk_data_dump_en: 1;
};
uint32_t val;
} modem_syscon_clk_conf_reg_t;
/** Type of clk_conf_force_on register
* No description
*/
typedef union {
struct {
uint32_t reserved_0: 22;
/** clk_etm_fo : R/W; bitpos: [22]; default: 0;
* No description
*/
uint32_t clk_etm_fo: 1;
uint32_t reserved_23: 1;
/** clk_zb_fo : R/W; bitpos: [24]; default: 0;
* No description
*/
uint32_t clk_zb_fo: 1;
uint32_t reserved_25: 4;
/** clk_modem_sec_fo : R/W; bitpos: [29]; default: 0;
* No description
*/
uint32_t clk_modem_sec_fo: 1;
/** clk_ble_timer_fo : R/W; bitpos: [30]; default: 0;
* No description
*/
uint32_t clk_ble_timer_fo: 1;
/** clk_data_dump_fo : R/W; bitpos: [31]; default: 0;
* No description
*/
uint32_t clk_data_dump_fo: 1;
};
uint32_t val;
} modem_syscon_clk_conf_force_on_reg_t;
/** Type of modem_rst_conf register
* No description
*/
typedef union {
struct {
uint32_t reserved_0: 14;
/** rst_fe : R/W; bitpos: [14]; default: 0;
* No description
*/
uint32_t rst_fe: 1;
/** rst_btmac_apb : R/W; bitpos: [15]; default: 0;
* No description
*/
uint32_t rst_btmac_apb: 1;
/** rst_btmac : R/W; bitpos: [16]; default: 0;
* No description
*/
uint32_t rst_btmac: 1;
/** rst_btbb_apb : R/W; bitpos: [17]; default: 0;
* No description
*/
uint32_t rst_btbb_apb: 1;
/** rst_btbb : R/W; bitpos: [18]; default: 0;
* No description
*/
uint32_t rst_btbb: 1;
uint32_t reserved_19: 3;
/** rst_etm : R/W; bitpos: [22]; default: 0;
* No description
*/
uint32_t rst_etm: 1;
/** rst_zbmac_apb : R/W; bitpos: [23]; default: 0;
* No description
*/
uint32_t rst_zbmac_apb: 1;
/** rst_zbmac : R/W; bitpos: [24]; default: 0;
* No description
*/
uint32_t rst_zbmac: 1;
/** rst_modem_ecb : R/W; bitpos: [25]; default: 0;
* No description
*/
uint32_t rst_modem_ecb: 1;
/** rst_modem_ccm : R/W; bitpos: [26]; default: 0;
* No description
*/
uint32_t rst_modem_ccm: 1;
/** rst_modem_bah : R/W; bitpos: [27]; default: 0;
* No description
*/
uint32_t rst_modem_bah: 1;
uint32_t reserved_28: 1;
/** rst_modem_sec : R/W; bitpos: [29]; default: 0;
* No description
*/
uint32_t rst_modem_sec: 1;
/** rst_ble_timer : R/W; bitpos: [30]; default: 0;
* No description
*/
uint32_t rst_ble_timer: 1;
/** rst_data_dump : R/W; bitpos: [31]; default: 0;
* No description
*/
uint32_t rst_data_dump: 1;
};
uint32_t val;
} modem_syscon_modem_rst_conf_reg_t;
/** Type of clk_conf1 register
* No description
*/
typedef union {
struct {
uint32_t reserved_0: 11;
/** clk_fe_txlogain_en : R/W; bitpos: [11]; default: 0;
* No description
*/
uint32_t clk_fe_txlogain_en: 1;
/** clk_fe_16m_en : R/W; bitpos: [12]; default: 0;
* No description
*/
uint32_t clk_fe_16m_en: 1;
/** clk_fe_32m_en : R/W; bitpos: [13]; default: 0;
* No description
*/
uint32_t clk_fe_32m_en: 1;
/** clk_fe_sdm_en : R/W; bitpos: [14]; default: 0;
* No description
*/
uint32_t clk_fe_sdm_en: 1;
/** clk_fe_adc_en : R/W; bitpos: [15]; default: 0;
* No description
*/
uint32_t clk_fe_adc_en: 1;
/** clk_fe_apb_en : R/W; bitpos: [16]; default: 0;
* No description
*/
uint32_t clk_fe_apb_en: 1;
/** clk_bt_apb_en : R/W; bitpos: [17]; default: 0;
* No description
*/
uint32_t clk_bt_apb_en: 1;
/** clk_bt_en : R/W; bitpos: [18]; default: 0;
* No description
*/
uint32_t clk_bt_en: 1;
uint32_t reserved_19: 13;
};
uint32_t val;
} modem_syscon_clk_conf1_reg_t;
/** Type of clk_conf1_force_on register
* No description
*/
typedef union {
struct {
uint32_t reserved_0: 16;
/** clk_fe_fo : R/W; bitpos: [16]; default: 0;
* No description
*/
uint32_t clk_fe_fo: 1;
uint32_t reserved_17: 1;
/** clk_bt_fo : R/W; bitpos: [18]; default: 0;
* No description
*/
uint32_t clk_bt_fo: 1;
uint32_t reserved_19: 13;
};
uint32_t val;
} modem_syscon_clk_conf1_force_on_reg_t;
/** Type of mem_conf register
* No description
*/
typedef union {
struct {
/** modem_mem_wp : R/W; bitpos: [2:0]; default: 0;
* No description
*/
uint32_t modem_mem_wp: 3;
/** modem_mem_wa : R/W; bitpos: [5:3]; default: 5;
* No description
*/
uint32_t modem_mem_wa: 3;
/** modem_mem_ra : R/W; bitpos: [7:6]; default: 0;
* No description
*/
uint32_t modem_mem_ra: 2;
/** modem_mem_rm : R/W; bitpos: [11:8]; default: 2;
* No description
*/
uint32_t modem_mem_rm: 4;
uint32_t reserved_12: 20;
};
uint32_t val;
} modem_syscon_mem_conf_reg_t;
/** Group: Version Register */
/** Type of date register
* No description
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37785904;
* No description
*/
uint32_t date: 28;
uint32_t reserved_28: 4;
};
uint32_t val;
} modem_syscon_date_reg_t;
typedef struct {
volatile modem_syscon_test_conf_reg_t test_conf;
volatile modem_syscon_clk_conf_reg_t clk_conf;
volatile modem_syscon_clk_conf_force_on_reg_t clk_conf_force_on;
volatile modem_syscon_modem_rst_conf_reg_t modem_rst_conf;
volatile modem_syscon_clk_conf1_reg_t clk_conf1;
volatile modem_syscon_clk_conf1_force_on_reg_t clk_conf1_force_on;
volatile modem_syscon_mem_conf_reg_t mem_conf;
volatile modem_syscon_date_reg_t date;
} modem_syscon_dev_t;
extern modem_syscon_dev_t MODEM_SYSCON;
#ifndef __cplusplus
_Static_assert(sizeof(modem_syscon_dev_t) == 0x20, "Invalid size of modem_syscon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

9
components/soc/esp32h21/include/modem/reg_base.h Normal file
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@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define DR_REG_MODEM_SYSCON_BASE 0x600A5400
#define DR_REG_MODEM_LPCON_BASE 0x600AD000

4
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
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@ -47,6 +47,10 @@ config SOC_SPI_FLASH_SUPPORTED
bool bool
default y default y
config SOC_MODEM_CLOCK_SUPPORTED
bool
default y
config SOC_PAU_SUPPORTED config SOC_PAU_SUPPORTED
bool bool
default y default y

2
components/soc/esp32h21/include/soc/soc_caps.h
View File

@ -63,7 +63,7 @@
// #define SOC_WDT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11528 // #define SOC_WDT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11528
#define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32H21] IDF-11526 #define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32H21] IDF-11526
// #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11503 // #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11503
// #define SOC_MODEM_CLOCK_SUPPORTED 1 #define SOC_MODEM_CLOCK_SUPPORTED 1
// #define SOC_REG_I2C_SUPPORTED 1 //TODO: [ESP32H21] IDF-11550 // #define SOC_REG_I2C_SUPPORTED 1 //TODO: [ESP32H21] IDF-11550
// #define SOC_PHY_SUPPORTED 1 // #define SOC_PHY_SUPPORTED 1
// #define SOC_PCNT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11566 // #define SOC_PCNT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11566

2
components/soc/esp32h21/ld/esp32h21.peripherals.ld
View File

@ -45,6 +45,8 @@ PROVIDE ( PCR = 0x60096000 );
PROVIDE ( TEE = 0x60098000 ); PROVIDE ( TEE = 0x60098000 );
PROVIDE ( HP_APM = 0x60099000 ); PROVIDE ( HP_APM = 0x60099000 );
PROVIDE ( LP_APM0 = 0x60099800 ); PROVIDE ( LP_APM0 = 0x60099800 );
PROVIDE ( MODEM_SYSCON = 0x600A5400 );
PROVIDE ( MODEM_LPCON = 0x600AD000 );
PROVIDE ( PMU = 0x600B0000 ); PROVIDE ( PMU = 0x600B0000 );
PROVIDE ( LP_CLKRST = 0x600B0400 ); PROVIDE ( LP_CLKRST = 0x600B0400 );
PROVIDE ( LP_TIMER = 0x600B0C00 ); PROVIDE ( LP_TIMER = 0x600B0C00 );