From 1454be7d4e7313cef65e6dc521eadad19ea4e094 Mon Sep 17 00:00:00 2001 From: hongshuqing Date: Tue, 16 Jul 2024 15:09:33 +0800 Subject: [PATCH] feat(esp32c5): add rng support for bootloader and app --- .../src/bootloader_random_esp32c5.c | 91 ++++++++++++++++++- .../esp32c5/include/soc/Kconfig.soc_caps.in | 4 + .../soc/esp32c5/include/soc/apb_saradc_reg.h | 56 ++++++------ .../soc/esp32c5/include/soc/regi2c_saradc.h | 28 ++++++ components/soc/esp32c5/include/soc/soc_caps.h | 1 + components/soc/esp32c5/include/soc/wdev_reg.h | 2 +- 6 files changed, 149 insertions(+), 33 deletions(-) diff --git a/components/bootloader_support/src/bootloader_random_esp32c5.c b/components/bootloader_support/src/bootloader_random_esp32c5.c index cf0dcd6c19..c2b93bacfe 100644 --- a/components/bootloader_support/src/bootloader_random_esp32c5.c +++ b/components/bootloader_support/src/bootloader_random_esp32c5.c @@ -3,20 +3,103 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include "sdkconfig.h" +#include "bootloader_random.h" #include "soc/soc.h" #include "soc/pcr_reg.h" +#include "soc/apb_saradc_reg.h" #include "soc/pmu_reg.h" #include "hal/regi2c_ctrl.h" +#include "soc/lpperi_reg.h" +#include "soc/regi2c_saradc.h" #include "esp_log.h" +static const uint32_t SAR2_CHANNEL = 9; +static const uint32_t SAR1_CHANNEL = 7; +static const uint32_t PATTERN_BIT_WIDTH = 6; +static const uint32_t SAR1_ATTEN = 3; +static const uint32_t SAR2_ATTEN = 3; + void bootloader_random_enable(void) { -// TODO: [ESP32C5] IDF-8626 - ESP_EARLY_LOGW("bootloader_random", "bootloader_random_enable() has not been implemented on C5 yet"); + // pull SAR ADC out of reset + REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN); + REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN); + + // enable SAR ADC APB clock + REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN); + + // pull APB register out of reset + REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN); + REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN); + + // enable ADC_CTRL_CLK (SAR ADC function clock) + REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN); + + // select XTAL clock (40 MHz) source for ADC_CTRL_CLK + REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0); // 0: XTAL; 1: 80M(from bbpll); 2. FOSC + + // set the clock divider for ADC_CTRL_CLK to default value (in case it has been changed) + REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0); + + // some magic register poke from the digital team + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); + + // Config ADC circuit (Analog part) with I2C (HOST ID 0X69) and choose internal voltage as sampling source + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 1); + + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66); + REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, 0x08); + REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, 0x66); + + // create patterns and set them in pattern table + uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation + uint32_t pattern_two = (SAR1_CHANNEL << 2) | SAR1_ATTEN; // we want channel 7 with max attenuation + uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH; + REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table); + + // set pattern length (APB_SARADC_SARADC_SAR_PATT_LEN counts from 0) + REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 1); + + REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15); + + // set timer expiry (timer is ADC_CTRL_CLK) + REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200); + + // enable timer + REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN); + CLEAR_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN); } void bootloader_random_disable(void) { -// TODO: [ESP32C5] IDF-8626 - ESP_EARLY_LOGW("bootloader_random", "bootloader_random_disable() has not been implemented on C5 yet"); + // disable timer + REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN); + + // Write reset value of this register + REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF); + + // Revert ADC I2C configuration and initial voltage source setting + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, 0x60); + REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, 0x0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 0); + + // Revert PMU_RF_PWC_REG to it's initial value + CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); + + // disable ADC_CTRL_CLK (SAR ADC function clock) + REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000); + + // Set PCR_SARADC_CONF_REG to initial state + REG_WRITE(PCR_SARADC_CONF_REG, 0x5); } diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 181dc73c47..9943374c24 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -179,6 +179,10 @@ config SOC_ECDSA_SUPPORTED bool default y +config SOC_RNG_SUPPORTED + bool + default y + config SOC_MODEM_CLOCK_SUPPORTED bool default y diff --git a/components/soc/esp32c5/include/soc/apb_saradc_reg.h b/components/soc/esp32c5/include/soc/apb_saradc_reg.h index 4ae6b5b124..050cabc46d 100644 --- a/components/soc/esp32c5/include/soc/apb_saradc_reg.h +++ b/components/soc/esp32c5/include/soc/apb_saradc_reg.h @@ -14,7 +14,7 @@ extern "C" { /** APB_SARADC_CTRL_REG register * digital saradc configure register */ -#define APB_SARADC_CTRL_REG (DR_REG_APB_BASE + 0x0) +#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) /** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0; * select software enable saradc sample */ @@ -82,7 +82,7 @@ extern "C" { /** APB_SARADC_CTRL2_REG register * digital saradc configure register */ -#define APB_SARADC_CTRL2_REG (DR_REG_APB_BASE + 0x4) +#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) /** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0; * enable max meas num */ @@ -129,7 +129,7 @@ extern "C" { /** APB_SARADC_FILTER_CTRL1_REG register * digital saradc configure register */ -#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_BASE + 0x8) +#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8) /** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0; * Factor of saradc filter1 */ @@ -148,7 +148,7 @@ extern "C" { /** APB_SARADC_FSM_WAIT_REG register * digital saradc configure register */ -#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_BASE + 0xc) +#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xc) /** APB_SARADC_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8; * saradc_xpd_wait */ @@ -174,7 +174,7 @@ extern "C" { /** APB_SARADC_SAR1_STATUS_REG register * digital saradc configure register */ -#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_BASE + 0x10) +#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10) /** APB_SARADC_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 536870912; * saradc1 status about data and channel */ @@ -186,7 +186,7 @@ extern "C" { /** APB_SARADC_SAR2_STATUS_REG register * digital saradc configure register */ -#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_BASE + 0x14) +#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14) /** APB_SARADC_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 536870912; * saradc2 status about data and channel */ @@ -198,7 +198,7 @@ extern "C" { /** APB_SARADC_SAR_PATT_TAB1_REG register * digital saradc configure register */ -#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_BASE + 0x18) +#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18) /** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215; * item 0 ~ 3 for pattern table 1 (each item one byte) */ @@ -210,7 +210,7 @@ extern "C" { /** APB_SARADC_SAR_PATT_TAB2_REG register * digital saradc configure register */ -#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_BASE + 0x1c) +#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c) /** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215; * Item 4 ~ 7 for pattern table 1 (each item one byte) */ @@ -222,7 +222,7 @@ extern "C" { /** APB_SARADC_ONETIME_SAMPLE_REG register * digital saradc configure register */ -#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_BASE + 0x20) +#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20) /** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0; * configure onetime atten */ @@ -262,7 +262,7 @@ extern "C" { /** APB_SARADC_ARB_CTRL_REG register * digital saradc configure register */ -#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_BASE + 0x24) +#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24) /** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0; * adc2 arbiter force to enableapb controller */ @@ -323,7 +323,7 @@ extern "C" { /** APB_SARADC_FILTER_CTRL0_REG register * digital saradc configure register */ -#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_BASE + 0x28) +#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28) /** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13; * configure filter1 to adc channel */ @@ -349,7 +349,7 @@ extern "C" { /** APB_SARADC_SAR1DATA_STATUS_REG register * digital saradc configure register */ -#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_BASE + 0x2c) +#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c) /** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0; * saradc1 data */ @@ -361,7 +361,7 @@ extern "C" { /** APB_SARADC_SAR2DATA_STATUS_REG register * digital saradc configure register */ -#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_BASE + 0x30) +#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30) /** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0; * saradc2 data */ @@ -373,7 +373,7 @@ extern "C" { /** APB_SARADC_THRES0_CTRL_REG register * digital saradc configure register */ -#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_BASE + 0x34) +#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34) /** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13; * configure thres0 to adc channel */ @@ -399,7 +399,7 @@ extern "C" { /** APB_SARADC_THRES1_CTRL_REG register * digital saradc configure register */ -#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_BASE + 0x38) +#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38) /** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13; * configure thres1 to adc channel */ @@ -425,7 +425,7 @@ extern "C" { /** APB_SARADC_THRES_CTRL_REG register * digital saradc configure register */ -#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_BASE + 0x3c) +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c) /** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0; * enable thres to all channel */ @@ -451,7 +451,7 @@ extern "C" { /** APB_SARADC_INT_ENA_REG register * digital saradc int register */ -#define APB_SARADC_INT_ENA_REG (DR_REG_APB_BASE + 0x40) +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40) /** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0; * tsens low interrupt enable */ @@ -505,7 +505,7 @@ extern "C" { /** APB_SARADC_INT_RAW_REG register * digital saradc int register */ -#define APB_SARADC_INT_RAW_REG (DR_REG_APB_BASE + 0x44) +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44) /** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; * saradc tsens interrupt raw */ @@ -559,7 +559,7 @@ extern "C" { /** APB_SARADC_INT_ST_REG register * digital saradc int register */ -#define APB_SARADC_INT_ST_REG (DR_REG_APB_BASE + 0x48) +#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48) /** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0; * saradc tsens interrupt state */ @@ -613,7 +613,7 @@ extern "C" { /** APB_SARADC_INT_CLR_REG register * digital saradc int register */ -#define APB_SARADC_INT_CLR_REG (DR_REG_APB_BASE + 0x4c) +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c) /** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0; * saradc tsens interrupt clear */ @@ -667,7 +667,7 @@ extern "C" { /** APB_SARADC_DMA_CONF_REG register * digital saradc configure register */ -#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_BASE + 0x50) +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50) /** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255; * the dma_in_suc_eof gen when sample cnt = spi_eof_num */ @@ -693,7 +693,7 @@ extern "C" { /** APB_SARADC_CLKM_CONF_REG register * digital saradc configure register */ -#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_BASE + 0x54) +#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54) /** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; * Integral I2S clock divider value */ @@ -733,7 +733,7 @@ extern "C" { /** APB_SARADC_APB_TSENS_CTRL_REG register * digital tsens configure register */ -#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_BASE + 0x58) +#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58) /** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128; * temperature sensor data out */ @@ -766,7 +766,7 @@ extern "C" { /** APB_SARADC_TSENS_CTRL2_REG register * digital tsens configure register */ -#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_BASE + 0x5c) +#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c) /** APB_SARADC_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2; * the time that power up tsens need wait */ @@ -799,7 +799,7 @@ extern "C" { /** APB_SARADC_CALI_REG register * digital saradc configure register */ -#define APB_SARADC_CALI_REG (DR_REG_APB_BASE + 0x60) +#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60) /** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768; * saradc cali factor */ @@ -811,7 +811,7 @@ extern "C" { /** APB_TSENS_WAKE_REG register * digital tsens configure register */ -#define APB_TSENS_WAKE_REG (DR_REG_APB_BASE + 0x64) +#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64) /** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0; * reg_wakeup_th_low */ @@ -851,7 +851,7 @@ extern "C" { /** APB_TSENS_SAMPLE_REG register * digital tsens configure register */ -#define APB_TSENS_SAMPLE_REG (DR_REG_APB_BASE + 0x68) +#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68) /** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20; * HW sample rate */ @@ -870,7 +870,7 @@ extern "C" { /** APB_SARADC_CTRL_DATE_REG register * version */ -#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_BASE + 0x3fc) +#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc) /** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736; * version */ diff --git a/components/soc/esp32c5/include/soc/regi2c_saradc.h b/components/soc/esp32c5/include/soc/regi2c_saradc.h index a5f8fbf611..120d51fc20 100644 --- a/components/soc/esp32c5/include/soc/regi2c_saradc.h +++ b/components/soc/esp32c5/include/soc/regi2c_saradc.h @@ -53,3 +53,31 @@ #define I2C_SARADC_TSENS_DAC 0x6 #define I2C_SARADC_TSENS_DAC_MSB 0x3 #define I2C_SARADC_TSENS_DAC_LSB 0x0 + +#define ADC_SARADC_DTEST_RTC_ADDR 0x7 +#define ADC_SARADC_DTEST_RTC_ADDR_MSB 0x1 +#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0x0 + +#define ADC_SARADC_ENT_TSENS_ADDR 0x7 +#define ADC_SARADC_ENT_TSENS_ADDR_MSB 0x2 +#define ADC_SARADC_ENT_TSENS_ADDR_LSB 0x2 + +#define ADC_SARADC1_EN_TOUT_SAR1_BUS_ADDR 0x7 +#define ADC_SARADC1_EN_TOUT_SAR1_BUS_ADDR_MSB 0x4 +#define ADC_SARADC1_EN_TOUT_SAR1_BUS_ADDR_LSB 0x4 + +#define ADC_SARADC2_EN_TOUT_SAR2_BUS_ADDR 0x7 +#define ADC_SARADC2_EN_TOUT_SAR2_BUS_ADDR_MSB 0x5 +#define ADC_SARADC2_EN_TOUT_SAR2_BUS_ADDR_LSB 0x5 + +#define ADC_SARADC_ENT_PERIF_ADDR 0x7 +#define ADC_SARADC_ENT_PERIF_ADDR_MSB 0x6 +#define ADC_SARADC_ENT_PERIF_ADDR_LSB 0x6 + +#define ADC_SARADC1_EN_TOUT_ADDR 0x8 +#define ADC_SARADC1_EN_TOUT_ADDR_MSB 0x0 +#define ADC_SARADC1_EN_TOUT_ADDR_LSB 0x0 + +#define ADC_SARADC2_EN_TOUT_ADDR 0x8 +#define ADC_SARADC2_EN_TOUT_ADDR_MSB 0x2 +#define ADC_SARADC2_EN_TOUT_ADDR_LSB 0x2 diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index c608de7ac8..c5af67190c 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -71,6 +71,7 @@ #define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32C5] IDF-8715 // #define SOC_BITSCRAMBLER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8711 #define SOC_ECDSA_SUPPORTED 1 +#define SOC_RNG_SUPPORTED 1 // #define SOC_KEY_MANAGER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8621 // #define SOC_HUK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8617 // #define SOC_LIGHT_SLEEP_SUPPORTED 1 // TODO: [ESP32C5] IDF-8640 diff --git a/components/soc/esp32c5/include/soc/wdev_reg.h b/components/soc/esp32c5/include/soc/wdev_reg.h index d607f9cb19..ab12db2061 100644 --- a/components/soc/esp32c5/include/soc/wdev_reg.h +++ b/components/soc/esp32c5/include/soc/wdev_reg.h @@ -10,4 +10,4 @@ #include "soc/lpperi_reg.h" /* Hardware random number generator register */ -#define WDEV_RND_REG LPPERI_RNG_DATA_REG +#define WDEV_RND_REG LPPERI_RNG_DATA_SYNC_REG