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refactor(mspi): rename to mspi_ll.h

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This commit is contained in:
Armando 2024-12-27 18:17:25 +08:00
parent 3f6d1f6496
commit 14b5db0e87
38 changed files with 703 additions and 527 deletions
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2
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
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@ -28,7 +28,7 @@
#include "hal/mmu_ll.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "bootloader_flash_override.h"
void bootloader_flash_update_id()

2
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
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@ -24,7 +24,7 @@
#include "hal/mmu_ll.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
static const char *TAG __attribute__((unused)) = "boot.esp32c61";

3
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c
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@ -24,6 +24,7 @@
#include "hal/mmu_ll.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hal/mspi_ll.h"
#include "soc/pcr_reg.h"
void bootloader_flash_update_id()
@ -87,7 +88,7 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
static void IRAM_ATTR bootloader_flash_clock_init(void)
{
// At this moment, BBPLL should be enabled, safe to switch MSPI clock source to PLL_F64M (default clock src) to raise speed
REG_SET_FIELD(PCR_MSPI_CONF_REG, PCR_MSPI_CLK_SEL, 2);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M);
}
static void update_flash_config(const esp_image_header_t *bootloader_hdr)

3
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c
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@ -17,6 +17,7 @@
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hal/mspi_ll.h"
#include "soc/pcr_reg.h"
static const char *TAG = "boot.esp32h21";
@ -80,7 +81,7 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
static void IRAM_ATTR bootloader_flash_clock_init(void)
{
// At this moment, BBPLL should be enabled, safe to switch MSPI clock source to PLL_F64M (default clock src) to raise speed
REG_SET_FIELD(PCR_MSPI_CONF_REG, PCR_MSPI_CLK_SEL, 2);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M);
}
static void update_flash_config(const esp_image_header_t *bootloader_hdr)

2
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
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@ -19,7 +19,7 @@
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "esp_private/bootloader_flash_internal.h"

2
components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c
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@ -12,7 +12,7 @@
#include "esp_efuse_table.h"
#include "esp_log.h"
#include "hal/key_mgr_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "soc/soc_caps.h"
#include "sdkconfig.h"

2
components/bootloader_support/src/esp32p4/flash_encryption_secure_features.c
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@ -12,7 +12,7 @@
#include "esp_log.h"
#include "sdkconfig.h"
#include "hal/key_mgr_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
static __attribute__((unused)) const char *TAG = "flash_encrypt";

2
components/esp_hw_support/mspi_timing_tuning/mspi_timing_by_dqs.c
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@ -25,7 +25,7 @@
#include "esp_private/rtc_clk.h"
#include "esp_private/periph_ctrl.h"
#include "hal/psram_ctrlr_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#define AP_HEX_PSRAM_SYNC_READ 0x0000
#define AP_HEX_PSRAM_SYNC_WRITE 0x8080

2
components/esp_hw_support/mspi_timing_tuning/mspi_timing_by_dqs.h
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@ -16,7 +16,7 @@
#if SOC_MEMSPI_TIMING_TUNING_BY_DQS
#include "mspi_timing_types.h"
#include "mspi_timing_tuning_configs.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#endif
#ifdef __cplusplus

2
components/esp_hw_support/mspi_timing_tuning/mspi_timing_by_flash_delay.c
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@ -22,7 +22,7 @@
#include "mspi_timing_by_flash_delay.h"
#include "mspi_timing_tuning_configs.h"
#include "esp_private/mspi_timing_config.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "rom/spi_flash.h"
const static char *TAG = "Flash Delay";

2
components/esp_hw_support/mspi_timing_tuning/mspi_timing_by_mspi_delay.c
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@ -19,7 +19,7 @@
#include "esp_types.h"
#include "esp_log.h"
#include "soc/rtc.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "hal/clk_tree_ll.h"
#include "hal/regi2c_ctrl_ll.h"
#include "esp_private/mspi_timing_config.h"

2
components/esp_hw_support/mspi_timing_tuning/mspi_timing_tuning.c
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@ -16,7 +16,7 @@
#include "hal/spi_flash_hal.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "esp_private/mspi_timing_tuning.h"
#include "esp_private/mspi_timing_config.h"
#include "mspi_timing_by_mspi_delay.h"

2
components/esp_hw_support/mspi_timing_tuning/mspi_timing_types.h
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@ -14,7 +14,7 @@
#include <stdint.h>
#include "soc/soc_caps.h"
#if SOC_MEMSPI_TIMING_TUNING_BY_DQS || SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY || SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "mspi_timing_tuning_configs.h"
#endif

2
components/esp_hw_support/mspi_timing_tuning/port/esp32p4/mspi_timing_config.c
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@ -15,7 +15,7 @@
#include "esp_private/mspi_timing_config.h"
#include "mspi_timing_tuning_configs.h"
#include "hal/psram_ctrlr_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "soc/hp_sys_clkrst_struct.h"
const static char *TAG = "MSPI Timing";

2
components/esp_hw_support/mspi_timing_tuning/port/esp32s3/mspi_timing_config.c
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@ -13,7 +13,7 @@
#include "soc/soc_caps.h"
#include "esp_private/mspi_timing_config.h"
#include "mspi_timing_tuning_configs.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#define FLASH_LOW_SPEED_CORE_CLOCK_MHZ MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT
#define FLASH_HIGH_SPEED_CORE_CLOCK_MHZ MSPI_TIMING_CORE_CLOCK_MHZ

2
components/esp_hw_support/sleep_modes.c
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@ -65,7 +65,7 @@
#include "hal/touch_sensor_hal.h"
#include "hal/touch_sens_hal.h"
#endif
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "sdkconfig.h"
#include "esp_rom_uart.h"

2
components/esp_pm/pm_impl.c
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@ -27,7 +27,7 @@
#include "hal/clk_tree_ll.h"
#include "hal/uart_ll.h"
#include "hal/uart_types.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "driver/gpio.h"

2
components/esp_psram/device/esp_psram_impl_ap_hex.c
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@ -12,7 +12,7 @@
#include "esp_private/mspi_timing_tuning.h"
#include "../esp_psram_impl.h"
#include "hal/psram_ctrlr_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "clk_ctrl_os.h"
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section

14
components/esp_system/port/soc/esp32s3/cache_err_int.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -227,15 +227,15 @@ void esp_cache_err_int_init(void)
.spi1_w = 1,
};
mspi_ll_set_flash_protection_addr(0, 0x0);
mspi_ll_set_flash_protection_size(0, max_flash_size);
mspi_ll_set_flash_protection_addr(0, 0, 0x0);
mspi_ll_set_flash_protection_size(0, 0, max_flash_size);
// Set other flash_aceN_size to 0 to disable them.
mspi_ll_set_flash_protection_size(1, 0);
mspi_ll_set_flash_protection_size(2, 0);
mspi_ll_set_flash_protection_size(3, 0);
mspi_ll_set_flash_protection_size(0, 1, 0);
mspi_ll_set_flash_protection_size(0, 2, 0);
mspi_ll_set_flash_protection_size(0, 3, 0);
mspi_ll_set_flash_protection_access(0, ctrl);
mspi_ll_set_flash_protection_access(0, 0, ctrl);
}

19
components/hal/esp32/include/hal/mspi_ll.h Normal file
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@ -0,0 +1,19 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* Background
*
* This file is for the MSPI related, but not Flash driver related registers, these registers:
* - may influence both Flash and PSRAM
* - not related or directly related to Flash controller driver
*
* Some hints for naming convention:
* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
* - For others, the LL should start with `mspi_ll_`
*/
//For compatibility

7
components/hal/esp32/include/hal/mspi_timing_tuning_ll.h
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@ -1,7 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
//For compatibility

19
components/hal/esp32c2/include/hal/mspi_ll.h Normal file
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@ -0,0 +1,19 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* Background
*
* This file is for the MSPI related, but not Flash driver related registers, these registers:
* - may influence both Flash and PSRAM
* - not related or directly related to Flash controller driver
*
* Some hints for naming convention:
* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
* - For others, the LL should start with `mspi_ll_`
*/
//For compatibility

7
components/hal/esp32c2/include/hal/mspi_timing_tuning_ll.h
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@ -1,7 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
//For compatibility

19
components/hal/esp32c3/include/hal/mspi_ll.h Normal file
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@ -0,0 +1,19 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* Background
*
* This file is for the MSPI related, but not Flash driver related registers, these registers:
* - may influence both Flash and PSRAM
* - not related or directly related to Flash controller driver
*
* Some hints for naming convention:
* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
* - For others, the LL should start with `mspi_ll_`
*/
//For compatibility

7
components/hal/esp32c3/include/hal/mspi_timing_tuning_ll.h
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@ -1,7 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
//For compatibility

14
components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h → components/hal/esp32c5/include/hal/mspi_ll.h
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@ -1,9 +1,21 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* Background
*
* This file is for the MSPI related, but not Flash driver related registers, these registers:
* - may influence both Flash and PSRAM
* - not related or directly related to Flash controller driver
*
* Some hints for naming convention:
* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
* - For others, the LL should start with `mspi_ll_`
*/
#pragma once
#include <stdint.h>

19
components/hal/esp32c6/include/hal/mspi_ll.h Normal file
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@ -0,0 +1,19 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* Background
*
* This file is for the MSPI related, but not Flash driver related registers, these registers:
* - may influence both Flash and PSRAM
* - not related or directly related to Flash controller driver
*
* Some hints for naming convention:
* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
* - For others, the LL should start with `mspi_ll_`
*/
//For compatibility

7
components/hal/esp32c6/include/hal/mspi_timing_tuning_ll.h
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@ -1,7 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
//For compatibility

14
components/hal/esp32c61/include/hal/mspi_timing_tuning_ll.h → components/hal/esp32c61/include/hal/mspi_ll.h
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@ -1,9 +1,21 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* Background
*
* This file is for the MSPI related, but not Flash driver related registers, these registers:
* - may influence both Flash and PSRAM
* - not related or directly related to Flash controller driver
*
* Some hints for naming convention:
* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
* - For others, the LL should start with `mspi_ll_`
*/
#pragma once
#include <stdint.h>

14
components/hal/esp32h2/include/hal/mspi_timing_tuning_ll.h → components/hal/esp32h2/include/hal/mspi_ll.h
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@ -1,9 +1,21 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* Background
*
* This file is for the MSPI related, but not Flash driver related registers, these registers:
* - may influence both Flash and PSRAM
* - not related or directly related to Flash controller driver
*
* Some hints for naming convention:
* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
* - For others, the LL should start with `mspi_ll_`
*/
#pragma once
#include <stdint.h>

67
components/hal/esp32h21/include/hal/mspi_ll.h Normal file
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@ -0,0 +1,67 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* Background
*
* This file is for the MSPI related, but not Flash driver related registers, these registers:
* - may influence both Flash and PSRAM
* - not related or directly related to Flash controller driver
*
* Some hints for naming convention:
* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
* - For others, the LL should start with `mspi_ll_`
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
//Timing tuning not applied, and flash has its own clock source. Can change flash clock source
#define MSPI_TIMING_LL_FLASH_CLK_SRC_CHANGEABLE 1
/************************** MSPI pll clock configurations **************************/
/*
* @brief Select FLASH clock source
*
* @param mspi_id mspi_id
* @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t`
*/
__attribute__((always_inline))
static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
{
HAL_ASSERT(mspi_id == 0);
switch (clk_src) {
case FLASH_CLK_SRC_XTAL:
PCR.mspi_conf.mspi_clk_sel = 0;
break;
case FLASH_CLK_SRC_RC_FAST:
PCR.mspi_conf.mspi_clk_sel = 1;
break;
case FLASH_CLK_SRC_PLL_F64M:
PCR.mspi_conf.mspi_clk_sel = 2;
break;
case FLASH_CLK_SRC_PLL_F48M:
PCR.mspi_conf.mspi_clk_sel = 3;
break;
default:
HAL_ASSERT(false);
}
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32h21/include/hal/mspi_timing_tuning_ll.h
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@ -1,7 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
//TODO: [ESP32H21] IDF-11918

12
components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h → components/hal/esp32p4/include/hal/mspi_ll.h
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@ -10,6 +10,18 @@
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
/**
* Background
*
* This file is for the MSPI related, but not Flash driver related registers, these registers:
* - may influence both Flash and PSRAM
* - not related or directly related to Flash controller driver
*
* Some hints for naming convention:
* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
* - For others, the LL should start with `mspi_ll_`
*/
#pragma once
#include <stdint.h>

19
components/hal/esp32s2/include/hal/mspi_ll.h Normal file
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@ -0,0 +1,19 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* Background
*
* This file is for the MSPI related, but not Flash driver related registers, these registers:
* - may influence both Flash and PSRAM
* - not related or directly related to Flash controller driver
*
* Some hints for naming convention:
* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
* - For others, the LL should start with `mspi_ll_`
*/
//For compatibility

7
components/hal/esp32s2/include/hal/mspi_timing_tuning_ll.h
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@ -1,7 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
//For compatibility

451
components/hal/esp32s3/include/hal/mspi_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,17 +10,453 @@
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
/**
* Background
*
* This file is for the MSPI related, but not Flash driver related registers, these registers:
* - may influence both Flash and PSRAM
* - not related or directly related to Flash controller driver
*
* Some hints for naming convention:
* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
* - For others, the LL should start with `mspi_ll_`
*/
#pragma once
#include <stdint.h>
#include <sys/param.h>
#include <stdbool.h>
#include "soc/syscon_struct.h"
#include "esp_bit_defs.h"
#include "hal/assert.h"
#include "soc/soc.h"
#include "soc/spi_mem_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/syscon_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ARRAY_SIZE(arr) (sizeof((arr))/sizeof(*(arr)))
#define MSPI_TIMING_LL_FLASH_OCT_MASK (SPI_MEM_FCMD_OCT | SPI_MEM_FADDR_OCT | SPI_MEM_FDIN_OCT | SPI_MEM_FDOUT_OCT)
#define MSPI_TIMING_LL_FLASH_QUAD_MASK (SPI_MEM_FASTRD_MODE | SPI_MEM_FREAD_DUAL | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_QIO)
#define MSPI_TIMING_LL_FLASH_QIO_MODE_MASK (SPI_MEM_FREAD_QIO | SPI_MEM_FASTRD_MODE)
#define MSPI_TIMING_LL_FLASH_QUAD_MODE_MASK (SPI_MEM_FREAD_QUAD | SPI_MEM_FASTRD_MODE)
#define MSPI_TIMING_LL_FLASH_DIO_MODE_MASK (SPI_MEM_FREAD_DIO | SPI_MEM_FASTRD_MODE)
#define MSPI_TIMING_LL_FLASH_DUAL_MODE_MASK (SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE)
#define MSPI_TIMING_LL_FLASH_FAST_MODE_MASK (SPI_MEM_FASTRD_MODE)
#define MSPI_TIMING_LL_FLASH_SLOW_MODE_MASK 0
#define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT 80
#define MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED 1
typedef enum {
MSPI_TIMING_LL_FLASH_OPI_MODE = BIT(0),
MSPI_TIMING_LL_FLASH_QIO_MODE = BIT(1),
MSPI_TIMING_LL_FLASH_QUAD_MODE = BIT(2),
MSPI_TIMING_LL_FLASH_DIO_MODE = BIT(3),
MSPI_TIMING_LL_FLASH_DUAL_MODE = BIT(4),
MSPI_TIMING_LL_FLASH_FAST_MODE = BIT(5),
MSPI_TIMING_LL_FLASH_SLOW_MODE = BIT(6),
} mspi_timing_ll_flash_mode_t;
/**
* Set all MSPI pin drive strength
*
* @param spi_num SPI0 / SPI1
* @param val Pin drive strength
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_all_pin_drive(uint8_t spi_num, uint32_t val)
{
SET_PERI_REG_MASK(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
REG_SET_FIELD(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, val);
REG_SET_FIELD(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV, val);
uint32_t regs[] = {IO_MUX_GPIO27_REG, IO_MUX_GPIO28_REG,
IO_MUX_GPIO31_REG, IO_MUX_GPIO32_REG,
IO_MUX_GPIO33_REG, IO_MUX_GPIO34_REG,
IO_MUX_GPIO35_REG, IO_MUX_GPIO36_REG,
IO_MUX_GPIO37_REG};
for (int i = 0; i < ARRAY_SIZE(regs); i++) {
PIN_SET_DRV(regs[i], val);
}
}
/**
* Set all MSPI Flash clock pin drive strength
*
* @param spi_num SPI0 / SPI1
* @param val Pin drive strength
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_clock_pin_drive(uint8_t spi_num, uint32_t val)
{
bool clk_pin_drive_control = GET_PERI_REG_MASK(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
//You should never call this function, while `mspi_timing_ll_set_all_pin_drive()` isn't called
HAL_ASSERT(clk_pin_drive_control);
REG_SET_FIELD(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV, val);
}
/**
* Set all MSPI PSRAM clock pin drive strength
*
* @param spi_num SPI0 / SPI1
* @param val Pin drive strength
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_clock_pin_drive(uint8_t spi_num, uint32_t val)
{
bool clk_pin_drive_control = GET_PERI_REG_MASK(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
//You should never call this function, while `mspi_timing_ll_set_all_pin_drive()` isn't called
HAL_ASSERT(clk_pin_drive_control);
REG_SET_FIELD(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, val);
}
/**
* Enable Flash timing adjust clock
*
* @param spi_num SPI0 / SPI1
*/
__attribute__((always_inline))
static inline void mspi_timinng_ll_enable_flash_timing_adjust_clk(uint8_t spi_num)
{
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CLK_ENA);
}
/**
* Enable PSRAM timing adjust clock
*
* @param spi_num SPI0 / SPI1
*/
__attribute__((always_inline))
static inline void mspi_timinng_ll_enable_psram_timing_adjust_clk(uint8_t spi_num)
{
REG_SET_BIT(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CLK_ENA);
}
/**
* Enable/Disable Flash variable dummy
*
* @param spi_num SPI0 / SPI1
* @param enable Enable / Disable
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_enable_flash_variable_dummy(uint8_t spi_num, bool enable)
{
REG_SET_FIELD(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY, enable);
}
/**
* Set MSPI core clock
*
* @param spi_num SPI0 / SPI1
* @param core_clk_mhz core clock mhz
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_core_clock(uint8_t spi_num, uint32_t core_clk_mhz)
{
uint32_t reg_val = 0;
switch (core_clk_mhz) {
case 80:
reg_val = 0;
break;
case 120:
reg_val = 1;
break;
case 160:
reg_val = 2;
break;
case 240:
reg_val = 3;
break;
default:
HAL_ASSERT(false);
}
REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(spi_num), SPI_MEM_CORE_CLK_SEL, reg_val);
}
/**
* Set MSPI Flash clock
*
* @param spi_num SPI0 / SPI1
* @param freqdiv Divider value
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_clock(uint8_t spi_num, uint32_t freqdiv)
{
if (freqdiv == 1) {
WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), SPI_MEM_CLK_EQU_SYSCLK);
} else {
uint32_t freqbits = (((freqdiv - 1) << SPI_MEM_CLKCNT_N_S)) | (((freqdiv / 2 - 1) << SPI_MEM_CLKCNT_H_S)) | ((freqdiv - 1) << SPI_MEM_CLKCNT_L_S);
WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), freqbits);
}
}
/**
* Set MSPI PSRAM clock
*
* @param spi_num SPI0 / SPI1
* @param freqdiv Divider value
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_clock(uint8_t spi_num, uint32_t freqdiv)
{
if (freqdiv == 1) {
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
} else {
uint32_t freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S);
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
}
}
/**
* Set MSPI Flash din mode
*
* @param spi_num SPI0 / SPI1
* @param din_mode Din mode value
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_din_mode(uint8_t spi_num, uint8_t din_mode)
{
uint32_t reg_val = (REG_READ(SPI_MEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_DIN0_MODE_M | SPI_MEM_DIN1_MODE_M | SPI_MEM_DIN2_MODE_M | SPI_MEM_DIN3_MODE_M | SPI_MEM_DIN4_MODE_M | SPI_MEM_DIN5_MODE_M | SPI_MEM_DIN6_MODE_M | SPI_MEM_DIN7_MODE_M | SPI_MEM_DINS_MODE_M)))
| (din_mode << SPI_MEM_DIN0_MODE_S) | (din_mode << SPI_MEM_DIN1_MODE_S) | (din_mode << SPI_MEM_DIN2_MODE_S) | (din_mode << SPI_MEM_DIN3_MODE_S)
| (din_mode << SPI_MEM_DIN4_MODE_S) | (din_mode << SPI_MEM_DIN5_MODE_S) | (din_mode << SPI_MEM_DIN6_MODE_S) | (din_mode << SPI_MEM_DIN7_MODE_S) | (din_mode << SPI_MEM_DINS_MODE_S);
REG_WRITE(SPI_MEM_DIN_MODE_REG(spi_num), reg_val);
}
/**
* Set MSPI Flash din num
*
* @param spi_num SPI0 / SPI1
* @param din_num Din num value
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_din_num(uint8_t spi_num, uint8_t din_num)
{
uint32_t reg_val = (REG_READ(SPI_MEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_DIN0_NUM_M | SPI_MEM_DIN1_NUM_M | SPI_MEM_DIN2_NUM_M | SPI_MEM_DIN3_NUM_M | SPI_MEM_DIN4_NUM_M | SPI_MEM_DIN5_NUM_M | SPI_MEM_DIN6_NUM_M | SPI_MEM_DIN7_NUM_M | SPI_MEM_DINS_NUM_M)))
| (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
| (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
REG_WRITE(SPI_MEM_DIN_NUM_REG(spi_num), reg_val);
}
/**
* Get MSPI Flash mode
*
* @param spi_num SPI0 / SPI1
*
* @return Flash mode
*/
__attribute__((always_inline))
static inline mspi_timing_ll_flash_mode_t mspi_timing_ll_get_flash_mode(uint8_t spi_num)
{
uint32_t ctrl_reg = READ_PERI_REG(SPI_MEM_CTRL_REG(0));
if (ctrl_reg & MSPI_TIMING_LL_FLASH_OCT_MASK) {
return MSPI_TIMING_LL_FLASH_OPI_MODE;
}
switch (ctrl_reg & MSPI_TIMING_LL_FLASH_QUAD_MASK) {
case MSPI_TIMING_LL_FLASH_QIO_MODE_MASK:
return MSPI_TIMING_LL_FLASH_QIO_MODE;
case MSPI_TIMING_LL_FLASH_QUAD_MODE_MASK:
return MSPI_TIMING_LL_FLASH_QUAD_MODE;
case MSPI_TIMING_LL_FLASH_DIO_MODE_MASK:
return MSPI_TIMING_LL_FLASH_DIO_MODE;
case MSPI_TIMING_LL_FLASH_DUAL_MODE_MASK:
return MSPI_TIMING_LL_FLASH_DUAL_MODE;
case MSPI_TIMING_LL_FLASH_FAST_MODE_MASK:
return MSPI_TIMING_LL_FLASH_FAST_MODE;
case MSPI_TIMING_LL_FLASH_SLOW_MODE_MASK:
return MSPI_TIMING_LL_FLASH_SLOW_MODE;
default:
HAL_ASSERT(false);
return (mspi_timing_ll_flash_mode_t)0;
}
}
/**
* Set MSPI Octal Flash extra dummy
*
* @param spi_num SPI0 / SPI1
* @param extra_dummy Extra dummy
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_octal_flash_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
{
if (extra_dummy > 0) {
SET_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
} else {
CLEAR_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, 0,
SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
}
}
/**
* Set MSPI Quad Flash dummy
*
* @param spi_num SPI0 / SPI1
* @param dummy dummy
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_quad_flash_dummy(uint8_t spi_num, uint8_t dummy)
{
//HW workaround: Use normal dummy register to set extra dummy, the calibration dedicated extra dummy register doesn't work for quad mode
SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_DUMMY);
SET_PERI_REG_BITS(SPI_MEM_USER1_REG(spi_num), SPI_MEM_USR_DUMMY_CYCLELEN_V, dummy, SPI_MEM_USR_DUMMY_CYCLELEN_S);
}
/**
* Set MSPI PSRAM din mode
*
* @param spi_num SPI0 / SPI1
* @param din_mode Din mode value
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_din_mode(uint8_t spi_num, uint8_t din_mode)
{
uint32_t reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_MODE_M | SPI_MEM_SPI_SMEM_DIN1_MODE_M | SPI_MEM_SPI_SMEM_DIN2_MODE_M | SPI_MEM_SPI_SMEM_DIN3_MODE_M | SPI_MEM_SPI_SMEM_DIN4_MODE_M | SPI_MEM_SPI_SMEM_DIN5_MODE_M | SPI_MEM_SPI_SMEM_DIN6_MODE_M | SPI_MEM_SPI_SMEM_DIN7_MODE_M | SPI_MEM_SPI_SMEM_DINS_MODE_M)))
| (din_mode << SPI_MEM_SPI_SMEM_DIN0_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN1_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN2_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN3_MODE_S)
| (din_mode << SPI_MEM_SPI_SMEM_DIN4_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN5_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN6_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN7_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DINS_MODE_S);
REG_WRITE(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num), reg_val);
}
/**
* Set MSPI PSRAM din num
*
* @param spi_num SPI0 / SPI1
* @param din_num Din num value
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_din_num(uint8_t spi_num, uint8_t din_num)
{
uint32_t reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_NUM_M | SPI_MEM_SPI_SMEM_DIN1_NUM_M | SPI_MEM_SPI_SMEM_DIN2_NUM_M | SPI_MEM_SPI_SMEM_DIN3_NUM_M | SPI_MEM_SPI_SMEM_DIN4_NUM_M | SPI_MEM_SPI_SMEM_DIN5_NUM_M | SPI_MEM_SPI_SMEM_DIN6_NUM_M | SPI_MEM_SPI_SMEM_DIN7_NUM_M | SPI_MEM_SPI_SMEM_DINS_NUM_M)))
| (din_num << SPI_MEM_SPI_SMEM_DIN0_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN1_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN2_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN3_NUM_S)
| (din_num << SPI_MEM_SPI_SMEM_DIN4_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN5_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN6_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN7_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DINS_NUM_S);
REG_WRITE(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num), reg_val);
}
/**
* Set MSPI Octal PSRAM extra dummy
*
* @param spi_num SPI0 / SPI1
* @param extra_dummy Extra dummy
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_octal_psram_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
{
if (extra_dummy > 0) {
SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
} else {
CLEAR_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, 0,
SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
}
}
/**
* Set MSPI Octal PSRAM dummy
*
* @param spi_num SPI0 / SPI1
* @param dummy dummy
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_quad_psram_dummy(uint8_t spi_num, uint8_t dummy)
{
//HW workaround: Use normal dummy register to set extra dummy, the calibration dedicated extra dummy register doesn't work for quad mode
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_USR_RD_SRAM_DUMMY_M);
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, dummy, SPI_MEM_SRAM_RDUMMY_CYCLELEN_S);
}
/**
* Clear MSPI hw fifo
*
* @param spi_num SPI0 / SPI1
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_clear_fifo(uint8_t spi_num)
{
for (int i = 0; i < 16; i++) {
REG_WRITE(SPI_MEM_W0_REG(spi_num) + i*4, 0);
}
}
/**
* Get if cs setup is enabled or not
*
* @param spi_num SPI0 / SPI1
*
* @return
* true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool mspi_timing_ll_is_cs_setup_enabled(uint8_t spi_num)
{
return REG_GET_BIT(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_SETUP);
}
/**
* Get cs setup val
*
* @param spi_num SPI0 / SPI1
*
* @return
* cs setup reg val
*/
static inline uint32_t mspi_timing_ll_get_cs_setup_val(uint8_t spi_num)
{
return REG_GET_FIELD(SPI_MEM_CTRL2_REG(spi_num), SPI_MEM_CS_SETUP_TIME);
}
/**
* Get if cs hold is enabled or not
*
* @param spi_num SPI0 / SPI1
*
* @return
* true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool mspi_timing_ll_is_cs_hold_enabled(uint8_t spi_num)
{
return REG_GET_BIT(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_HOLD);
}
/**
* Get cs hold val
*
* @param spi_num SPI0 / SPI1
*
* @return
* cs hold reg val
*/
static inline uint32_t mspi_timing_ll_get_cs_hold_val(uint8_t spi_num)
{
return REG_GET_FIELD(SPI_MEM_CTRL2_REG(spi_num), SPI_MEM_CS_HOLD_TIME);
}
/**
* Get clock reg val
*
* @param spi_num SPI0 / SPI1
*
* @return
* clock reg val
*/
__attribute__((always_inline))
static inline uint32_t mspi_timing_ll_get_clock_reg(uint8_t spi_num)
{
return READ_PERI_REG(SPI_MEM_CLOCK_REG(spi_num));
}
/**
* flash access control config struct
*/
@ -41,12 +477,13 @@ typedef union {
/**
* @brief Set PMS flash protection start address
*
* @param spi_num SPI0 / SPI1
* @param region PMS region id (0~3)
* @param address Starting address
*
*/
__attribute__((always_inline))
static inline void mspi_ll_set_flash_protection_addr(uint32_t region, uint32_t address)
static inline void mspi_ll_set_flash_protection_addr(uint8_t spi_num, uint32_t region, uint32_t address)
{
switch(region){
case 0:
@ -69,12 +506,13 @@ static inline void mspi_ll_set_flash_protection_addr(uint32_t region, uint32_t a
/**
* @brief Set PMS flash protection size
*
* @param spi_num SPI0 / SPI1
* @param region PMS region id (0~3)
* @param size Size, in number of 64kB pages
*
*/
__attribute__((always_inline))
static inline void mspi_ll_set_flash_protection_size(uint32_t region, uint32_t size)
static inline void mspi_ll_set_flash_protection_size(uint8_t spi_num, uint32_t region, uint32_t size)
{
switch(region){
case 0:
@ -97,12 +535,13 @@ static inline void mspi_ll_set_flash_protection_size(uint32_t region, uint32_t s
/**
* @brief Set PMS flash protection access ctrl bits
*
* @param spi_num SPI0 / SPI1
* @param region PMS region id (0~3)
* @param address ctrl bits, RWX per mode
*
*/
__attribute__((always_inline))
static inline void mspi_ll_set_flash_protection_access(uint32_t region, mspi_ll_flash_ace_ctrl_t ctrl)
static inline void mspi_ll_set_flash_protection_access(uint8_t spi_num, uint32_t region, mspi_ll_flash_ace_ctrl_t ctrl)
{
switch(region){
case 0:

450
components/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h
View File

@ -1,450 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include <sys/param.h>
#include "esp_bit_defs.h"
#include "hal/assert.h"
#include "soc/soc.h"
#include "soc/spi_mem_reg.h"
#include "soc/io_mux_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ARRAY_SIZE(arr) (sizeof((arr))/sizeof(*(arr)))
#define MSPI_TIMING_LL_FLASH_OCT_MASK (SPI_MEM_FCMD_OCT | SPI_MEM_FADDR_OCT | SPI_MEM_FDIN_OCT | SPI_MEM_FDOUT_OCT)
#define MSPI_TIMING_LL_FLASH_QUAD_MASK (SPI_MEM_FASTRD_MODE | SPI_MEM_FREAD_DUAL | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_QIO)
#define MSPI_TIMING_LL_FLASH_QIO_MODE_MASK (SPI_MEM_FREAD_QIO | SPI_MEM_FASTRD_MODE)
#define MSPI_TIMING_LL_FLASH_QUAD_MODE_MASK (SPI_MEM_FREAD_QUAD | SPI_MEM_FASTRD_MODE)
#define MSPI_TIMING_LL_FLASH_DIO_MODE_MASK (SPI_MEM_FREAD_DIO | SPI_MEM_FASTRD_MODE)
#define MSPI_TIMING_LL_FLASH_DUAL_MODE_MASK (SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE)
#define MSPI_TIMING_LL_FLASH_FAST_MODE_MASK (SPI_MEM_FASTRD_MODE)
#define MSPI_TIMING_LL_FLASH_SLOW_MODE_MASK 0
#define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT 80
#define MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED 1
typedef enum {
MSPI_TIMING_LL_FLASH_OPI_MODE = BIT(0),
MSPI_TIMING_LL_FLASH_QIO_MODE = BIT(1),
MSPI_TIMING_LL_FLASH_QUAD_MODE = BIT(2),
MSPI_TIMING_LL_FLASH_DIO_MODE = BIT(3),
MSPI_TIMING_LL_FLASH_DUAL_MODE = BIT(4),
MSPI_TIMING_LL_FLASH_FAST_MODE = BIT(5),
MSPI_TIMING_LL_FLASH_SLOW_MODE = BIT(6),
} mspi_timing_ll_flash_mode_t;
/**
* Set all MSPI pin drive strength
*
* @param spi_num SPI0 / SPI1
* @param val Pin drive strength
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_all_pin_drive(uint8_t spi_num, uint32_t val)
{
SET_PERI_REG_MASK(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
REG_SET_FIELD(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, val);
REG_SET_FIELD(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV, val);
uint32_t regs[] = {IO_MUX_GPIO27_REG, IO_MUX_GPIO28_REG,
IO_MUX_GPIO31_REG, IO_MUX_GPIO32_REG,
IO_MUX_GPIO33_REG, IO_MUX_GPIO34_REG,
IO_MUX_GPIO35_REG, IO_MUX_GPIO36_REG,
IO_MUX_GPIO37_REG};
for (int i = 0; i < ARRAY_SIZE(regs); i++) {
PIN_SET_DRV(regs[i], val);
}
}
/**
* Set all MSPI Flash clock pin drive strength
*
* @param spi_num SPI0 / SPI1
* @param val Pin drive strength
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_clock_pin_drive(uint8_t spi_num, uint32_t val)
{
bool clk_pin_drive_control = GET_PERI_REG_MASK(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
//You should never call this function, while `mspi_timing_ll_set_all_pin_drive()` isn't called
HAL_ASSERT(clk_pin_drive_control);
REG_SET_FIELD(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV, val);
}
/**
* Set all MSPI PSRAM clock pin drive strength
*
* @param spi_num SPI0 / SPI1
* @param val Pin drive strength
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_clock_pin_drive(uint8_t spi_num, uint32_t val)
{
bool clk_pin_drive_control = GET_PERI_REG_MASK(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
//You should never call this function, while `mspi_timing_ll_set_all_pin_drive()` isn't called
HAL_ASSERT(clk_pin_drive_control);
REG_SET_FIELD(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, val);
}
/**
* Enable Flash timing adjust clock
*
* @param spi_num SPI0 / SPI1
*/
__attribute__((always_inline))
static inline void mspi_timinng_ll_enable_flash_timing_adjust_clk(uint8_t spi_num)
{
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CLK_ENA);
}
/**
* Enable PSRAM timing adjust clock
*
* @param spi_num SPI0 / SPI1
*/
__attribute__((always_inline))
static inline void mspi_timinng_ll_enable_psram_timing_adjust_clk(uint8_t spi_num)
{
REG_SET_BIT(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CLK_ENA);
}
/**
* Enable/Disable Flash variable dummy
*
* @param spi_num SPI0 / SPI1
* @param enable Enable / Disable
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_enable_flash_variable_dummy(uint8_t spi_num, bool enable)
{
REG_SET_FIELD(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY, enable);
}
/**
* Set MSPI core clock
*
* @param spi_num SPI0 / SPI1
* @param core_clk_mhz core clock mhz
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_core_clock(uint8_t spi_num, uint32_t core_clk_mhz)
{
uint32_t reg_val = 0;
switch (core_clk_mhz) {
case 80:
reg_val = 0;
break;
case 120:
reg_val = 1;
break;
case 160:
reg_val = 2;
break;
case 240:
reg_val = 3;
break;
default:
HAL_ASSERT(false);
}
REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(spi_num), SPI_MEM_CORE_CLK_SEL, reg_val);
}
/**
* Set MSPI Flash clock
*
* @param spi_num SPI0 / SPI1
* @param freqdiv Divider value
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_clock(uint8_t spi_num, uint32_t freqdiv)
{
if (freqdiv == 1) {
WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), SPI_MEM_CLK_EQU_SYSCLK);
} else {
uint32_t freqbits = (((freqdiv - 1) << SPI_MEM_CLKCNT_N_S)) | (((freqdiv / 2 - 1) << SPI_MEM_CLKCNT_H_S)) | ((freqdiv - 1) << SPI_MEM_CLKCNT_L_S);
WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), freqbits);
}
}
/**
* Set MSPI PSRAM clock
*
* @param spi_num SPI0 / SPI1
* @param freqdiv Divider value
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_clock(uint8_t spi_num, uint32_t freqdiv)
{
if (freqdiv == 1) {
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
} else {
uint32_t freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S);
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
}
}
/**
* Set MSPI Flash din mode
*
* @param spi_num SPI0 / SPI1
* @param din_mode Din mode value
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_din_mode(uint8_t spi_num, uint8_t din_mode)
{
uint32_t reg_val = (REG_READ(SPI_MEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_DIN0_MODE_M | SPI_MEM_DIN1_MODE_M | SPI_MEM_DIN2_MODE_M | SPI_MEM_DIN3_MODE_M | SPI_MEM_DIN4_MODE_M | SPI_MEM_DIN5_MODE_M | SPI_MEM_DIN6_MODE_M | SPI_MEM_DIN7_MODE_M | SPI_MEM_DINS_MODE_M)))
| (din_mode << SPI_MEM_DIN0_MODE_S) | (din_mode << SPI_MEM_DIN1_MODE_S) | (din_mode << SPI_MEM_DIN2_MODE_S) | (din_mode << SPI_MEM_DIN3_MODE_S)
| (din_mode << SPI_MEM_DIN4_MODE_S) | (din_mode << SPI_MEM_DIN5_MODE_S) | (din_mode << SPI_MEM_DIN6_MODE_S) | (din_mode << SPI_MEM_DIN7_MODE_S) | (din_mode << SPI_MEM_DINS_MODE_S);
REG_WRITE(SPI_MEM_DIN_MODE_REG(spi_num), reg_val);
}
/**
* Set MSPI Flash din num
*
* @param spi_num SPI0 / SPI1
* @param din_num Din num value
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_din_num(uint8_t spi_num, uint8_t din_num)
{
uint32_t reg_val = (REG_READ(SPI_MEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_DIN0_NUM_M | SPI_MEM_DIN1_NUM_M | SPI_MEM_DIN2_NUM_M | SPI_MEM_DIN3_NUM_M | SPI_MEM_DIN4_NUM_M | SPI_MEM_DIN5_NUM_M | SPI_MEM_DIN6_NUM_M | SPI_MEM_DIN7_NUM_M | SPI_MEM_DINS_NUM_M)))
| (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
| (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
REG_WRITE(SPI_MEM_DIN_NUM_REG(spi_num), reg_val);
}
/**
* Get MSPI Flash mode
*
* @param spi_num SPI0 / SPI1
*
* @return Flash mode
*/
__attribute__((always_inline))
static inline mspi_timing_ll_flash_mode_t mspi_timing_ll_get_flash_mode(uint8_t spi_num)
{
uint32_t ctrl_reg = READ_PERI_REG(SPI_MEM_CTRL_REG(0));
if (ctrl_reg & MSPI_TIMING_LL_FLASH_OCT_MASK) {
return MSPI_TIMING_LL_FLASH_OPI_MODE;
}
switch (ctrl_reg & MSPI_TIMING_LL_FLASH_QUAD_MASK) {
case MSPI_TIMING_LL_FLASH_QIO_MODE_MASK:
return MSPI_TIMING_LL_FLASH_QIO_MODE;
case MSPI_TIMING_LL_FLASH_QUAD_MODE_MASK:
return MSPI_TIMING_LL_FLASH_QUAD_MODE;
case MSPI_TIMING_LL_FLASH_DIO_MODE_MASK:
return MSPI_TIMING_LL_FLASH_DIO_MODE;
case MSPI_TIMING_LL_FLASH_DUAL_MODE_MASK:
return MSPI_TIMING_LL_FLASH_DUAL_MODE;
case MSPI_TIMING_LL_FLASH_FAST_MODE_MASK:
return MSPI_TIMING_LL_FLASH_FAST_MODE;
case MSPI_TIMING_LL_FLASH_SLOW_MODE_MASK:
return MSPI_TIMING_LL_FLASH_SLOW_MODE;
default:
HAL_ASSERT(false);
return (mspi_timing_ll_flash_mode_t)0;
}
}
/**
* Set MSPI Octal Flash extra dummy
*
* @param spi_num SPI0 / SPI1
* @param extra_dummy Extra dummy
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_octal_flash_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
{
if (extra_dummy > 0) {
SET_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
} else {
CLEAR_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, 0,
SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
}
}
/**
* Set MSPI Quad Flash dummy
*
* @param spi_num SPI0 / SPI1
* @param dummy dummy
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_quad_flash_dummy(uint8_t spi_num, uint8_t dummy)
{
//HW workaround: Use normal dummy register to set extra dummy, the calibration dedicated extra dummy register doesn't work for quad mode
SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_DUMMY);
SET_PERI_REG_BITS(SPI_MEM_USER1_REG(spi_num), SPI_MEM_USR_DUMMY_CYCLELEN_V, dummy, SPI_MEM_USR_DUMMY_CYCLELEN_S);
}
/**
* Set MSPI PSRAM din mode
*
* @param spi_num SPI0 / SPI1
* @param din_mode Din mode value
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_din_mode(uint8_t spi_num, uint8_t din_mode)
{
uint32_t reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_MODE_M | SPI_MEM_SPI_SMEM_DIN1_MODE_M | SPI_MEM_SPI_SMEM_DIN2_MODE_M | SPI_MEM_SPI_SMEM_DIN3_MODE_M | SPI_MEM_SPI_SMEM_DIN4_MODE_M | SPI_MEM_SPI_SMEM_DIN5_MODE_M | SPI_MEM_SPI_SMEM_DIN6_MODE_M | SPI_MEM_SPI_SMEM_DIN7_MODE_M | SPI_MEM_SPI_SMEM_DINS_MODE_M)))
| (din_mode << SPI_MEM_SPI_SMEM_DIN0_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN1_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN2_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN3_MODE_S)
| (din_mode << SPI_MEM_SPI_SMEM_DIN4_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN5_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN6_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN7_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DINS_MODE_S);
REG_WRITE(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num), reg_val);
}
/**
* Set MSPI PSRAM din num
*
* @param spi_num SPI0 / SPI1
* @param din_num Din num value
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_din_num(uint8_t spi_num, uint8_t din_num)
{
uint32_t reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_NUM_M | SPI_MEM_SPI_SMEM_DIN1_NUM_M | SPI_MEM_SPI_SMEM_DIN2_NUM_M | SPI_MEM_SPI_SMEM_DIN3_NUM_M | SPI_MEM_SPI_SMEM_DIN4_NUM_M | SPI_MEM_SPI_SMEM_DIN5_NUM_M | SPI_MEM_SPI_SMEM_DIN6_NUM_M | SPI_MEM_SPI_SMEM_DIN7_NUM_M | SPI_MEM_SPI_SMEM_DINS_NUM_M)))
| (din_num << SPI_MEM_SPI_SMEM_DIN0_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN1_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN2_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN3_NUM_S)
| (din_num << SPI_MEM_SPI_SMEM_DIN4_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN5_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN6_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN7_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DINS_NUM_S);
REG_WRITE(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num), reg_val);
}
/**
* Set MSPI Octal PSRAM extra dummy
*
* @param spi_num SPI0 / SPI1
* @param extra_dummy Extra dummy
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_octal_psram_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
{
if (extra_dummy > 0) {
SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
} else {
CLEAR_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, 0,
SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
}
}
/**
* Set MSPI Octal PSRAM dummy
*
* @param spi_num SPI0 / SPI1
* @param dummy dummy
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_quad_psram_dummy(uint8_t spi_num, uint8_t dummy)
{
//HW workaround: Use normal dummy register to set extra dummy, the calibration dedicated extra dummy register doesn't work for quad mode
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_USR_RD_SRAM_DUMMY_M);
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, dummy, SPI_MEM_SRAM_RDUMMY_CYCLELEN_S);
}
/**
* Clear MSPI hw fifo
*
* @param spi_num SPI0 / SPI1
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_clear_fifo(uint8_t spi_num)
{
for (int i = 0; i < 16; i++) {
REG_WRITE(SPI_MEM_W0_REG(spi_num) + i*4, 0);
}
}
/**
* Get if cs setup is enabled or not
*
* @param spi_num SPI0 / SPI1
*
* @return
* true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool mspi_timing_ll_is_cs_setup_enabled(uint8_t spi_num)
{
return REG_GET_BIT(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_SETUP);
}
/**
* Get cs setup val
*
* @param spi_num SPI0 / SPI1
*
* @return
* cs setup reg val
*/
static inline uint32_t mspi_timing_ll_get_cs_setup_val(uint8_t spi_num)
{
return REG_GET_FIELD(SPI_MEM_CTRL2_REG(spi_num), SPI_MEM_CS_SETUP_TIME);
}
/**
* Get if cs hold is enabled or not
*
* @param spi_num SPI0 / SPI1
*
* @return
* true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool mspi_timing_ll_is_cs_hold_enabled(uint8_t spi_num)
{
return REG_GET_BIT(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_HOLD);
}
/**
* Get cs hold val
*
* @param spi_num SPI0 / SPI1
*
* @return
* cs hold reg val
*/
static inline uint32_t mspi_timing_ll_get_cs_hold_val(uint8_t spi_num)
{
return REG_GET_FIELD(SPI_MEM_CTRL2_REG(spi_num), SPI_MEM_CS_HOLD_TIME);
}
/**
* Get clock reg val
*
* @param spi_num SPI0 / SPI1
*
* @return
* clock reg val
*/
__attribute__((always_inline))
static inline uint32_t mspi_timing_ll_get_clock_reg(uint8_t spi_num)
{
return READ_PERI_REG(SPI_MEM_CLOCK_REG(spi_num));
}
#ifdef __cplusplus
}
#endif

19
components/soc/esp32h21/include/soc/clk_tree_defs.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -244,6 +244,23 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
//////////////////////////////////////////////////FLASH///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of FLASH MSPI controller
*/
#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_PLL_F48M}
/**
* @brief FLASH MSPI controller clock source
*/
typedef enum {
FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
FLASH_CLK_SRC_PLL_F64M = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the source clock */
FLASH_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the default clock choice */
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_flash_clk_src_t;
#ifdef __cplusplus
}
#endif