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feat(uart): change fifo.byte to fifo.val when uart_ll_write_txfifo

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This commit is contained in:
gaoxu 2024-02-29 14:20:10 +08:00
parent f9109beda2
commit 1b1e4d2f76
7 changed files with 32 additions and 11 deletions
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7
components/hal/esp32c2/include/hal/uart_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -345,8 +345,11 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
*/
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
{
// Write to the FIFO should make sure only involve write operation, any read operation would cause data lost.
// Non-32-bit access would lead to a read-modify-write operation to the register, which is undesired.
// Therefore, use 32-bit access to avoid any potential problem.
for (int i = 0; i < (int)wr_len; i++) {
hw->ahb_fifo.rw_byte = buf[i];
hw->ahb_fifo.val = (int)buf[i];
}
}

7
components/hal/esp32c3/include/hal/uart_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -348,8 +348,11 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
*/
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
{
// Write to the FIFO should make sure only involve write operation, any read operation would cause data lost.
// Non-32-bit access would lead to a read-modify-write operation to the register, which is undesired.
// Therefore, use 32-bit access to avoid any potential problem.
for (int i = 0; i < (int)wr_len; i++) {
hw->ahb_fifo.rw_byte = buf[i];
hw->ahb_fifo.val = (int)buf[i];
}
}

5
components/hal/esp32c5/include/hal/uart_ll.h
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@ -540,8 +540,11 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
*/
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
{
// Write to the FIFO should make sure only involve write operation, any read operation would cause data lost.
// Non-32-bit access would lead to a read-modify-write operation to the register, which is undesired.
// Therefore, use 32-bit access to avoid any potential problem.
for (int i = 0; i < (int)wr_len; i++) {
hw->fifo.rxfifo_rd_byte = buf[i];
hw->fifo.val = (int)buf[i];
}
}

5
components/hal/esp32c6/include/hal/uart_ll.h
View File

@ -521,8 +521,11 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
*/
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
{
// Write to the FIFO should make sure only involve write operation, any read operation would cause data lost.
// Non-32-bit access would lead to a read-modify-write operation to the register, which is undesired.
// Therefore, use 32-bit access to avoid any potential problem.
for (int i = 0; i < (int)wr_len; i++) {
hw->fifo.rxfifo_rd_byte = buf[i];
hw->fifo.val = (int)buf[i];
}
}

7
components/hal/esp32h2/include/hal/uart_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -373,8 +373,11 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
*/
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
{
// Write to the FIFO should make sure only involve write operation, any read operation would cause data lost.
// Non-32-bit access would lead to a read-modify-write operation to the register, which is undesired.
// Therefore, use 32-bit access to avoid any potential problem.
for (int i = 0; i < (int)wr_len; i++) {
hw->fifo.rxfifo_rd_byte = buf[i];
hw->fifo.val = (int)buf[i];
}
}

5
components/hal/esp32p4/include/hal/uart_ll.h
View File

@ -634,8 +634,11 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
*/
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
{
// Write to the FIFO should make sure only involve write operation, any read operation would cause data lost.
// Non-32-bit access would lead to a read-modify-write operation to the register, which is undesired.
// Therefore, use 32-bit access to avoid any potential problem.
for (int i = 0; i < (int)wr_len; i++) {
hw->fifo.rxfifo_rd_byte = buf[i];
hw->fifo.val = (int)buf[i];
}
}

7
components/hal/esp32s3/include/hal/uart_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -332,8 +332,11 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
*/
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
{
// Write to the FIFO should make sure only involve write operation, any read operation would cause data lost.
// Non-32-bit access would lead to a read-modify-write operation to the register, which is undesired.
// Therefore, use 32-bit access to avoid any potential problem.
for (int i = 0; i < (int)wr_len; i++) {
hw->fifo.rxfifo_rd_byte = buf[i];
hw->fifo.val = (int)buf[i];
}
}