test_rtc: add test_app to test power consumption

components/esp_system/test_apps/rtc_power_modes/CMakeLists.txt

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+# This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.5)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(rtc_power_modes)

components/esp_system/test_apps/rtc_power_modes/README.md

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+| Supported Targets | ESP32-S3 |
+| ----------------- | -------- |
+
+# RTC power test
+
+This test app is to enter 7 different sub power modes we have, so that the power consumption under different power modes can be measured.
+
+Currently there are 6 sub power modes, 3 for deepsleep and 3 for lightsleep. Show as below (priority from high to low).
+
+## Deepsleep
+1. Mode for ADC/Temp Sensor in monitor mode (ULP). To enable this mode, call `rtc_sleep_enable_adc_tesn_monitor`.
+2. Default mode.
+3. Ultra low power mode. To enable this mode, call `rtc_sleep_enable_ultra_low`. Note if mode 1 has higher priority than this.
+
+## Lightsleep
+1. Mode for using 40 MHz XTAL in lightsleep. To enable this mode, call `esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON)`.
+2. Mode for using 8M clock by digital system (peripherals). To enable this mode, initialize LEDC with 8M clock source.
+3. Mode for ADC/Temp Sensor in monitor mode (ULP). To enable this mdoe, call `rtc_sleep_enable_adc_tesn_monitor`.
+4. Default mode.

components/esp_system/test_apps/rtc_power_modes/main/CMakeLists.txt

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+set(srcs "test_app_main.c"
+         "test_rtc_power.c")
+
+# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
+# the component can be registered as WHOLE_ARCHIVE
+idf_component_register(SRCS ${srcs}
+                       WHOLE_ARCHIVE)

components/esp_system/test_apps/rtc_power_modes/main/test_app_main.c

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+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "unity.h"
+#include "unity_test_runner.h"
+#include "unity_test_utils.h"
+
+#define LEAKS (400)
+
+
+void setUp(void)
+{
+    unity_utils_record_free_mem();
+}
+
+void tearDown(void)
+{
+    unity_utils_evaluate_leaks_direct(LEAKS);
+}
+
+void app_main(void)
+{
+    unity_run_menu();
+}

components/esp_system/test_apps/rtc_power_modes/main/test_rtc_power.c

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+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "esp_sleep.h"
+#include "unity.h"
+#include "unity_test_utils.h"
+#include "esp_log.h"
+#include "freertos/task.h"
+#include "driver/uart.h"
+#include "freertos/FreeRTOS.h"
+#include "soc/soc_caps.h"
+#include "driver/ledc.h"
+#include "soc/rtc.h"
+
+static const char TAG[] = "rtc_power";
+
+static void test_deepsleep(void)
+{
+    esp_sleep_enable_timer_wakeup(2000000);
+    ESP_LOGI(TAG, "Entering deep sleep");
+    esp_deep_sleep_start();
+}
+
+TEST_CASE("Power Test: Deepsleep (with ADC/TSEN in monitor)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+
+    extern void rtc_sleep_enable_adc_tesn_monitor(bool);
+    rtc_sleep_enable_adc_tesn_monitor(true);
+    test_deepsleep();
+}
+
+TEST_CASE("Power Test: Deepsleep (default)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+
+    test_deepsleep();
+}
+
+TEST_CASE("Power Test: Deepsleep (ultra-low power)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+
+    extern void rtc_sleep_enable_ultra_low(bool);
+    rtc_sleep_enable_ultra_low(true);
+    test_deepsleep();
+}
+
+static void test_lightsleep(void)
+{
+    esp_sleep_enable_timer_wakeup(2000000);
+
+    while (true) {
+        printf("Entering light sleep\n");
+        /* To make sure the complete line is printed before entering sleep mode,
+         * need to wait until UART TX FIFO is empty:
+         */
+        uart_wait_tx_idle_polling(CONFIG_ESP_CONSOLE_UART_NUM);
+
+        /* Enter sleep mode */
+        esp_light_sleep_start();
+
+        /* Determine wake up reason */
+        const char* wakeup_reason;
+        switch (esp_sleep_get_wakeup_cause()) {
+            case ESP_SLEEP_WAKEUP_TIMER:
+                wakeup_reason = "timer";
+                break;
+            default:
+                wakeup_reason = "other";
+                break;
+        }
+        printf("Returned from light sleep, reason: %s\n", wakeup_reason);
+
+        vTaskDelay(1000/portTICK_PERIOD_MS);
+    }
+}
+
+TEST_CASE("Power Test: Lightsleep (XTAL 40M)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+
+    esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
+    test_lightsleep();
+}
+
+TEST_CASE("Power Test: Lightsleep (8M by digital)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+
+    ledc_timer_config_t config = {
+        .speed_mode = LEDC_LOW_SPEED_MODE,
+        .duty_resolution = LEDC_TIMER_12_BIT,
+        .timer_num = 0,
+        .freq_hz = 2 * 1000,
+        .clk_cfg = LEDC_USE_RTC8M_CLK,
+    };
+    ledc_timer_config(&config);
+    test_lightsleep();
+}
+
+TEST_CASE("Power Test: Lightsleep (with ADC/TSEN in monitor)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+
+    extern void rtc_sleep_enable_adc_tesn_monitor(bool);
+    rtc_sleep_enable_adc_tesn_monitor(true);
+    test_lightsleep();
+}
+
+TEST_CASE("Power Test: Lightsleep (default)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+    test_lightsleep();
+}

components/esp_system/test_apps/rtc_power_modes/pytest_rtc_power.py

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+# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+
+import pytest
+from pytest_embedded import Dut
+
+# This is a manual test, not run on CI
+
+
+def deepsleep_test(dut: Dut, case_name: str) -> None:
+    dut.expect_exact('Press ENTER to see the list of tests')
+    dut.write(case_name)
+    reset_reason = 'DEEPSLEEP_RESET' if dut.target == 'esp32' else 'DSLEEP'
+    if dut.target == 'esp32c3':
+        # Known issue: IDF-5003
+        dut.expect(r'rst:.*\(%s\)' % reset_reason, timeout=40)
+    else:
+        dut.expect(r'rst:.*\(%s\)' % reset_reason, timeout=10)
+
+
+@pytest.mark.deepsleep
+def test_rtc_8md256_deepsleep(dut: Dut) -> None:
+    deepsleep_test(dut, '"Can use 8MD256 as RTC clock source in deepsleep"')
+
+
+@pytest.mark.deepsleep
+def test_rtc_8md256_deepsleep_force_rtcperiph(dut: Dut) -> None:
+    deepsleep_test(dut, '"Can use 8MD256 as RTC clock source in deepsleep (force rtc_periph)"')
+
+
+def lightsleep_test(dut: Dut, case_name: str) -> None:
+    dut.expect_exact('Press ENTER to see the list of tests')
+    dut.write(case_name)
+    if dut.target == 'esp32c3':
+        # Known issue: IDF-5003
+        dut.expect(r'Returned from light sleep, reason: timer', timeout=40)
+    else:
+        dut.expect(r'Returned from light sleep, reason: timer', timeout=10)
+
+
+@pytest.mark.deepsleep
+def test_rtc_8md256_lightsleep(dut: Dut) -> None:
+    lightsleep_test(dut, '"Can use 8MD256 as RTC clock source in lightsleep"')
+
+
+@pytest.mark.deepsleep
+def test_rtc_8md256_lightsleep_force_rtcperiph(dut: Dut) -> None:
+    lightsleep_test(dut, '"Can use 8MD256 as RTC clock source in lightsleep (force rtc_periph)"')

components/esp_system/test_apps/rtc_power_modes/sdkconfig.defaults

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+CONFIG_FREERTOS_HZ=1000
+CONFIG_ESP_TASK_WDT=n