From 1e1beb69aa0759f5f67ba4c775720852bfd71912 Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 23 Sep 2020 21:01:13 +0800 Subject: [PATCH] spi: fix build fail issue when target is esp32s3 --- components/hal/esp32s3/include/hal/spi_ll.h | 22 ++++++++++++++- components/hal/include/hal/spi_slave_hd_hal.h | 1 - components/hal/spi_hal.c | 27 ++++++++++++++++++ components/hal/spi_hal_iram.c | 28 +++++++++++++++++++ components/hal/spi_slave_hal.c | 28 +++++++++++++++++++ components/hal/spi_slave_hal_iram.c | 28 +++++++++++++++++++ components/hal/spi_slave_hd_hal.c | 28 +++++++++++++++++++ .../soc/soc/esp32s3/include/soc/soc_caps.h | 4 ++- 8 files changed, 163 insertions(+), 3 deletions(-) diff --git a/components/hal/esp32s3/include/hal/spi_ll.h b/components/hal/esp32s3/include/hal/spi_ll.h index 3475b3c14f..c9be4dfd47 100644 --- a/components/hal/esp32s3/include/hal/spi_ll.h +++ b/components/hal/esp32s3/include/hal/spi_ll.h @@ -48,6 +48,7 @@ extern "C" { * stored somewhere to be quickly used. */ typedef uint32_t spi_ll_clock_val_t; +typedef spi_dev_t spi_dma_dev_t; /** IO modes supported by the master. */ typedef enum { @@ -418,7 +419,7 @@ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) * @param hw Beginning address of the peripheral registers. * @param val stored clock configuration calculated before (by ``spi_ll_cal_clock``). */ -static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, spi_ll_clock_val_t *val) +static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_clock_val_t *val) { hw->clock.val = *(uint32_t *)val; } @@ -782,6 +783,25 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) return 0; } +static inline void spi_ll_dma_fifo_reset(spi_dev_t *hw) +{ +} + +static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) +{ +} + +static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable) +{ +} + +static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) +{ +} + +static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable) +{ +} #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK diff --git a/components/hal/include/hal/spi_slave_hd_hal.h b/components/hal/include/hal/spi_slave_hd_hal.h index 69ebba4105..e1cb5bc534 100644 --- a/components/hal/include/hal/spi_slave_hd_hal.h +++ b/components/hal/include/hal/spi_slave_hd_hal.h @@ -56,7 +56,6 @@ #include "hal/spi_ll.h" #include "hal/spi_types.h" - /// Configuration of the HAL typedef struct { uint32_t host_id; ///< Host ID of the spi peripheral diff --git a/components/hal/spi_hal.c b/components/hal/spi_hal.c index d22c851fcd..80fe3e842b 100644 --- a/components/hal/spi_hal.c +++ b/components/hal/spi_hal.c @@ -15,7 +15,34 @@ // The HAL layer for SPI (common part) #include "hal/spi_hal.h" +#include "soc/soc_caps.h" +#if SOC_GDMA_SUPPORTED +#include "soc/gdma_struct.h" +#include "hal/gdma_ll.h" + +#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL) +#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL); +#define spi_dma_ll_rx_enable_burst_data(dev, enable) gdma_ll_rx_enable_data_burst(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_ll_tx_enable_burst_data(dev, enable) gdma_ll_tx_enable_data_burst(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_ll_rx_enable_burst_desc(dev, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_ll_tx_enable_burst_desc(dev, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_set_rx_channel_priority(dev, priority) gdma_ll_rx_set_priority(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, priority); +#define spi_dma_set_tx_channel_priority(dev, priority) gdma_ll_tx_set_priority(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, priority); +#define spi_dma_enable_out_auto_wrback(dev, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_set_out_eof_generation(dev, enable) gdma_ll_tx_set_eof_mode(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_connect_rx_channel_to_periph(dev, periph_id) gdma_ll_rx_connect_to_periph(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, periph_id); +#define spi_dma_connect_tx_channel_to_periph(dev, periph_id) gdma_ll_tx_connect_to_periph(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, periph_id); +#define spi_dma_ll_rx_start(dev, addr) do {\ + gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, (uint32_t)addr);\ + gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL);\ + } while (0) +#define spi_dma_ll_tx_start(dev, addr) do {\ + gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, (uint32_t)addr);\ + gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL);\ + } while (0) + +#endif static const char SPI_HAL_TAG[] = "spi_hal"; #define SPI_HAL_CHECK(a, str, ret_val, ...) \ diff --git a/components/hal/spi_hal_iram.c b/components/hal/spi_hal_iram.c index f49c96dfe8..90706ef166 100644 --- a/components/hal/spi_hal_iram.c +++ b/components/hal/spi_hal_iram.c @@ -16,6 +16,34 @@ // make these functions in a seperate file to make sure all LL functions are in the IRAM. #include "hal/spi_hal.h" +#include "soc/soc_caps.h" + +#if SOC_GDMA_SUPPORTED +#include "soc/gdma_struct.h" +#include "hal/gdma_ll.h" + +#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL) +#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL); +#define spi_dma_ll_rx_enable_burst_data(dev, enable) gdma_ll_rx_enable_data_burst(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_ll_tx_enable_burst_data(dev, enable) gdma_ll_tx_enable_data_burst(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_ll_rx_enable_burst_desc(dev, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_ll_tx_enable_burst_desc(dev, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_set_rx_channel_priority(dev, priority) gdma_ll_rx_set_priority(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, priority); +#define spi_dma_set_tx_channel_priority(dev, priority) gdma_ll_tx_set_priority(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, priority); +#define spi_dma_enable_out_auto_wrback(dev, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_set_out_eof_generation(dev, enable) gdma_ll_tx_set_eof_mode(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_connect_rx_channel_to_periph(dev, periph_id) gdma_ll_rx_connect_to_periph(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, periph_id); +#define spi_dma_connect_tx_channel_to_periph(dev, periph_id) gdma_ll_tx_connect_to_periph(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, periph_id); +#define spi_dma_ll_rx_start(dev, addr) do {\ + gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, (uint32_t)addr);\ + gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL);\ + } while (0) +#define spi_dma_ll_tx_start(dev, addr) do {\ + gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, (uint32_t)addr);\ + gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL);\ + } while (0) + +#endif void spi_hal_setup_device(spi_hal_context_t *hal, const spi_hal_dev_config_t *dev) { diff --git a/components/hal/spi_slave_hal.c b/components/hal/spi_slave_hal.c index 904f620e84..b6a2e7dffb 100644 --- a/components/hal/spi_slave_hal.c +++ b/components/hal/spi_slave_hal.c @@ -1,5 +1,33 @@ #include "hal/spi_slave_hal.h" #include "hal/spi_ll.h" +#include "soc/soc_caps.h" + +#if SOC_GDMA_SUPPORTED +#include "soc/gdma_struct.h" +#include "hal/gdma_ll.h" + +#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL) +#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL); +#define spi_dma_ll_rx_enable_burst_data(dev, enable) gdma_ll_rx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_ll_tx_enable_burst_data(dev, enable) gdma_ll_tx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_ll_rx_enable_burst_desc(dev, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_ll_tx_enable_burst_desc(dev, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_set_rx_channel_priority(dev, priority) gdma_ll_rx_set_priority(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, priority); +#define spi_dma_set_tx_channel_priority(dev, priority) gdma_ll_tx_set_priority(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, priority); +#define spi_dma_enable_out_auto_wrback(dev, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_set_out_eof_generation(dev, enable) gdma_ll_tx_set_eof_mode(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_connect_rx_channel_to_periph(dev, periph_id) gdma_ll_rx_connect_to_periph(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, periph_id); +#define spi_dma_connect_tx_channel_to_periph(dev, periph_id) gdma_ll_tx_connect_to_periph(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, periph_id); +#define spi_dma_ll_rx_start(dev, addr) do {\ + gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\ + gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\ + } while (0) +#define spi_dma_ll_tx_start(dev, addr) do {\ + gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\ + gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\ + } while (0) + +#endif static void s_spi_slave_hal_dma_init_config(const spi_slave_hal_context_t *hal) { diff --git a/components/hal/spi_slave_hal_iram.c b/components/hal/spi_slave_hal_iram.c index 2d42737594..bb44d40410 100644 --- a/components/hal/spi_slave_hal_iram.c +++ b/components/hal/spi_slave_hal_iram.c @@ -1,5 +1,33 @@ #include "hal/spi_slave_hal.h" #include "hal/spi_ll.h" +#include "soc/soc_caps.h" + +#if SOC_GDMA_SUPPORTED +#include "soc/gdma_struct.h" +#include "hal/gdma_ll.h" + +#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL) +#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL); +#define spi_dma_ll_rx_enable_burst_data(dev, enable) gdma_ll_rx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_ll_tx_enable_burst_data(dev, enable) gdma_ll_tx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_ll_rx_enable_burst_desc(dev, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_ll_tx_enable_burst_desc(dev, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_set_rx_channel_priority(dev, priority) gdma_ll_rx_set_priority(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, priority); +#define spi_dma_set_tx_channel_priority(dev, priority) gdma_ll_tx_set_priority(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, priority); +#define spi_dma_enable_out_auto_wrback(dev, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_set_out_eof_generation(dev, enable) gdma_ll_tx_set_eof_mode(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_connect_rx_channel_to_periph(dev, periph_id) gdma_ll_rx_connect_to_periph(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, periph_id); +#define spi_dma_connect_tx_channel_to_periph(dev, periph_id) gdma_ll_tx_connect_to_periph(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, periph_id); +#define spi_dma_ll_rx_start(dev, addr) do {\ + gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\ + gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\ + } while (0) +#define spi_dma_ll_tx_start(dev, addr) do {\ + gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\ + gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\ + } while (0) + +#endif bool spi_slave_hal_usr_is_done(spi_slave_hal_context_t* hal) { diff --git a/components/hal/spi_slave_hd_hal.c b/components/hal/spi_slave_hd_hal.c index b966fcba0b..ac17c3c51b 100644 --- a/components/hal/spi_slave_hd_hal.c +++ b/components/hal/spi_slave_hd_hal.c @@ -22,6 +22,34 @@ #include "soc/spi_periph.h" #include "soc/lldesc.h" #include "hal/spi_slave_hd_hal.h" +#include "soc/soc_caps.h" + +#if SOC_GDMA_SUPPORTED +#include "soc/gdma_struct.h" +#include "hal/gdma_ll.h" + +#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL) +#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL); +#define spi_dma_ll_rx_enable_burst_data(dev, enable) gdma_ll_rx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_ll_tx_enable_burst_data(dev, enable) gdma_ll_tx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_ll_rx_enable_burst_desc(dev, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_ll_tx_enable_burst_desc(dev, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_set_rx_channel_priority(dev, priority) gdma_ll_rx_set_priority(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, priority); +#define spi_dma_set_tx_channel_priority(dev, priority) gdma_ll_tx_set_priority(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, priority); +#define spi_dma_enable_out_auto_wrback(dev, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_set_out_eof_generation(dev, enable) gdma_ll_tx_set_eof_mode(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_connect_rx_channel_to_periph(dev, periph_id) gdma_ll_rx_connect_to_periph(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, periph_id); +#define spi_dma_connect_tx_channel_to_periph(dev, periph_id) gdma_ll_tx_connect_to_periph(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, periph_id); +#define spi_dma_ll_rx_start(dev, addr) do {\ + gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\ + gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\ + } while (0) +#define spi_dma_ll_tx_start(dev, addr) do {\ + gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\ + gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\ + } while (0) + +#endif static void s_spi_slave_hd_hal_dma_init_config(const spi_slave_hd_hal_context_t *hal) { diff --git a/components/soc/soc/esp32s3/include/soc/soc_caps.h b/components/soc/soc/esp32s3/include/soc/soc_caps.h index de1b02ae73..1e19ad7fb8 100644 --- a/components/soc/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/soc/esp32s3/include/soc/soc_caps.h @@ -12,4 +12,6 @@ // Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically // Remove them when GDMA driver API is ready -#define SOC_GDMA_M2M_DMA_CHANNEL (0) +#define SOC_GDMA_M2M_DMA_CHANNEL (0) +#define SOC_GDMA_SPI2_DMA_CHANNEL (1) +#define SOC_GDMA_SPI3_DMA_CHANNEL (2) \ No newline at end of file