From 1ef989a1b51b30ef38e6aaab50f59a6f0f05b13e Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 11 Aug 2021 17:35:21 +0800 Subject: [PATCH] update reset reason for c3/s3/h2 --- components/esp_rom/include/esp32c3/rom/rtc.h | 8 ++++++-- components/esp_rom/include/esp32s3/rom/rtc.h | 3 +++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/components/esp_rom/include/esp32c3/rom/rtc.h b/components/esp_rom/include/esp32c3/rom/rtc.h index 8c9be5ea26..85241bf83f 100644 --- a/components/esp_rom/include/esp32c3/rom/rtc.h +++ b/components/esp_rom/include/esp32c3/rom/rtc.h @@ -82,8 +82,7 @@ typedef enum { NO_MEAN = 0, POWERON_RESET = 1, /**<1, Vbat power on reset*/ RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/ - DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/ - SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core*/ + DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/ TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/ TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/ RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/ @@ -95,6 +94,11 @@ typedef enum { RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/ TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/ SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/ + GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/ + EFUSE_RESET = 20, /**<20, efuse reset digital core*/ + USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */ + USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */ + POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/ } RESET_REASON; typedef enum { diff --git a/components/esp_rom/include/esp32s3/rom/rtc.h b/components/esp_rom/include/esp32s3/rom/rtc.h index a5a1ecb6a1..34b0affe10 100644 --- a/components/esp_rom/include/esp32s3/rom/rtc.h +++ b/components/esp_rom/include/esp32s3/rom/rtc.h @@ -90,6 +90,9 @@ typedef enum { SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/ GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/ EFUSE_RESET = 20, /**<20, efuse reset digital core*/ + USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */ + USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */ + POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/ } RESET_REASON; typedef enum {