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https://github.com/espressif/esp-idf
synced 2025-03-09 09:09:10 -04:00
refactor(ecdsa): rely on efuse to get chip revision
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@ -42,10 +42,6 @@ ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
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esp_crypto_dpa_protection_startup();
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#endif
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#if SOC_ECDSA_REGISTER_INCOMPATIBILITY_ACROSS_REV
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ecdsa_compatible_mem_reg_addr_init();
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#endif
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#if CONFIG_ESP_CRYPTO_FORCE_ECC_CONSTANT_TIME_POINT_MUL
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bool force_constant_time = true;
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#if CONFIG_IDF_TARGET_ESP32H2
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@ -27,10 +27,6 @@ if(target STREQUAL "esp32")
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list(APPEND srcs "${target_folder}/dport_access.c")
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endif()
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if(target STREQUAL "esp32h2")
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list(APPEND srcs "${target_folder}/ecdsa_reg_addr.c")
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endif()
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if(CONFIG_SOC_ADC_SUPPORTED)
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list(APPEND srcs "${target_folder}/adc_periph.c")
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endif()
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@ -1,28 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// This file initialises the memory register addresses for the ECDSA accelerator
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// This software initialization is required due to incompatibility between the old and new ECDSA versions
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// for the ESP32-H2 ECDSA accelerator
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#include <stddef.h>
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#include "soc/ecdsa_reg.h"
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// Initializing the memory address with the base address of the old ECDSA version
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uint32_t ECDSA_R_MEM = (DR_REG_ECDSA_BASE + 0xA00);
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uint32_t ECDSA_S_MEM = (DR_REG_ECDSA_BASE + 0xA20);
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uint32_t ECDSA_Z_MEM = (DR_REG_ECDSA_BASE + 0xA40);
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uint32_t ECDSA_QAX_MEM = (DR_REG_ECDSA_BASE + 0xA60);
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uint32_t ECDSA_QAY_MEM = (DR_REG_ECDSA_BASE + 0xA80);
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void ecdsa_compatible_mem_reg_addr_init(void)
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{
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// set the memory registers based on the DATE register value
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ECDSA_R_MEM = (DR_REG_ECDSA_BASE + ECDSA_REG_GET_OFFSET(0xA00, 0x340));
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ECDSA_S_MEM = (DR_REG_ECDSA_BASE + ECDSA_REG_GET_OFFSET(0xA20, 0x360));
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ECDSA_Z_MEM = (DR_REG_ECDSA_BASE + ECDSA_REG_GET_OFFSET(0xA40, 0x380));
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ECDSA_QAX_MEM = (DR_REG_ECDSA_BASE + ECDSA_REG_GET_OFFSET(0xA60, 0x3A0));
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ECDSA_QAY_MEM = (DR_REG_ECDSA_BASE + ECDSA_REG_GET_OFFSET(0xA80, 0x3C0));
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}
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13
components/soc/esp32h2/include/soc/chip_rev.h
Normal file
13
components/soc/esp32h2/include/soc/chip_rev.h
Normal file
@ -0,0 +1,13 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/efuse_struct.h"
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#define ESP_SOC_GET_CHIP_REV (EFUSE.rd_mac_sys_3.wafer_version_major * 100 + EFUSE.rd_mac_sys_3.wafer_version_minor)
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#define REG_COMPATIBLE_ADDR(rev, before_addr, after_addr) ((ESP_SOC_GET_CHIP_REV >= (rev)) ? (after_addr) : (before_addr))
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@ -7,6 +7,8 @@
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/chip_rev.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -448,34 +450,33 @@ extern "C" {
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/** ECDSA_R_MEM register
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* The memory that stores r.
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*/
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extern uint32_t ECDSA_R_MEM;
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#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + REG_COMPATIBLE_ADDR(102, 0xa00, 0x340))
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#define ECDSA_R_MEM_SIZE_BYTES 32
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/** ECDSA_S_MEM register
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* The memory that stores s.
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*/
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extern uint32_t ECDSA_S_MEM;
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#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + REG_COMPATIBLE_ADDR(102, 0xa20, 0x360))
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#define ECDSA_S_MEM_SIZE_BYTES 32
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/** ECDSA_Z_MEM register
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* The memory that stores software written z.
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*/
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extern uint32_t ECDSA_Z_MEM;
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#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + REG_COMPATIBLE_ADDR(102, 0xa40, 0x380))
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#define ECDSA_Z_MEM_SIZE_BYTES 32
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/** ECDSA_QAX_MEM register
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* The memory that stores x coordinates of QA or software written k.
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*/
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extern uint32_t ECDSA_QAX_MEM;
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#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + REG_COMPATIBLE_ADDR(102, 0xa60, 0x3a0))
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#define ECDSA_QAX_MEM_SIZE_BYTES 32
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/** ECDSA_QAY_MEM register
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* The memory that stores y coordinates of QA.
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*/
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extern uint32_t ECDSA_QAY_MEM;
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#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + REG_COMPATIBLE_ADDR(102, 0xa80, 0x3c0))
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#define ECDSA_QAY_MEM_SIZE_BYTES 32
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#ifdef __cplusplus
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}
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#endif
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