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https://github.com/espressif/esp-idf
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fix(cache): fixed cache hal ctx not initialised in app issue
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@ -45,7 +45,6 @@
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#include "soc/assist_debug_reg.h"
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#include "soc/system_reg.h"
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#include "esp32s3/rom/opi_flash.h"
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#include "hal/cache_hal.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rtc.h"
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#include "esp32c3/rom/cache.h"
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@ -83,6 +82,7 @@
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#include "esp_private/sleep_gpio.h"
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#include "hal/wdt_hal.h"
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#include "soc/rtc.h"
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#include "hal/cache_hal.h"
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#include "hal/cache_ll.h"
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#include "hal/efuse_ll.h"
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#include "soc/periph_defs.h"
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@ -374,6 +374,11 @@ void IRAM_ATTR call_start_cpu0(void)
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#endif
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#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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//cache hal ctx needs to be initialised
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cache_hal_init();
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#endif
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// When the APP is loaded into ram for execution, some hardware initialization behaviors
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// in the bootloader are still necessary
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#if CONFIG_APP_BUILD_TYPE_RAM
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -8,6 +8,11 @@
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static uint32_t s_cache_status[2];
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void cache_hal_init(void)
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{
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//for compatibility
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}
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void cache_hal_suspend(cache_type_t type)
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{
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s_cache_status[0] = cache_ll_l1_get_enabled_bus(0);
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