From 2422c5285113d5108ae4b9c6a75c8949ab69ff54 Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 27 Dec 2019 17:08:28 +0800 Subject: [PATCH] global: hello world on real esp32-s2 --- Kconfig | 1 - .../bootloader_support/src/bootloader_clock.c | 11 - .../src/bootloader_utility.c | 2 - .../test/include/test/test_common_spi.h | 14 - components/driver/test/test_spi_param.c | 14 - components/esp32s2beta/clk.c | 6 +- components/esp32s2beta/cpu_start.c | 4 - components/esp32s2beta/sleep_modes.c | 4 +- .../esp32s2beta/system_api_esp32s2beta.c | 4 - components/esptool_py/esptool | 2 +- components/freertos/test/test_thread_local.c | 2 +- components/heap/test/test_leak.c | 4 +- components/mbedtls/test/test_mbedtls_sha.c | 2 +- .../esp32s2beta/include/hal/touch_sensor_ll.h | 12 +- components/soc/esp32s2beta/include/soc/rtc.h | 230 +++++++- .../esp32s2beta/include/soc/rtc_cntl_reg.h | 11 - .../soc/esp32s2beta/include/soc/sens_reg.h | 4 +- .../soc/esp32s2beta/include/soc/sens_struct.h | 10 +- components/soc/esp32s2beta/include/soc/soc.h | 2 +- components/soc/esp32s2beta/rtc_clk.c | 551 ++++++++---------- components/soc/esp32s2beta/rtc_init.c | 71 +-- components/soc/esp32s2beta/rtc_sleep.c | 140 ++--- components/soc/esp32s2beta/rtc_time.c | 14 +- components/soc/esp32s2beta/spi_periph.c | 2 +- .../esp32s2beta/spi_flash_rom_patch.c | 8 +- 25 files changed, 537 insertions(+), 588 deletions(-) diff --git a/Kconfig b/Kconfig index 3dee973b84..b2a207e3b6 100644 --- a/Kconfig +++ b/Kconfig @@ -28,7 +28,6 @@ mainmenu "Espressif IoT Development Framework Configuration" bool default "y" if IDF_TARGET="esp32s2beta" select FREERTOS_UNICORE - select IDF_ENV_FPGA config IDF_FIRMWARE_CHIP_ID hex diff --git a/components/bootloader_support/src/bootloader_clock.c b/components/bootloader_support/src/bootloader_clock.c index 2c01a49ebc..9e156e583e 100644 --- a/components/bootloader_support/src/bootloader_clock.c +++ b/components/bootloader_support/src/bootloader_clock.c @@ -26,16 +26,6 @@ #include "esp32s2beta/rom/rtc.h" #endif -#if CONFIG_IDF_ENV_FPGA -void bootloader_clock_configure(void) -{ - uart_tx_wait_idle(0); - REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0); - rtc_cpu_freq_t cpu_freq = ets_get_apb_freq(); - ets_update_cpu_frequency(cpu_freq / 1000000); - REG_WRITE(RTC_CNTL_STORE5_REG, (cpu_freq >> 12) | ((cpu_freq >> 12) << 16)); -} -#else // CONFIG_IDF_ENV_FPGA void bootloader_clock_configure(void) { // ROM bootloader may have put a lot of text into UART0 FIFO. @@ -83,7 +73,6 @@ void bootloader_clock_configure(void) } #endif } -#endif // CONFIG_IDF_ENV_FPGA #ifdef BOOTLOADER_BUILD diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 4a9cc709fc..88b675cb08 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -615,9 +615,7 @@ static void load_image(const esp_image_metadata_t *image_data) #endif ESP_LOGI(TAG, "Disabling RNG early entropy source..."); -#if !CONFIG_IDF_ENV_FPGA bootloader_random_disable(); -#endif // copy loaded segments to RAM, set up caches for mapped segments, and start application unpack_load_app(image_data); diff --git a/components/driver/test/include/test/test_common_spi.h b/components/driver/test/include/test/test_common_spi.h index 80aa4399e1..29521ba666 100644 --- a/components/driver/test/include/test/test_common_spi.h +++ b/components/driver/test/include/test/test_common_spi.h @@ -109,7 +109,6 @@ #define PSET_NAME_LEN 30 ///< length of each param set name //test low frequency, high frequency until freq limit for worst case (both GPIO) -#if APB_CLK_FREQ==80*1000*1000 #define TEST_FREQ_DEFAULT(){ \ 1*1000*1000, \ SPI_MASTER_FREQ_8M , \ @@ -124,19 +123,6 @@ SPI_MASTER_FREQ_80M, \ 0,\ } -#endif - -#if APB_CLK_FREQ==40*1000*1000 -#define TEST_FREQ_DEFAULT(){ \ - 1*1000*1000, \ - SPI_MASTER_FREQ_8M , \ - SPI_MASTER_FREQ_10M, \ - SPI_MASTER_FREQ_13M, \ - SPI_MASTER_FREQ_20M, \ - SPI_MASTER_FREQ_40M, \ - 0,\ - } -#endif //default bus config for tests #define SPI_BUS_TEST_DEFAULT_CONFIG() {\ diff --git a/components/driver/test/test_spi_param.c b/components/driver/test/test_spi_param.c index 946051c6b8..dd578087b8 100644 --- a/components/driver/test/test_spi_param.c +++ b/components/driver/test/test_spi_param.c @@ -299,17 +299,11 @@ TEST_SPI_LOCAL(TIMING, timing_pgroup) #define FREQ_LIMIT_MODE SPI_MASTER_FREQ_16M static int test_freq_mode_local[]={ 1*1000*1000, -#if APB_CLK_FREQ==80*1000*1000 SPI_MASTER_FREQ_9M, //maximum freq MISO stable before next latch edge -#endif SPI_MASTER_FREQ_13M, -#if APB_CLK_FREQ==80*1000*1000 SPI_MASTER_FREQ_16M, -#endif SPI_MASTER_FREQ_20M, -#if APB_CLK_FREQ==80*1000*1000 SPI_MASTER_FREQ_26M, -#endif SPI_MASTER_FREQ_40M, 0, }; @@ -351,7 +345,6 @@ static spitest_param_set_t mode_pgroup[] = { .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, }, -#if APB_CLK_FREQ==80*1000*1000 { .pset_name = "Mode 1", .freq_list = test_freq_mode_local, .freq_limit = SPI_MASTER_FREQ_26M, @@ -362,7 +355,6 @@ static spitest_param_set_t mode_pgroup[] = { .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, }, -#endif { .pset_name = "Mode 2", .freq_list = test_freq_mode_local, .master_limit = SPI_MASTER_FREQ_13M, @@ -372,7 +364,6 @@ static spitest_param_set_t mode_pgroup[] = { .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, }, -#if APB_CLK_FREQ==80*1000*1000 { .pset_name = "Mode 3", .freq_list = test_freq_mode_local, .freq_limit = SPI_MASTER_FREQ_26M, @@ -383,7 +374,6 @@ static spitest_param_set_t mode_pgroup[] = { .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, }, -#endif { .pset_name = "Mode 0, DMA", .freq_list = test_freq_mode_local, .master_limit = SPI_MASTER_FREQ_13M, @@ -395,7 +385,6 @@ static spitest_param_set_t mode_pgroup[] = { .slave_tv_ns = TV_INT_CONNECT, .length_aligned = true, }, -#if APB_CLK_FREQ==80*1000*1000 { .pset_name = "Mode 1, DMA", .freq_list = test_freq_mode_local, .freq_limit = SPI_MASTER_FREQ_26M, @@ -408,7 +397,6 @@ static spitest_param_set_t mode_pgroup[] = { .slave_tv_ns = TV_INT_CONNECT, .length_aligned = true, }, -#endif { .pset_name = "Mode 2, DMA", .freq_list = test_freq_mode_local, .master_limit = SPI_MASTER_FREQ_13M, @@ -420,7 +408,6 @@ static spitest_param_set_t mode_pgroup[] = { .slave_tv_ns = TV_INT_CONNECT, .length_aligned = true, }, -#if APB_CLK_FREQ==80*1000*1000 { .pset_name = "Mode 3, DMA", .freq_list = test_freq_mode_local, .freq_limit = SPI_MASTER_FREQ_26M, @@ -433,7 +420,6 @@ static spitest_param_set_t mode_pgroup[] = { .slave_tv_ns = TV_INT_CONNECT, .length_aligned = true, }, -#endif /////////////////////////// MISO //////////////////////////////////// { .pset_name = "MISO, Mode 0", .freq_list = test_freq_mode_local, diff --git a/components/esp32s2beta/clk.c b/components/esp32s2beta/clk.c index 04a4fd4b98..94e8578e26 100644 --- a/components/esp32s2beta/clk.c +++ b/components/esp32s2beta/clk.c @@ -210,7 +210,7 @@ void esp_perip_clk_init(void) rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET) { common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG); - hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG); + hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG); wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG); } else { common_perip_clk = DPORT_WDG_CLK_EN | @@ -288,8 +288,8 @@ void esp_perip_clk_init(void) DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, common_perip_clk1); /* Disable hardware crypto clocks. */ - DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_CLK_EN_REG, hwcrypto_perip_clk); - DPORT_SET_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, hwcrypto_perip_clk); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, hwcrypto_perip_clk); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, hwcrypto_perip_clk); /* Disable WiFi/BT/SDIO clocks. */ DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk); diff --git a/components/esp32s2beta/cpu_start.c b/components/esp32s2beta/cpu_start.c index 12cfad40bb..024793fc5c 100644 --- a/components/esp32s2beta/cpu_start.c +++ b/components/esp32s2beta/cpu_start.c @@ -250,12 +250,8 @@ void start_cpu0_default(void) trax_enable(TRAX_ENA_PRO); trax_start_trace(TRAX_DOWNCOUNT_WORDS); #endif -#if !CONFIG_IDF_ENV_FPGA // ToDo: remove it once we get a real chip esp_clk_init(); esp_perip_clk_init(); -#else - ets_update_cpu_frequency(CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ); -#endif intr_matrix_clear(); #ifndef CONFIG_ESP_CONSOLE_UART_NONE diff --git a/components/esp32s2beta/sleep_modes.c b/components/esp32s2beta/sleep_modes.c index 44337e9027..f063ba2179 100644 --- a/components/esp32s2beta/sleep_modes.c +++ b/components/esp32s2beta/sleep_modes.c @@ -196,7 +196,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) s_config.sleep_duration > 0) { timer_wakeup_prepare(); } - uint32_t result = rtc_sleep_start(s_config.wakeup_triggers, 0); + uint32_t result = rtc_sleep_start(s_config.wakeup_triggers, 0, 1); // Restore CPU frequency rtc_clk_cpu_freq_set(cpu_freq); @@ -422,7 +422,7 @@ touch_pad_t esp_sleep_get_touchpad_wakeup_status(void) return TOUCH_PAD_MAX; } touch_pad_t pad_num; - esp_err_t ret = touch_pad_get_wakeup_status(&pad_num); + esp_err_t ret = touch_pad_get_wakeup_status(&pad_num); //TODO 723diff commit id:fda9ada1b assert(ret == ESP_OK && "wakeup reason is RTC_TOUCH_TRIG_EN but SENS_TOUCH_MEAS_EN is zero"); return pad_num; } diff --git a/components/esp32s2beta/system_api_esp32s2beta.c b/components/esp32s2beta/system_api_esp32s2beta.c index ef356a24e0..f69f88dc70 100644 --- a/components/esp32s2beta/system_api_esp32s2beta.c +++ b/components/esp32s2beta/system_api_esp32s2beta.c @@ -94,9 +94,7 @@ void IRAM_ATTR esp_restart_noos(void) DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); // Set CPU back to XTAL source, no PLL, same as hard reset -#if !CONFIG_IDF_ENV_FPGA rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL); -#endif // Reset CPUs if (core_id == 0) { @@ -114,6 +112,4 @@ void esp_chip_info(esp_chip_info_t *out_info) out_info->model = CHIP_ESP32S2BETA; out_info->cores = 1; out_info->features = CHIP_FEATURE_WIFI_BGN; - - // FIXME: other features? } diff --git a/components/esptool_py/esptool b/components/esptool_py/esptool index abdceb512d..51fe3c19f1 160000 --- a/components/esptool_py/esptool +++ b/components/esptool_py/esptool @@ -1 +1 @@ -Subproject commit abdceb512db1cf2faffbb261a5e474442bc41bdb +Subproject commit 51fe3c19f1b999869d9b071665c9555f24df924c diff --git a/components/freertos/test/test_thread_local.c b/components/freertos/test/test_thread_local.c index 64dbc0b9b7..d2d97caa23 100644 --- a/components/freertos/test/test_thread_local.c +++ b/components/freertos/test/test_thread_local.c @@ -24,7 +24,7 @@ static __thread struct test_tls_var { uint8_t farr[10]; } tl_test_struct_var; -static __attribute__((unused)) void task_test_tls(void *arg) +static void task_test_tls(void *arg) { bool *running = (bool *)arg; uint32_t tp = (uint32_t)-1; diff --git a/components/heap/test/test_leak.c b/components/heap/test/test_leak.c index d66a26a169..0144cd937e 100644 --- a/components/heap/test/test_leak.c +++ b/components/heap/test/test_leak.c @@ -46,13 +46,13 @@ TEST_CASE_MULTIPLE_STAGES("Not check for leaks in MULTIPLE_STAGES mode", "[heap] TEST_CASE_MULTIPLE_STAGES("Check for leaks in MULTIPLE_STAGES mode (leak)", "[heap][ignore]", test_fn, test_fn, test_fn); -static __attribute__((unused)) void test_fn2(void) +static void test_fn2(void) { check_calloc(1000); esp_restart(); } -static __attribute__((unused)) void test_fn3(void) +static void test_fn3(void) { check_calloc(1000); } diff --git a/components/mbedtls/test/test_mbedtls_sha.c b/components/mbedtls/test/test_mbedtls_sha.c index ad3041965e..1798f0015d 100644 --- a/components/mbedtls/test/test_mbedtls_sha.c +++ b/components/mbedtls/test/test_mbedtls_sha.c @@ -264,7 +264,7 @@ typedef struct { bool done; } finalise_sha_param_t; -static __attribute__((unused)) void tskFinaliseSha(void *v_param) +static void tskFinaliseSha(void *v_param) { finalise_sha_param_t *param = (finalise_sha_param_t *)v_param; diff --git a/components/soc/esp32s2beta/include/hal/touch_sensor_ll.h b/components/soc/esp32s2beta/include/hal/touch_sensor_ll.h index ef86de5ad2..3f0075c72f 100644 --- a/components/soc/esp32s2beta/include/hal/touch_sensor_ll.h +++ b/components/soc/esp32s2beta/include/hal/touch_sensor_ll.h @@ -945,11 +945,11 @@ static inline void touch_ll_proximity_get_meas_times(uint32_t *times) static inline void touch_ll_proximity_read_meas_cnt(touch_pad_t touch_num, uint32_t *cnt) { if (SENS.sar_touch_conf.touch_approach_pad0 == touch_num) { - *cnt = SENS.sar_touch_appr_status.touch_approach_pad0_cnt; + *cnt = SENS.sar_touch_status16.touch_approach_pad0_cnt; } else if (SENS.sar_touch_conf.touch_approach_pad1 == touch_num) { - *cnt = SENS.sar_touch_appr_status.touch_approach_pad1_cnt; + *cnt = SENS.sar_touch_status16.touch_approach_pad1_cnt; } else if (SENS.sar_touch_conf.touch_approach_pad2 == touch_num) { - *cnt = SENS.sar_touch_appr_status.touch_approach_pad2_cnt; + *cnt = SENS.sar_touch_status16.touch_approach_pad2_cnt; } } @@ -1040,7 +1040,7 @@ static inline void touch_ll_sleep_disable_approach(void) */ static inline void touch_ll_sleep_read_baseline(uint32_t *baseline) { - *baseline = REG_GET_FIELD(SENS_SAR_TOUCH_SLP_STATUS_REG, SENS_TOUCH_SLP_BASELINE); + *baseline = REG_GET_FIELD(SENS_SAR_TOUCH_STATUS15_REG, SENS_TOUCH_SLP_BASELINE); } /** @@ -1050,7 +1050,7 @@ static inline void touch_ll_sleep_read_baseline(uint32_t *baseline) */ static inline void touch_ll_sleep_read_debounce(uint32_t *debounce) { - *debounce = REG_GET_FIELD(SENS_SAR_TOUCH_SLP_STATUS_REG, SENS_TOUCH_SLP_DEBOUNCE); + *debounce = REG_GET_FIELD(SENS_SAR_TOUCH_STATUS15_REG, SENS_TOUCH_SLP_DEBOUNCE); } /** @@ -1059,7 +1059,7 @@ static inline void touch_ll_sleep_read_debounce(uint32_t *debounce) */ static inline void touch_ll_sleep_read_proximity_cnt(uint32_t *approach_cnt) { - *approach_cnt = REG_GET_FIELD(SENS_SAR_TOUCH_APPR_STATUS_REG, SENS_TOUCH_SLP_APPROACH_CNT); + *approach_cnt = REG_GET_FIELD(SENS_SAR_TOUCH_STATUS16_REG, SENS_TOUCH_SLP_APPROACH_CNT); } /** diff --git a/components/soc/esp32s2beta/include/soc/rtc.h b/components/soc/esp32s2beta/include/soc/rtc.h index 3e7fc8083d..f14c77650e 100644 --- a/components/soc/esp32s2beta/include/soc/rtc.h +++ b/components/soc/esp32s2beta/include/soc/rtc.h @@ -51,6 +51,79 @@ extern "C" { * - rtc_init: initialization */ +#define MHZ (1000000) + +#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) + +#define RTC_SLOW_CLK_FREQ_150K 150000 +#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256) +#define RTC_SLOW_CLK_FREQ_32K 32768 + +#define OTHER_BLOCKS_POWERUP 1 +#define OTHER_BLOCKS_WAIT 1 + +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ +#define RTC_CNTL_DBIAS_0V90 0 +#define RTC_CNTL_DBIAS_0V95 1 +#define RTC_CNTL_DBIAS_1V00 2 +#define RTC_CNTL_DBIAS_1V05 3 +#define RTC_CNTL_DBIAS_1V10 4 +#define RTC_CNTL_DBIAS_1V15 5 +#define RTC_CNTL_DBIAS_1V20 6 +#define RTC_CNTL_DBIAS_1V25 7 + +#define DELAY_FAST_CLK_SWITCH 3 +#define DELAY_SLOW_CLK_SWITCH 300 +#define DELAY_8M_ENABLE 50 + +/* Number of 8M/256 clock cycles to use for XTAL frequency estimation. + * 10 cycles will take approximately 300 microseconds. + */ +#define XTAL_FREQ_EST_CYCLES 10 + +/* Core voltage needs to be increased in two cases: + * 1. running at 240 MHz + * 2. running with 80MHz Flash frequency + */ +#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25 +#else +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 +#endif +#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25 +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 +#define RTC_CK8M_ENABLE_WAIT_DEFAULT 1 + +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 + +/* +set sleep_init default param +*/ +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 + +#define APLL_SDM_STOP_VAL_1 0x09 +#define APLL_SDM_STOP_VAL_2_REV0 0x69 +#define APLL_SDM_STOP_VAL_2_REV1 0x49 +#define APLL_CAL_DELAY_1 0x0f +#define APLL_CAL_DELAY_2 0x3f +#define APLL_CAL_DELAY_3 0x1f /** * @brief Possible main XTAL frequency values. @@ -70,6 +143,9 @@ typedef enum { RTC_CPU_FREQ_160M = 2, //!< 160 MHz RTC_CPU_FREQ_240M = 3, //!< 240 MHz RTC_CPU_FREQ_2M = 4, //!< 2 MHz + RTC_CPU_320M_80M = 5, //!< for test + RTC_CPU_320M_160M = 6, //!< for test + RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset } rtc_cpu_freq_t; /** @@ -92,6 +168,11 @@ typedef enum { /* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */ #define RTC_FAST_CLK_FREQ_APPROX 8500000 +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO +#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO + /** * @brief Clock source to be calibrated using rtc_clk_cal function */ @@ -109,7 +190,8 @@ typedef struct { rtc_cpu_freq_t cpu_freq : 3; //!< CPU frequency to set rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set - uint32_t clk_8m_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t clk_rtc_clk_div : 8; + uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) } rtc_clk_config_t; @@ -122,11 +204,74 @@ typedef struct { .cpu_freq = RTC_CPU_FREQ_80M, \ .fast_freq = RTC_FAST_FREQ_8M, \ .slow_freq = RTC_SLOW_FREQ_RTC, \ - .clk_8m_div = 0, \ + .clk_rtc_clk_div = 0, \ + .clk_8m_clk_div = 0, \ .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ } +typedef struct { + uint32_t dac : 6; + uint32_t dres : 3; + uint32_t dgm : 3; + uint32_t dbuf: 1; +} x32k_config_t; + +#define X32K_CONFIG_DEFAULT() { \ + .dac = 1, \ + .dres = 3, \ + .dgm = 0, \ + .dbuf = 1, \ +} + +#if 0 +#define X32K_CONFIG_BOOTSTRAP_DEFAULT() { \ + .dac = 3, \ + .dres = 3, \ + .dgm = 0, \ +} + +typedef struct { + x32k_config_t x32k_cfg; + uint32_t bt_lpck_div_num : 12; + uint32_t bt_lpck_div_a : 12; + uint32_t bt_lpck_div_b : 12; +} x32k_bootstrap_config_t; + +#define X32K_BOOTSTRAP_CONFIG_DEFAULT() { \ + .x32k_cfg = X32K_CONFIG_BOOTSTRAP_DEFAULT(), \ + .bt_lpck_div_num = 2441, \ + .bt_lpck_div_a = 32, \ + .bt_lpck_div_b = 13, \ +} +#endif + +typedef struct { + uint16_t wifi_powerup_cycles : 7; + uint16_t wifi_wait_cycles : 9; + uint16_t rtc_powerup_cycles : 7; + uint16_t rtc_wait_cycles : 9; + uint16_t dg_wrap_powerup_cycles : 7; + uint16_t dg_wrap_wait_cycles : 9; + uint16_t rtc_mem_powerup_cycles : 7; + uint16_t rtc_mem_wait_cycles : 9; +} rtc_init_config_t; + +#define RTC_INIT_CONFIG_DEFAULT() { \ + .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \ + .rtc_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .rtc_wait_cycles = OTHER_BLOCKS_WAIT, \ + .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \ + .rtc_mem_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .rtc_mem_wait_cycles = OTHER_BLOCKS_WAIT, \ +} + +void rtc_clk_divider_set(uint32_t div); + +void rtc_clk_8m_divider_set(uint32_t div); + /** * Initialize clocks and set CPU frequency * @@ -224,8 +369,12 @@ bool rtc_clk_8md256_enabled(void); * @param sdm2 frequency adjustment parameter, 0..63 * @param o_div frequency divider, 0..31 */ -void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, - uint32_t sdm2, uint32_t o_div); +void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div); + +/** + * @brief Set XTAL wait cycles by RTC slow clock's period + */ +void rtc_clk_set_xtal_wait(void); /** * @brief Select source for RTC_SLOW_CLK @@ -322,7 +471,7 @@ uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq); * @param[out] out_val output, rtc_cpu_freq_t value corresponding to the frequency * @return true if the given frequency value matches one of enum values */ -bool rtc_clk_cpu_freq_from_mhz(int cpu_freq_mhz, rtc_cpu_freq_t *out_val); + bool rtc_clk_cpu_freq_from_mhz(int cpu_freq_mhz, rtc_cpu_freq_t* out_val); /** * @brief Store new APB frequency value into RTC_APB_FREQ_REG @@ -344,7 +493,7 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq); */ uint32_t rtc_clk_apb_freq_get(void); -#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal +uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); /** * @brief Measure RTC slow clock's period, based on main XTAL frequency @@ -401,6 +550,10 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); */ uint64_t rtc_time_get(void); +uint64_t rtc_light_slp_time_get(void); + +uint64_t rtc_deep_slp_time_get(void); + /** * @brief Busy loop until next RTC_SLOW_CLK cycle * @@ -410,27 +563,53 @@ uint64_t rtc_time_get(void); */ void rtc_clk_wait_for_slow_cycle(void); +/** + * @brief Power down flags for rtc_sleep_pd function + */ +typedef struct { + uint32_t dig_fpu : 1; //!< Set to 1 to power down digital part in sleep + uint32_t rtc_fpu : 1; //!< Set to 1 to power down RTC memories in sleep + uint32_t cpu_fpu : 1; //!< Set to 1 to power down digital memories and CPU in sleep + uint32_t i2s_fpu : 1; //!< Set to 1 to power down I2S in sleep + uint32_t bb_fpu : 1; //!< Set to 1 to power down WiFi in sleep + uint32_t nrx_fpu : 1; //!< Set to 1 to power down WiFi in sleep + uint32_t fe_fpu : 1; //!< Set to 1 to power down WiFi in sleep +} rtc_sleep_pd_config_t; + +/** + * Initializer for rtc_sleep_pd_config_t which sets all flags to the same value + */ +#define RTC_SLEEP_PD_CONFIG_ALL(val) {\ + .dig_fpu = (val), \ + .rtc_fpu = (val), \ + .cpu_fpu = (val), \ + .i2s_fpu = (val), \ + .bb_fpu = (val), \ + .nrx_fpu = (val), \ + .fe_fpu = (val), \ +} + +void rtc_sleep_pd(rtc_sleep_pd_config_t cfg); + /** * @brief sleep configuration for rtc_sleep_init function */ typedef struct { uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory) - uint32_t rtc_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (RTC memory) uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used) uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals uint32_t wifi_pd_en : 1; //!< power down WiFi - uint32_t rom_mem_pd_en : 1; //!< power down main RAM and ROM uint32_t deep_slp : 1; //!< power down digital domain uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode - uint32_t lslp_meminf_pd : 1; //!< remove all peripheral force power up flags uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator - uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep + uint32_t deep_slp_reject : 1; + uint32_t light_slp_reject : 1; } rtc_sleep_config_t; /** @@ -443,22 +622,20 @@ typedef struct { */ #define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_fpu = 0, \ .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .wifi_pd_en = 0, \ - .rom_mem_pd_en = 0, \ + .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \ .dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90, \ .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90, \ - .lslp_meminf_pd = 1, \ + .rtc_dbias_slp = RTC_CNTL_DBIAS_1V00, \ .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1 \ + .deep_slp_reject = 1, \ + .light_slp_reject = 1 \ }; #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) @@ -467,7 +644,7 @@ typedef struct { #define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory #define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU #define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator -#define RTC_SLEEP_PD_XTAL BIT(6) //!< Power down main XTAL +#define RTC_SLEEP_PD_WIFI BIT(6) /** * @brief Prepare the chip to enter sleep mode @@ -504,6 +681,10 @@ void rtc_sleep_set_wakeup_time(uint64_t t); #define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup #define RTC_ULP_TRIG_EN BIT(9) //!< ULP wakeup #define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only) +#define RTC_COCPU_TRIG_EN BIT(11) +#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12) +#define RTC_COCPU_TRAP_TRIG_EN BIT(13) +#define RTC_USB_TRIG_EN BIT(14) /** * @brief Enter deep or light sleep mode @@ -530,7 +711,7 @@ void rtc_sleep_set_wakeup_time(uint64_t t); * an external host is communicating via SDIO slave * @return non-zero if sleep was rejected by hardware */ -uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); +uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu); /** * RTC power and clock control initialization settings @@ -542,6 +723,9 @@ typedef struct { uint32_t clkctl_init : 1; //!< Perform clock control related initialization uint32_t pwrctl_init : 1; //!< Perform power control related initialization uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST + uint32_t xtal_fpu : 1; + uint32_t bbpll_fpu : 1; + uint32_t cpu_waiti_clk_gate : 1; } rtc_config_t; /** @@ -556,7 +740,10 @@ typedef struct { .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ .clkctl_init = 1, \ .pwrctl_init = 1, \ - .rtc_dboost_fpd = 1 \ + .rtc_dboost_fpd = 1, \ + .xtal_fpu = 0, \ + .bbpll_fpu = 0, \ + .cpu_waiti_clk_gate = 1\ } /** @@ -565,9 +752,6 @@ typedef struct { */ void rtc_init(rtc_config_t cfg); -#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO -#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO - /** * Structure describing vddsdio configuration */ diff --git a/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h b/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h index de886c8ec3..ac336c8b20 100644 --- a/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h @@ -275,21 +275,18 @@ extern "C" { #define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) #define RTC_CNTL_PLL_BUF_WAIT_V 0xFF #define RTC_CNTL_PLL_BUF_WAIT_S 24 -#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ /*description: XTAL wait cycles in slow_clk_rtc*/ #define RTC_CNTL_XTL_BUF_WAIT 0x000003FF #define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) #define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF #define RTC_CNTL_XTL_BUF_WAIT_S 14 -#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ /*description: CK8M wait cycles in slow_clk_rtc*/ #define RTC_CNTL_CK8M_WAIT 0x000000FF #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) #define RTC_CNTL_CK8M_WAIT_V 0xFF #define RTC_CNTL_CK8M_WAIT_S 6 -#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ /*description: CPU stall wait cycles in fast_clk_rtc*/ #define RTC_CNTL_CPU_STALL_WAIT 0x0000001F @@ -1568,13 +1565,6 @@ extern "C" { #define RTC_CNTL_DIG_DBIAS_1V15 6 #define RTC_CNTL_DIG_DBIAS_1V20 7 -/* The value of 1V00 can be adjusted between 0~3*/ -#define RTC_CNTL_DBIAS_1V00 0 -#define RTC_CNTL_DBIAS_1V05 4 -#define RTC_CNTL_DBIAS_1V10 5 -#define RTC_CNTL_DBIAS_1V15 6 -#define RTC_CNTL_DBIAS_1V20 7 - /* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ /*description: RTC_DBIAS during sleep*/ #define RTC_CNTL_DBIAS_SLP 0x00000007 @@ -1587,7 +1577,6 @@ extern "C" { #define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) #define RTC_CNTL_SCK_DCAP_V 0xFF #define RTC_CNTL_SCK_DCAP_S 14 -#define RTC_CNTL_SCK_DCAP_DEFAULT 255 /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ /*description: DIG_REG_DBIAS during wakeup*/ #define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 diff --git a/components/soc/esp32s2beta/include/soc/sens_reg.h b/components/soc/esp32s2beta/include/soc/sens_reg.h index d3cdf38830..9b9052b3ab 100644 --- a/components/soc/esp32s2beta/include/soc/sens_reg.h +++ b/components/soc/esp32s2beta/include/soc/sens_reg.h @@ -1150,7 +1150,7 @@ extern "C" { #define SENS_TOUCH_PAD14_BASELINE_V 0x3FFFFF #define SENS_TOUCH_PAD14_BASELINE_S 0 -#define SENS_SAR_TOUCH_SLP_STATUS_REG (DR_REG_SENS_BASE + 0x0114) +#define SENS_SAR_TOUCH_STATUS15_REG (DR_REG_SENS_BASE + 0x0114) /* SENS_TOUCH_SLP_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ /*description: */ #define SENS_TOUCH_SLP_DEBOUNCE 0x00000007 @@ -1164,7 +1164,7 @@ extern "C" { #define SENS_TOUCH_SLP_BASELINE_V 0x3FFFFF #define SENS_TOUCH_SLP_BASELINE_S 0 -#define SENS_SAR_TOUCH_APPR_STATUS_REG (DR_REG_SENS_BASE + 0x0118) +#define SENS_SAR_TOUCH_STATUS16_REG (DR_REG_SENS_BASE + 0x0118) /* SENS_TOUCH_SLP_APPROACH_CNT : RO ;bitpos:[31:24] ;default: 8'd0 ; */ /*description: */ #define SENS_TOUCH_SLP_APPROACH_CNT 0x000000FF diff --git a/components/soc/esp32s2beta/include/soc/sens_struct.h b/components/soc/esp32s2beta/include/soc/sens_struct.h index 080c580598..98808fc618 100644 --- a/components/soc/esp32s2beta/include/soc/sens_struct.h +++ b/components/soc/esp32s2beta/include/soc/sens_struct.h @@ -277,14 +277,6 @@ typedef volatile struct { }; uint32_t val; } sar_touch_status[14]; - union { - struct { - uint32_t touch_slp_baseline:22; - uint32_t reserved22: 7; - uint32_t touch_slp_debounce: 3; - }; - uint32_t val; - } sar_touch_slp_status; union { struct { uint32_t touch_approach_pad2_cnt: 8; @@ -293,7 +285,7 @@ typedef volatile struct { uint32_t touch_slp_approach_cnt: 8; }; uint32_t val; - } sar_touch_appr_status; + } sar_touch_status16; union { struct { uint32_t sw_fstep: 16; /*frequency step for CW generator*/ diff --git a/components/soc/esp32s2beta/include/soc/soc.h b/components/soc/esp32s2beta/include/soc/soc.h index 353c66f57a..a3badcaadc 100644 --- a/components/soc/esp32s2beta/include/soc/soc.h +++ b/components/soc/esp32s2beta/include/soc/soc.h @@ -232,7 +232,7 @@ #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM #define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM #define CPU_CLK_FREQ APB_CLK_FREQ -#define APB_CLK_FREQ ( 40*1000000 ) //unit: Hz +#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz #define REF_CLK_FREQ ( 1000000 ) #define UART_CLK_FREQ APB_CLK_FREQ #define WDT_CLK_FREQ APB_CLK_FREQ diff --git a/components/soc/esp32s2beta/rtc_clk.c b/components/soc/esp32s2beta/rtc_clk.c index 1f43b391ef..a74cf81ece 100644 --- a/components/soc/esp32s2beta/rtc_clk.c +++ b/components/soc/esp32s2beta/rtc_clk.c @@ -27,76 +27,14 @@ #include "soc/sens_reg.h" #include "soc/dport_reg.h" #include "soc/efuse_reg.h" -#include "soc/apb_ctrl_reg.h" +#include "soc/syscon_reg.h" #include "i2c_rtc_clk.h" #include "soc_log.h" +#include "sdkconfig.h" #include "xtensa/core-macros.h" -#define MHZ (1000000) - -/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */ -#define RTC_FAST_CLK_FREQ_8M 8500000 -#define RTC_SLOW_CLK_FREQ_150K 150000 -#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256) -#define RTC_SLOW_CLK_FREQ_32K 32768 - static const char *TAG = "rtc_clk"; -/* Various constants related to the analog internals of the chip. - * Defined here because they don't have any use outside of this file. - */ - -#define BBPLL_ENDIV5_VAL_320M 0x43 -#define BBPLL_BBADC_DSMP_VAL_320M 0x84 -#define BBPLL_ENDIV5_VAL_480M 0xc3 -#define BBPLL_BBADC_DSMP_VAL_480M 0x74 - -#define APLL_SDM_STOP_VAL_1 0x09 -#define APLL_SDM_STOP_VAL_2_REV0 0x69 -#define APLL_SDM_STOP_VAL_2_REV1 0x49 - -#define APLL_CAL_DELAY_1 0x0f -#define APLL_CAL_DELAY_2 0x3f -#define APLL_CAL_DELAY_3 0x1f - -#define XTAL_32K_DAC_VAL 1 -#define XTAL_32K_DRES_VAL 3 -#define XTAL_32K_DBIAS_VAL 0 - -#define XTAL_32K_BOOTSTRAP_DAC_VAL 3 -#define XTAL_32K_BOOTSTRAP_DRES_VAL 3 -#define XTAL_32K_BOOTSTRAP_DBIAS_VAL 0 -#define XTAL_32K_BOOTSTRAP_TIME_US 7 - -/* Delays for various clock sources to be enabled/switched. - * All values are in microseconds. - * TODO: some of these are excessive, and should be reduced. - */ -#define DELAY_PLL_DBIAS_RAISE 3 -#define DELAY_PLL_ENABLE_WITH_150K 80 -#define DELAY_PLL_ENABLE_WITH_32K 160 -#define DELAY_FAST_CLK_SWITCH 3 -#define DELAY_SLOW_CLK_SWITCH 300 -#define DELAY_8M_ENABLE 50 - -/* Number of 8M/256 clock cycles to use for XTAL frequency estimation. - * 10 cycles will take approximately 300 microseconds. - */ -#define XTAL_FREQ_EST_CYCLES 10 - -/* Core voltage needs to be increased in two cases: - * 1. running at 240 MHz - * 2. running with 80MHz Flash frequency - */ -#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M -#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 -#else -#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 -#endif -#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V10 -#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 -#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 - /* PLL currently enabled, if any */ typedef enum { RTC_PLL_NONE, @@ -108,58 +46,42 @@ static rtc_pll_t s_cur_pll = RTC_PLL_NONE; /* Current CPU frequency; saved in a variable for faster freq. switching */ static rtc_cpu_freq_t s_cur_freq = RTC_CPU_FREQ_XTAL; - -static void rtc_clk_32k_enable_internal(int dac, int dres, int dbias) +void rtc_clk_32k_enable_internal(x32k_config_t cfg) { - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DAC_XTAL_32K, dac); - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DRES_XTAL_32K, dres); - //FIXME: RTC_CNTL_DBIAS_XTAL_32K removed, do not know how to config at the moment - //REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DBIAS_XTAL_32K, dbias); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DAC_XTAL_32K, cfg.dac); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DRES_XTAL_32K, cfg.dres); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DGM_XTAL_32K, cfg.dgm); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DBUF_XTAL_32K, cfg.dbuf); SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K); } void rtc_clk_32k_enable(bool enable) { if (enable) { - rtc_clk_32k_enable_internal(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL); + x32k_config_t cfg = X32K_CONFIG_DEFAULT(); + rtc_clk_32k_enable_internal(cfg); } else { + SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE); CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K); } } -/* Helping external 32kHz crystal to start up. - * External crystal connected to outputs GPIO32 GPIO33. - * Forms N pulses with a frequency of about 32KHz on the outputs of the crystal. - */ void rtc_clk_32k_bootstrap(uint32_t cycle) { - if (cycle) { - const uint32_t pin_32 = 32; - const uint32_t pin_33 = 33; - const uint32_t mask_32 = (1 << (pin_32 - 32)); - const uint32_t mask_33 = (1 << (pin_33 - 32)); - - gpio_pad_select_gpio(pin_32); - gpio_pad_select_gpio(pin_33); - gpio_output_set_high(mask_32, mask_33, mask_32 | mask_33, 0); - - const uint32_t delay_us = (1000000 / RTC_SLOW_CLK_FREQ_32K / 2); - while (cycle) { - gpio_output_set_high(mask_32, mask_33, mask_32 | mask_33, 0); - ets_delay_us(delay_us); - gpio_output_set_high(mask_33, mask_32, mask_32 | mask_33, 0); - ets_delay_us(delay_us); - cycle--; - } - gpio_output_set_high(0, 0, 0, mask_32 | mask_33); // disable pins - } - - CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K); } bool rtc_clk_32k_enabled(void) { - return GET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K) != 0; + uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG); + /* If xtal xpd is controlled by software */ + bool xtal_xpd_sw = (xtal_conf & RTC_CNTL_XTAL32K_XPD_FORCE) >> RTC_CNTL_XTAL32K_XPD_FORCE_S; + /* If xtal xpd software control is on */ + bool xtal_xpd_st = (xtal_conf & RTC_CNTL_XPD_XTAL_32K) >> RTC_CNTL_XPD_XTAL_32K_S; + if (xtal_xpd_sw & !xtal_xpd_st) { + return false; + } else { + return true; + } } void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) @@ -167,17 +89,20 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) if (clk_8m_en) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); /* no need to wait once enabled by software */ - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1); - if (d256_en) { - CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); - } else { - SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); - } + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT); ets_delay_us(DELAY_8M_ENABLE); } else { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT); } + /* d256 should be independent configured with 8M + * Maybe we can split this function into 8m and dmd256 + */ + if (d256_en) { + CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); + } else { + SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); + } } bool rtc_clk_8m_enabled(void) @@ -195,13 +120,30 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1); REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0); + /* BIAS I2C not exist any more, but not sure how to get the same effect yet... + * if (!enable && + * REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL) != DPORT_SOC_CLK_SEL_PLL) { + * REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); + * } else { + * REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); + * } + */ + if (enable) { + /* no need to differentiate ECO chip any more uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1; + uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0); + if (is_rev0) { + sdm0 = 0; + sdm1 = 0; + sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0; + } + */ I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2); I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0); I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1); I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1); - I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2); + I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_2_REV1); I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div); /* calibration */ @@ -217,13 +159,44 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm } } +void rtc_clk_set_xtal_wait(void) +{ + /* + the `xtal_wait` time need 1ms, so we need calibrate slow clk period, + and `RTC_CNTL_XTL_BUF_WAIT` depend on it. + */ + rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); + rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL; + rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256; + rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; + if (slow_clk_freq == (rtc_slow_freq_x32k)) { + cal_clk = RTC_CAL_32K_XTAL; + } else if (slow_clk_freq == rtc_slow_freq_8MD256) { + cal_clk = RTC_CAL_8MD256; + } + uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 2000); + uint32_t xtal_wait_1ms = 100; + if (slow_clk_period) { + xtal_wait_1ms = (1000 << RTC_CLK_CAL_FRACT) / slow_clk_period; + } + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, xtal_wait_1ms); +} + void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq); + /* Why we need to connect this clock to digital? + * Or maybe this clock should be connected to digital when xtal 32k clock is enabled instead? + */ REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); + /* The clk_8m_d256 will be closed when rtc_state in SLEEP, + so if the slow_clk is 8md256, clk_8m must be force power on + */ + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0); + rtc_clk_set_xtal_wait(); ets_delay_us(DELAY_SLOW_CLK_SWITCH); } @@ -253,9 +226,18 @@ rtc_fast_freq_t rtc_clk_fast_freq_get(void) return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); } -void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_cpu_freq_t cpu_freq) +/* In 7.2.2, cpu can run at 80M/160M/240M if PLL is 480M + * pll can run 80M/160M is PLL is 320M + */ +#define DR_REG_I2C_MST_BASE 0x3f40E000 +#define I2C_MST_ANA_STATE_REG (DR_REG_I2C_MST_BASE + 0x040) +#define I2C_MST_BBPLL_CAL_END (BIT(24)) +#define I2C_MST_BBPLL_CAL_END_M (BIT(24)) +#define I2C_MST_BBPLL_CAL_END_V 0x1 +#define I2C_MST_BBPLL_CAL_END_S 24 + +void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_pll_t pll_freq) { -#if !CONFIG_IDF_ENV_FPGA uint8_t div_ref; uint8_t div7_0; uint8_t dr1; @@ -263,98 +245,70 @@ void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_cpu_freq_t cpu_freq) uint8_t dchgp; uint8_t dcur; - if (cpu_freq != RTC_CPU_FREQ_240M) { - /* Configure 320M PLL */ - switch (xtal_freq) { - case RTC_XTAL_FREQ_40M: - div_ref = 0; - div7_0 = 4; - dr1 = 0; - dr3 = 0; - dchgp = 5; - dcur = 4; - break; - case RTC_XTAL_FREQ_26M: - div_ref = 12; - div7_0 = 156; - dr1 = 3; - dr3 = 3; - dchgp = 4; - dcur = 1; - break; - case RTC_XTAL_FREQ_24M: - div_ref = 11; - div7_0 = 156; - dr1 = 3; - dr3 = 3; - dchgp = 4; - dcur = 1; - break; - default: - div_ref = 0; - div7_0 = 4; - dr1 = 0; - dr3 = 0; - dchgp = 5; - dcur = 4; - break; - } - I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0); - I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_DIV_ADC, 2); + assert(xtal_freq == RTC_XTAL_FREQ_40M); + + if (pll_freq == RTC_PLL_480M) { + /* Raise the voltage, if needed */ + /* move to 240M logic */ + //REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M); + /* Set this register to let digital know pll is 480M */ + SET_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); + /* Configure 480M PLL */ + div_ref = 0; + div7_0 = 8; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dcur = 4; + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B); } else { /* Raise the voltage */ - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V25); - ets_delay_us(DELAY_PLL_DBIAS_RAISE); + //REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M); + //ets_delay_us(DELAY_PLL_DBIAS_RAISE); + CLEAR_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); /* Configure 480M PLL */ - switch (xtal_freq) { - case RTC_XTAL_FREQ_40M: - div_ref = 0; - div7_0 = 8; - dr1 = 0; - dr3 = 0; - dchgp = 5; - dcur = 5; - break; - case RTC_XTAL_FREQ_26M: - div_ref = 12; - div7_0 = 236; - dr1 = 3; - dr3 = 3; - dchgp = 0; - dcur = 2; - break; - case RTC_XTAL_FREQ_24M: - div_ref = 11; - div7_0 = 236; - dr1 = 3; - dr3 = 3; - dchgp = 0; - dcur = 2; - break; - default: - div_ref = 0; - div7_0 = 8; - dr1 = 0; - dr3 = 0; - dchgp = 5; - dcur = 5; - break; - } - I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 1); - I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_DIV_ADC, 2); + div_ref = 0; + div7_0 = 4; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dcur = 5; + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69); } - - I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, dcur); + uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref); + uint8_t i2c_bbpll_div_7_0 = div7_0; + uint8_t i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur; + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0); I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1); I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); - I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCHGP, dchgp); - I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, div7_0); - I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, div_ref); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); - uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ? - DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K; - ets_delay_us(delay_pll_en); -#endif + // Enable calibration by software + I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_ENX_CAP, 1); + for (int ext_cap = 0; ext_cap < 16; ext_cap++) { + uint8_t cal_result; + I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, ext_cap); + cal_result = I2C_READREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OR_CAL_CAP); + if (cal_result == 0) { + break; + } + if (ext_cap == 15) { + SOC_LOGE(TAG, "BBPLL SOFTWARE CAL FAIL"); + } + } + + /* this delay is replaced by polling Pll calibration end flag + * uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ? + * DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K; + * ets_delay_us(delay_pll_en); + */ + /* this calibration didn't work on 480M + need to test exact delay according to 320M + while (!GET_PERI_REG_MASK(I2C_MST_ANA_STATE_REG, I2C_MST_BBPLL_CAL_END)) { + ets_delay_us(1); + } + */ } /** @@ -365,12 +319,14 @@ static void rtc_clk_cpu_freq_to_xtal(void) rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); ets_update_cpu_frequency(xtal_freq); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); - REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0); - REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_SOC_CLK_SEL, APB_CTRL_SOC_CLK_SEL_XTL); - DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); // clear DPORT_CPUPERIOD_SEL + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0); + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, 0); + /* Why we need to do this ? */ + //DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); // clear DPORT_CPUPERIOD_SEL rtc_clk_apb_freq_update(xtal_freq * MHZ); s_cur_freq = RTC_CPU_FREQ_XTAL; + s_cur_pll = RTC_PLL_NONE; } /** @@ -383,31 +339,29 @@ static void rtc_clk_cpu_freq_to_xtal(void) static void rtc_clk_cpu_freq_to_pll(rtc_cpu_freq_t cpu_freq) { int freq = 0; - if (s_cur_pll == RTC_PLL_NONE || - (cpu_freq == RTC_CPU_FREQ_240M && s_cur_pll == RTC_PLL_320M) || - (cpu_freq != RTC_CPU_FREQ_240M && s_cur_pll == RTC_PLL_480M)) { - /* need to switch PLLs, fall back to full implementation */ + if ((s_cur_pll == RTC_PLL_NONE) || ((s_cur_pll == RTC_PLL_320M) && (cpu_freq == RTC_CPU_FREQ_240M))) { + /* + * if switch from non-pll or switch from PLL 320M to 480M + * need to switch PLLs, fall back to full implementation + */ rtc_clk_cpu_freq_set(cpu_freq); return; } - if (cpu_freq == RTC_CPU_FREQ_80M) { + if ((cpu_freq == RTC_CPU_FREQ_80M) || (cpu_freq == RTC_CPU_320M_80M)) { REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M); - DPORT_REG_CLR_BIT(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); freq = 80; - } else if (cpu_freq == RTC_CPU_FREQ_160M) { + } else if ((cpu_freq == RTC_CPU_FREQ_160M) || (cpu_freq == RTC_CPU_320M_160M)) { REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M); - DPORT_REG_CLR_BIT(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 1); freq = 160; } else if (cpu_freq == RTC_CPU_FREQ_240M) { REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M); - DPORT_REG_SET_BIT(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 2); freq = 240; } - REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_SOC_CLK_SEL, APB_CTRL_SOC_CLK_SEL_PLL); + // REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL); rtc_clk_apb_freq_update(80 * MHZ); ets_update_cpu_frequency(freq); s_cur_freq = cpu_freq; @@ -424,7 +378,8 @@ void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq) rtc_clk_cpu_freq_to_xtal(); } else if (cpu_freq > RTC_CPU_FREQ_XTAL) { rtc_clk_cpu_freq_to_pll(cpu_freq); - rtc_clk_wait_for_slow_cycle(); + /* Not neccessary any more */ + //rtc_clk_wait_for_slow_cycle(); } } @@ -433,54 +388,71 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); /* Switch CPU to XTAL frequency first */ REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); - REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_SOC_CLK_SEL, APB_CTRL_SOC_CLK_SEL_XTL); - REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0); + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, 0); + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0); ets_update_cpu_frequency(xtal_freq); - /* Frequency switch is synchronized to SLOW_CLK cycle. Wait until the switch * is complete before disabling the PLL. */ - rtc_clk_wait_for_slow_cycle(); + /* register SOC_CLK_SEL is moved to APB domain, so this delay is not neccessary any more */ + //rtc_clk_wait_for_slow_cycle(); - DPORT_REG_CLR_BIT(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0); + + /* BBPLL force power down won't affect force power up setting */ SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); s_cur_pll = RTC_PLL_NONE; rtc_clk_apb_freq_update(xtal_freq * MHZ); + /* is APLL under force power down? */ + /* may need equivalent function + uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); + + * if (apll_fpd) { + * SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); + * } + */ + /* now switch to the desired frequency */ if (cpu_freq == RTC_CPU_FREQ_XTAL) { /* already at XTAL, nothing to do */ } else if (cpu_freq == RTC_CPU_FREQ_2M) { /* set up divider to produce 2MHz from XTAL */ - REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, (xtal_freq / 2) - 1); + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, (xtal_freq / 2) - 1); ets_update_cpu_frequency(2); rtc_clk_apb_freq_update(2 * MHZ); /* lower the voltage */ REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M); } else { /* use PLL as clock source */ - rtc_clk_bbpll_set(xtal_freq, cpu_freq); - if (cpu_freq == RTC_CPU_FREQ_80M) { - DPORT_REG_CLR_BIT(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); - DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0); - ets_update_cpu_frequency(80); + CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, + RTC_CNTL_BB_I2C_FORCE_PD | + RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); + if (cpu_freq > RTC_CPU_FREQ_2M) { + rtc_clk_bbpll_set(xtal_freq, RTC_PLL_320M); s_cur_pll = RTC_PLL_320M; - } else if (cpu_freq == RTC_CPU_FREQ_160M) { - DPORT_REG_CLR_BIT(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); - DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1); - ets_update_cpu_frequency(160); - s_cur_pll = RTC_PLL_320M; - } else if (cpu_freq == RTC_CPU_FREQ_240M) { - DPORT_REG_SET_BIT(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); - DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2); - ets_update_cpu_frequency(240); + } else { + rtc_clk_bbpll_set(xtal_freq, RTC_PLL_480M); s_cur_pll = RTC_PLL_480M; } - REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_SOC_CLK_SEL, APB_CTRL_SOC_CLK_SEL_PLL); - rtc_clk_wait_for_slow_cycle(); + + if ((cpu_freq == RTC_CPU_FREQ_80M) || (cpu_freq == RTC_CPU_320M_80M)) { + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M); + DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0); + ets_update_cpu_frequency(80); + } else if ((cpu_freq == RTC_CPU_FREQ_160M) || (cpu_freq == RTC_CPU_320M_160M)) { + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M); + DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1); + ets_update_cpu_frequency(160); + } else if (cpu_freq == RTC_CPU_FREQ_240M) { + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M); + DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2); + ets_update_cpu_frequency(240); + } + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, 1); + //rtc_clk_wait_for_slow_cycle(); rtc_clk_apb_freq_update(80 * MHZ); } s_cur_freq = cpu_freq; @@ -488,12 +460,14 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) rtc_cpu_freq_t rtc_clk_cpu_freq_get(void) { - uint32_t soc_clk_sel = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_SOC_CLK_SEL); + uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL); switch (soc_clk_sel) { - case APB_CTRL_SOC_CLK_SEL_XTL: { - uint32_t pre_div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT); + case 0: { + uint32_t pre_div = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT); if (pre_div == 0) { return RTC_CPU_FREQ_XTAL; + } else if (pre_div == 1) { + return RTC_CPU_FREQ_XTAL_DIV2; } else if (pre_div == rtc_clk_xtal_freq_get() / 2 - 1) { return RTC_CPU_FREQ_2M; } else { @@ -501,12 +475,21 @@ rtc_cpu_freq_t rtc_clk_cpu_freq_get(void) } break; } - case APB_CTRL_SOC_CLK_SEL_PLL: { + case 1: { uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); + uint32_t pllfreq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); if (cpuperiod_sel == 0) { - return RTC_CPU_FREQ_80M; + if (pllfreq_sel == 1) { + return RTC_CPU_FREQ_80M; + } else { + return RTC_CPU_320M_80M; + } } else if (cpuperiod_sel == 1) { - return RTC_CPU_FREQ_160M; + if (pllfreq_sel == 1) { + return RTC_CPU_FREQ_160M; + } else { + return RTC_CPU_320M_160M; + } } else if (cpuperiod_sel == 2) { return RTC_CPU_FREQ_240M; } else { @@ -514,12 +497,12 @@ rtc_cpu_freq_t rtc_clk_cpu_freq_get(void) } break; } - case APB_CTRL_SOC_CLK_SEL_APLL: - case APB_CTRL_SOC_CLK_SEL_8M: + case 2: + case 3: default: assert(false && "unsupported frequency"); } - return APB_CTRL_SOC_CLK_SEL_XTL; + return 0; } uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq) @@ -527,6 +510,8 @@ uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq) switch (cpu_freq) { case RTC_CPU_FREQ_XTAL: return ((uint32_t) rtc_clk_xtal_freq_get()) * MHZ; + case RTC_CPU_FREQ_XTAL_DIV2: + return ((uint32_t) rtc_clk_xtal_freq_get()) / 2 * MHZ; case RTC_CPU_FREQ_2M: return 2 * MHZ; case RTC_CPU_FREQ_80M: @@ -535,6 +520,10 @@ uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq) return 160 * MHZ; case RTC_CPU_FREQ_240M: return 240 * MHZ; + case RTC_CPU_320M_80M: + return 80 * MHZ; + case RTC_CPU_320M_160M: + return 160 * MHZ; default: assert(false && "invalid rtc_cpu_freq_t value"); return 0; @@ -551,6 +540,8 @@ bool rtc_clk_cpu_freq_from_mhz(int mhz, rtc_cpu_freq_t *out_val) *out_val = RTC_CPU_FREQ_80M; } else if (mhz == (int) rtc_clk_xtal_freq_get()) { *out_val = RTC_CPU_FREQ_XTAL; + } else if (mhz == (int) rtc_clk_xtal_freq_get() / 2) { + *out_val = RTC_CPU_FREQ_XTAL_DIV2; } else if (mhz == 2) { *out_val = RTC_CPU_FREQ_2M; } else { @@ -582,7 +573,6 @@ static uint32_t clk_val_to_reg_val(uint32_t val) rtc_xtal_freq_t rtc_clk_xtal_freq_get(void) { - /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */ uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG); if (!clk_val_is_valid(xtal_freq_reg)) { SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg); @@ -596,42 +586,6 @@ void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq) WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq)); } -static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void) -{ - /* Enable 8M/256 clock if needed */ - const bool clk_8m_enabled = rtc_clk_8m_enabled(); - const bool clk_8md256_enabled = rtc_clk_8md256_enabled(); - if (!clk_8md256_enabled) { - rtc_clk_8m_enable(true, true); - } - - uint64_t cal_val = rtc_clk_cal_ratio(RTC_CAL_8MD256, XTAL_FREQ_EST_CYCLES); - /* cal_val contains period of 8M/256 clock in XTAL clock cycles - * (shifted by RTC_CLK_CAL_FRACT bits). - * Xtal frequency will be (cal_val * 8M / 256) / 2^19 - */ - uint32_t freq_mhz = (cal_val * RTC_FAST_CLK_FREQ_APPROX / MHZ / 256 ) >> RTC_CLK_CAL_FRACT; - /* Guess the XTAL type. For now, only 40 and 26MHz are supported. - */ - switch (freq_mhz) { - case 21 ... 31: - return RTC_XTAL_FREQ_26M; - case 32 ... 33: - SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz); - return RTC_XTAL_FREQ_26M; - case 34 ... 35: - SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz); - return RTC_XTAL_FREQ_40M; - case 36 ... 45: - return RTC_XTAL_FREQ_40M; - default: - SOC_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz); - return RTC_XTAL_FREQ_AUTO; - } - /* Restore 8M and 8md256 clocks to original state */ - rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled); -} - void rtc_clk_apb_freq_update(uint32_t apb_freq) { WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12)); @@ -646,28 +600,36 @@ uint32_t rtc_clk_apb_freq_get(void) return freq_hz - remainder; } +void rtc_clk_divider_set(uint32_t div) +{ + CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); + REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, div); + SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); +} + +void rtc_clk_8m_divider_set(uint32_t div) +{ + CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, div); + SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); +} void rtc_clk_init(rtc_clk_config_t cfg) { rtc_cpu_freq_t cpu_source_before = rtc_clk_cpu_freq_get(); - /* If we get a TG WDT system reset while running at 240MHz, * DPORT_CPUPERIOD_SEL register will be reset to 0 resulting in 120MHz * APB and CPU frequencies after reset. This will cause issues with XTAL * frequency estimation, so we switch to XTAL frequency first. * - * Ideally we would only do this if APB_CTRL_SOC_CLK_SEL == PLL and + * Ideally we would only do this if SYSCON_SOC_CLK_SEL == PLL and * PLL is configured for 480M, but it takes less time to switch to 40M and * run the following code than querying the PLL does. */ - if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, APB_CTRL_SOC_CLK_SEL) == APB_CTRL_SOC_CLK_SEL_PLL) { + if (REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL) == 1) { rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL); } - CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); - REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, 0); - SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); - /* Set tuning parameters for 8M and 150k clocks. * Note: this doesn't attempt to set the clocks to precise frequencies. * Instead, we calibrate these clocks against XTAL frequency later, when necessary. @@ -679,37 +641,16 @@ void rtc_clk_init(rtc_clk_config_t cfg) REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); + /* Configure 150k clock division */ + rtc_clk_divider_set(cfg.clk_rtc_clk_div); /* Configure 8M clock division */ - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, cfg.clk_8m_div); + rtc_clk_8m_divider_set(cfg.clk_8m_clk_div); /* Enable the internal bus used to configure PLLs */ SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S); CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M); rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; - if (xtal_freq == RTC_XTAL_FREQ_AUTO) { - if (clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) { - /* XTAL frequency has already been set, use existing value */ - xtal_freq = rtc_clk_xtal_freq_get(); - } else { - /* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */ - xtal_freq = rtc_clk_xtal_freq_estimate(); - if (xtal_freq == RTC_XTAL_FREQ_AUTO) { - SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz"); - xtal_freq = RTC_XTAL_FREQ_26M; - } - } - } else if (!clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) { - /* Exact frequency was set in sdkconfig, but still warn if autodetected - * frequency is different. If autodetection failed, worst case we get a - * bit of garbage output. - */ - rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate(); - if (est_xtal_freq != xtal_freq) { - SOC_LOGW(TAG, "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting (%dMHz). Detected %d MHz.", - xtal_freq, est_xtal_freq); - } - } uart_tx_wait_idle(0); rtc_clk_xtal_freq_update(xtal_freq); rtc_clk_apb_freq_update(xtal_freq * MHZ); diff --git a/components/soc/esp32s2beta/rtc_init.c b/components/soc/esp32s2beta/rtc_init.c index 0d129ec1ac..b2277f335f 100644 --- a/components/soc/esp32s2beta/rtc_init.c +++ b/components/soc/esp32s2beta/rtc_init.c @@ -13,7 +13,6 @@ // limitations under the License. #include - #include "soc/soc.h" #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" @@ -21,33 +20,11 @@ #include "soc/efuse_periph.h" #include "soc/gpio_reg.h" #include "soc/spi_mem_reg.h" +#include "soc/extmem_reg.h" #include "i2c_rtc_clk.h" -/* Various delays to be programmed into power control state machines */ -#define RTC_CNTL_XTL_BUF_WAIT_SLP 2 -#define RTC_CNTL_PLL_BUF_WAIT_SLP 2 -#define RTC_CNTL_CK8M_WAIT_SLP 4 -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - -#define ROM_RAM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define ROM_RAM_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define WIFI_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define WIFI_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define RTC_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define DG_WRAP_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define DG_WRAP_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_MEM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define RTC_MEM_WAIT_CYCLES OTHER_BLOCKS_WAIT - void rtc_init(rtc_config_t cfg) { -#if !CONFIG_IDF_ENV_FPGA CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU); rtc_clk_set_xtal_wait(); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait); @@ -63,17 +40,18 @@ void rtc_init(rtc_config_t cfg) * REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_WAIT_TIMER, ROM_RAM_WAIT_CYCLES); */ // set wifi timer - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, WIFI_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, WIFI_WAIT_CYCLES); + rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT(); + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles); // set rtc peri timer - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, RTC_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, RTC_WAIT_CYCLES); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, rtc_init_cfg.rtc_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, rtc_init_cfg.rtc_wait_cycles); // set digital wrap timer - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, DG_WRAP_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, DG_WRAP_WAIT_CYCLES); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles); // set rtc memory timer - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, RTC_MEM_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, RTC_MEM_WAIT_CYCLES); + REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, rtc_init_cfg.rtc_mem_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, rtc_init_cfg.rtc_mem_wait_cycles); SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DEC_HEARTBEAT_WIDTH | RTC_CNTL_INC_HEARTBEAT_PERIOD); @@ -84,14 +62,14 @@ void rtc_init(rtc_config_t cfg) if (cfg.clkctl_init) { //clear CMMU clock force on - CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_MMU_POWER_CTRL_REG, DPORT_PRO_CACHE_MMU_MEM_FORCE_ON); + CLEAR_PERI_REG_MASK(EXTMEM_PRO_CACHE_MMU_POWER_CTRL_REG, EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON); //clear rom clock force on REG_SET_FIELD(DPORT_ROM_CTRL_0_REG, DPORT_ROM_FO, 0); //clear sram clock force on REG_SET_FIELD(DPORT_SRAM_CTRL_0_REG, DPORT_SRAM_FO, 0); //clear tag clock force on - CLEAR_PERI_REG_MASK(DPORT_PRO_DCACHE_TAG_POWER_CTRL_REG, DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON); - CLEAR_PERI_REG_MASK(DPORT_PRO_ICACHE_TAG_POWER_CTRL_REG, DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON); + CLEAR_PERI_REG_MASK(EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_REG, EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON); + CLEAR_PERI_REG_MASK(EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON); //clear register clock force on CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN); CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN); @@ -105,14 +83,6 @@ void rtc_init(rtc_config_t cfg) } else { SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU); } - // cancel BIAS force pu - // CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PU); - // CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP); - // bias follow 8M - // SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FOLW_8M); - // SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FOLW_8M); - SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_SLEEP_FOLW_8M); // CLEAR APLL close CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); @@ -128,7 +98,7 @@ void rtc_init(rtc_config_t cfg) SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); } //cancel RTC REG force PU - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PWC_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU); @@ -141,8 +111,12 @@ void rtc_init(rtc_config_t cfg) } else { CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD); } + //cancel sar i2c pd force + CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_SAR_I2C_FORCE_PD); //cancel digital pu force CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU); + //cannel i2c_reset_protect pd force + CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_I2C_RESET_POR_FORCE_PD); /* If this mask is enabled, all soc memories cannot enter power down mode */ /* We should control soc memory power down mode from RTC, so we will not touch this register any more */ @@ -168,18 +142,9 @@ void rtc_init(rtc_config_t cfg) } /*if DPORT_CPU_WAIT_MODE_FORCE_ON == 0 , the cpu clk will be closed when cpu enter WAITI mode*/ -#ifdef CONFIG_CHIP_IS_ESP32 - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_UNHOLD); - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_NOISO); -#endif CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO); -#ifdef CONFIG_CHIP_IS_ESP32 - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_AUTOHOLD_EN); - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN); -#endif } -#endif } rtc_vddsdio_config_t rtc_vddsdio_get_config(void) diff --git a/components/soc/esp32s2beta/rtc_sleep.c b/components/soc/esp32s2beta/rtc_sleep.c index fc70aad0a2..15fde3237e 100644 --- a/components/soc/esp32s2beta/rtc_sleep.c +++ b/components/soc/esp32s2beta/rtc_sleep.c @@ -27,112 +27,34 @@ #include "soc/rtc.h" #include "esp32s2beta/rom/ets_sys.h" -#define MHZ (1000000) - -/* Various delays to be programmed into power control state machines */ -#define RTC_CNTL_XTL_BUF_WAIT_SLP 2 -#define RTC_CNTL_PLL_BUF_WAIT_SLP 2 -#define RTC_CNTL_CK8M_WAIT_SLP 4 -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - -#define ROM_RAM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define ROM_RAM_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define WIFI_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define WIFI_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define RTC_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define DG_WRAP_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define DG_WRAP_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_MEM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define RTC_MEM_WAIT_CYCLES OTHER_BLOCKS_WAIT - -/** - * @brief Power down flags for rtc_sleep_pd function - */ -typedef struct { - uint32_t dig_pd : 1; //!< Set to 1 to power down digital part in sleep - uint32_t rtc_pd : 1; //!< Set to 1 to power down RTC memories in sleep - uint32_t cpu_pd : 1; //!< Set to 1 to power down digital memories and CPU in sleep - uint32_t i2s_pd : 1; //!< Set to 1 to power down I2S in sleep - uint32_t bb_pd : 1; //!< Set to 1 to power down WiFi in sleep - uint32_t nrx_pd : 1; //!< Set to 1 to power down WiFi in sleep - uint32_t fe_pd : 1; //!< Set to 1 to power down WiFi in sleep -} rtc_sleep_pd_config_t; - -/** - * Initializer for rtc_sleep_pd_config_t which sets all flags to the same value - */ -#define RTC_SLEEP_PD_CONFIG_ALL(val) {\ - .dig_pd = (val), \ - .rtc_pd = (val), \ - .cpu_pd = (val), \ - .i2s_pd = (val), \ - .bb_pd = (val), \ - .nrx_pd = (val), \ - .fe_pd = (val), \ -} - /** * Configure whether certain peripherals are powered down in deep sleep * @param cfg power down flags as rtc_sleep_pd_config_t structure */ void rtc_sleep_pd(rtc_sleep_pd_config_t cfg) { - REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, ~cfg.dig_pd); - REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, ~cfg.rtc_pd); - REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, ~cfg.rtc_pd); - DPORT_REG_SET_FIELD(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK, ~cfg.cpu_pd); - REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_PLC_MEM_FORCE_PU, ~cfg.i2s_pd); - REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_FIFO_FORCE_PU, ~cfg.i2s_pd); - REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, ~cfg.bb_pd); - REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, ~cfg.bb_pd); - REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, ~cfg.nrx_pd); - REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, ~cfg.nrx_pd); - REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, ~cfg.nrx_pd); - REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, ~cfg.fe_pd); - REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, ~cfg.fe_pd); + REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); + REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu); + REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu); + REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_PLC_MEM_FORCE_PU, cfg.i2s_fpu); + REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_FIFO_FORCE_PU, cfg.i2s_fpu); + REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu); + REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu); + REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu); + REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu); + REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu); + REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu); } void rtc_sleep_init(rtc_sleep_config_t cfg) { - // set 5 PWC state machine times to fit in main state machine time - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, RTC_CNTL_XTL_BUF_WAIT_SLP); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP); - - // set shortest possible sleep time limit - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN); - - // set rom&ram timer - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_POWERUP_TIMER, ROM_RAM_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_WAIT_TIMER, ROM_RAM_WAIT_CYCLES); - // set wifi timer - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, WIFI_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, WIFI_WAIT_CYCLES); - // set rtc peri timer - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, RTC_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, RTC_WAIT_CYCLES); - // set digital wrap timer - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, DG_WRAP_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, DG_WRAP_WAIT_CYCLES); - // set rtc memory timer - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, RTC_MEM_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, RTC_MEM_WAIT_CYCLES); - - REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.lslp_mem_inf_fpu); - - rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(cfg.lslp_meminf_pd); - rtc_sleep_pd(pd_cfg); - - if (cfg.rtc_mem_inf_fpu) { - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU); - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU); + if (cfg.lslp_mem_inf_fpu) { + rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(1); + rtc_sleep_pd(pd_cfg); } if (cfg.rtc_mem_inf_follow_cpu) { @@ -174,20 +96,20 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } if (cfg.deep_slp) { - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, - RTC_CNTL_DG_PAD_FORCE_ISO | RTC_CNTL_DG_PAD_FORCE_NOISO); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, - RTC_CNTL_DG_WRAP_FORCE_PU | RTC_CNTL_DG_WRAP_FORCE_PD); - // Shut down parts of RTC which may have been left enabled by the wireless drivers CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU); } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT); } - - REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT); /* enable VDDSDIO control by state machine */ REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); @@ -197,6 +119,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); + + REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); + REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); } void rtc_sleep_set_wakeup_time(uint64_t t) @@ -205,10 +130,10 @@ void rtc_sleep_set_wakeup_time(uint64_t t) WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); } -uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt) +uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu) { REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt); - WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt); + REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt); /* Start entry into sleep mode */ SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); @@ -222,5 +147,10 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt) SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); + /* restore config if it is a light sleep */ + if (lslp_mem_inf_fpu) { + rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0); + rtc_sleep_pd(pd_cfg); + } return reject; } diff --git a/components/soc/esp32s2beta/rtc_time.c b/components/soc/esp32s2beta/rtc_time.c index 290c439784..52d63934b3 100644 --- a/components/soc/esp32s2beta/rtc_time.c +++ b/components/soc/esp32s2beta/rtc_time.c @@ -18,8 +18,6 @@ #include "soc/rtc_cntl_reg.h" #include "soc/timer_group_reg.h" -#define MHZ (1000000) - /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. * This feature counts the number of XTAL clock cycles within a given number of * RTC_SLOW_CLK cycles. @@ -66,14 +64,14 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) /* Set timeout reg and expect time delay*/ uint32_t expected_freq; if (cal_clk == RTC_CAL_32K_XTAL) { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 13)); - expected_freq = 32768; + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = RTC_SLOW_CLK_FREQ_32K; } else if (cal_clk == RTC_CAL_8MD256) { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 13)); - expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256; + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = RTC_SLOW_CLK_FREQ_8MD256; } else { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 11)); - expected_freq = 90000; + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = RTC_SLOW_CLK_FREQ_150K; } uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ diff --git a/components/soc/esp32s2beta/spi_periph.c b/components/soc/esp32s2beta/spi_periph.c index 5291d1f576..8f092af2a7 100644 --- a/components/soc/esp32s2beta/spi_periph.c +++ b/components/soc/esp32s2beta/spi_periph.c @@ -45,7 +45,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .hw = (spi_dev_t *) &SPIMEM1, .func = SPI_FUNC_NUM, }, { - .spiclk_out = FSPICLK_OUT_MUX_IDX, + .spiclk_out = FSPICLK_OUT_IDX, .spiclk_in = FSPICLK_IN_IDX, .spid_out = FSPID_OUT_IDX, .spiq_out = FSPIQ_OUT_IDX, diff --git a/components/spi_flash/esp32s2beta/spi_flash_rom_patch.c b/components/spi_flash/esp32s2beta/spi_flash_rom_patch.c index e6656e2fb9..d0b08967b7 100644 --- a/components/spi_flash/esp32s2beta/spi_flash_rom_patch.c +++ b/components/spi_flash/esp32s2beta/spi_flash_rom_patch.c @@ -194,10 +194,10 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t * uint32_t status_value = ESP_ROM_SPIFLASH_BUSY_FLAG; if (g_rom_spiflash_dummy_len_plus[1] == 0) { + REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY); while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) { WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, 0); // clear regisrter WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_MEM_FLASH_RDSR); - REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY); while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); status_value = READ_PERI_REG(PERIPHS_SPI_FLASH_STATUS) & (spi->status_mask); @@ -255,7 +255,7 @@ static esp_rom_spiflash_result_t esp_rom_spiflash_read_data(esp_rom_spiflash_chi if (temp_length >= ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM) { //WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << ESP_ROM_SPIFLASH_BYTES_LEN)); REG_WRITE(SPI_MEM_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_MEM_USR_MISO_DBITLEN_S); - WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8); + WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr); REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_MEM_USR); while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0); @@ -266,7 +266,7 @@ static esp_rom_spiflash_result_t esp_rom_spiflash_read_data(esp_rom_spiflash_chi temp_addr = temp_addr + ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM; } else { //WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(temp_length << ESP_ROM_SPIFLASH_BYTES_LEN )); - WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8); + WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr); REG_WRITE(SPI_MEM_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_MEM_USR_MISO_DBITLEN_S); REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_MEM_USR); while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0); @@ -321,7 +321,7 @@ static void spi_cache_mode_switch(uint32_t modebit) } else if ((modebit & SPI_MEM_FREAD_DUAL)) { REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]); REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, 0x3B); - } else{ + } else { REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]); REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, 0x0B); }