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feat(intr): clean up and support interrupts on H21

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This commit is contained in:
Marius Vikhammer 2025-01-20 15:10:30 +08:00
parent 4c5e1a0341
commit 267a8776a0
17 changed files with 149 additions and 28 deletions
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4
components/esp_hw_support/port/esp32h21/esp_cpu_intr.c
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@ -10,13 +10,11 @@
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
{
/* On the ESP32-H21, interrupt:
* - 1 is for Wi-Fi
* - 6 for "permanently disabled interrupt"
*
* Interrupts 3, 4 and 7 are unavailable for PULP CPU as they are bound to Core-Local Interrupts (CLINT)
*/
//TODO: [ESP32H21] IDF-11537
const uint32_t rsvd_mask = BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7);
const uint32_t rsvd_mask = BIT(3) | BIT(4) | BIT(6) | BIT(7);
intr_desc_ret->priority = 1;
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;

13
components/esp_system/crosscore_int.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,6 +11,7 @@
#include "esp_intr_alloc.h"
#include "esp_debug_helpers.h"
#include "soc/periph_defs.h"
#include "soc/system_intr.h"
#include "hal/crosscore_int_ll.h"
#include "freertos/FreeRTOS.h"
@ -20,10 +21,6 @@
#include "esp_gdbstub.h"
#endif
#if CONFIG_IDF_TARGET_ESP32H21
#define ETS_FROM_CPU_INTR0_SOURCE ETS_CPU_INTR_FROM_CPU_0_SOURCE
#endif
#define REASON_YIELD BIT(0)
#define REASON_FREQ_SWITCH BIT(1)
#define REASON_PRINT_BACKTRACE BIT(2)
@ -98,12 +95,12 @@ void esp_crosscore_int_init(void)
esp_err_t err __attribute__((unused)) = ESP_OK;
#if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
if (esp_cpu_get_core_id() == 0) {
err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
} else {
err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
}
#else
err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
#endif
ESP_ERROR_CHECK(err);
}

12
components/esp_system/int_wdt.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -12,6 +12,7 @@
#include "hal/wdt_hal.h"
#include "hal/mwdt_ll.h"
#include "hal/timer_ll.h"
#include "soc/system_intr.h"
#include "freertos/FreeRTOS.h"
#include "esp_cpu.h"
#include "esp_check.h"
@ -28,15 +29,10 @@
#include "esp_private/sleep_retention.h"
#endif
#if CONFIG_IDF_TARGET_ESP32H21
#define ETS_TG0_WDT_LEVEL_INTR_SOURCE ETS_TG0_WDT_INTR_SOURCE
#define ETS_TG1_WDT_LEVEL_INTR_SOURCE ETS_TG1_WDT_INTR_SOURCE
#endif
#if SOC_TIMER_GROUPS > 1
/* If we have two hardware timer groups, use the second one for interrupt watchdog. */
#define WDT_LEVEL_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE
#define WDT_LEVEL_INTR_SOURCE SYS_TG1_WDT_INTR_SOURCE
#define IWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
#define IWDT_TICKS_PER_US 500
#define IWDT_INSTANCE WDT_MWDT1
@ -46,7 +42,7 @@
#else
#define WDT_LEVEL_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#define WDT_LEVEL_INTR_SOURCE SYS_TG0_WDT_INTR_SOURCE
#define IWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
#define IWDT_TICKS_PER_US 500
#define IWDT_INSTANCE WDT_MWDT0

10
components/esp_system/task_wdt/task_wdt_impl_timergroup.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,6 +11,7 @@
#include "hal/wdt_hal.h"
#include "hal/mwdt_ll.h"
#include "hal/timer_ll.h"
#include "soc/system_intr.h"
#include "esp_check.h"
#include "esp_err.h"
#include "esp_attr.h"
@ -29,11 +30,8 @@
#define TWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
#define TWDT_PERIPH_MODULE PERIPH_TIMG0_MODULE
#define TWDT_TIMER_GROUP 0
#if CONFIG_IDF_TARGET_ESP32H21
#define TWDT_INTR_SOURCE ETS_TG0_WDT_INTR_SOURCE
#else
#define TWDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#endif
#define TWDT_INTR_SOURCE SYS_TG0_WDT_INTR_SOURCE
/**
* Context for the software implementation of the Task WatchDog Timer.
* This will be passed as a parameter to public functions below. */

2
components/hal/esp32h21/include/hal/crosscore_int_ll.h
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@ -8,8 +8,6 @@
#include "esp_attr.h"
#include "soc/intpri_reg.h"
//TODO: [ESP32H21] IDF-11537, inherit from h2
#ifdef __cplusplus
extern "C" {
#endif

13
components/soc/esp32/include/soc/system_intr.h Normal file
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@ -0,0 +1,13 @@
/**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// Maps misc system interrupt to hardware interrupt names
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
#define SYS_CPU_INTR_FROM_CPU_1_SOURCE ETS_FROM_CPU_INTR1_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

12
components/soc/esp32c2/include/soc/system_intr.h Normal file
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@ -0,0 +1,12 @@
/**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// Maps misc system interrupt to hardware interrupt names
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

12
components/soc/esp32c3/include/soc/system_intr.h Normal file
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@ -0,0 +1,12 @@
/**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// Maps misc system interrupt to hardware interrupt names
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

12
components/soc/esp32c5/include/soc/system_intr.h Normal file
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@ -0,0 +1,12 @@
/**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// Maps misc system interrupt to hardware interrupt names
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

12
components/soc/esp32c6/include/soc/system_intr.h Normal file
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@ -0,0 +1,12 @@
/**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// Maps misc system interrupt to hardware interrupt names
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

12
components/soc/esp32c61/include/soc/system_intr.h Normal file
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@ -0,0 +1,12 @@
/**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// Maps misc system interrupt to hardware interrupt names
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

12
components/soc/esp32h2/include/soc/system_intr.h Normal file
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@ -0,0 +1,12 @@
/**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// Maps misc system interrupt to hardware interrupt names
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

12
components/soc/esp32h21/include/soc/system_intr.h Normal file
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@ -0,0 +1,12 @@
/**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// Maps misc system interrupt to hardware interrupt names
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_CPU_INTR_FROM_CPU_0_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_INTR_SOURCE

1
components/soc/esp32h21/register/soc/plic_reg.h
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@ -10,7 +10,6 @@
extern "C" {
#endif
//TODO: [ESP32H21] IDF-11859
#define DR_REG_PLIC_MX_BASE ( 0x20001000 )
#define DR_REG_PLIC_UX_BASE ( 0x20001400 )

13
components/soc/esp32p4/include/soc/system_intr.h Normal file
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@ -0,0 +1,13 @@
/**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// Maps misc system interrupt to hardware interrupt names
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
#define SYS_CPU_INTR_FROM_CPU_1_SOURCE ETS_FROM_CPU_INTR1_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

12
components/soc/esp32s2/include/soc/system_intr.h Normal file
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@ -0,0 +1,12 @@
/**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// Maps misc system interrupt to hardware interrupt names
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

13
components/soc/esp32s3/include/soc/system_intr.h Normal file
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@ -0,0 +1,13 @@
/**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// Maps misc system interrupt to hardware interrupt names
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
#define SYS_CPU_INTR_FROM_CPU_1_SOURCE ETS_FROM_CPU_INTR1_SOURCE
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE