From 281031e24d25e7cb155018acd8161386e2e1c37b Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Fri, 16 Feb 2024 17:36:11 +0200 Subject: [PATCH] feat(efuse): Adds new efuses for esp32p4 --- components/efuse/esp32p4/esp_efuse_table.c | 293 +++++++++++++++--- components/efuse/esp32p4/esp_efuse_table.csv | 42 ++- .../efuse/esp32p4/include/esp_efuse_table.h | 45 ++- components/hal/esp32p4/include/hal/efuse_ll.h | 17 +- .../soc/esp32p4/include/soc/efuse_reg.h | 206 ++++++++---- .../soc/esp32p4/include/soc/efuse_struct.h | 110 +++++-- .../system/inc/espefuse_summary_ESP32-P4.rst | 31 +- .../system/inc/show-efuse-table_ESP32-P4.rst | 221 +++++++------ 8 files changed, 712 insertions(+), 253 deletions(-) diff --git a/components/efuse/esp32p4/esp_efuse_table.c b/components/efuse/esp32p4/esp_efuse_table.c index 24408d3007..74bf9dd257 100644 --- a/components/efuse/esp32p4/esp_efuse_table.c +++ b/components/efuse/esp32p4/esp_efuse_table.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 78dff63df528392f0f37f4880b83c6db +// md5_digest_table 2eb36a43d52e9922e08cf545d0e23381 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -75,18 +75,74 @@ static const esp_efuse_desc_t WR_DIS_MAC[] = { {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, }; -static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of MAC_EXT, +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR, }; -static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA1[] = { - {EFUSE_BLK0, 21, 1}, // [WR_DIS.SYS_DATA_PART1] wr_dis of BLOCK_SYS_DATA1, +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_TEMP, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR, +}; + +static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP, +}; + +static const esp_efuse_desc_t WR_DIS_PSRAM_TEMP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_TEMP, +}; + +static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VENDOR, +}; + +static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, +}; + +static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, }; static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA, }; +static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC, +}; + static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = { {EFUSE_BLK0, 23, 1}, // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0, }; @@ -195,12 +251,8 @@ static const esp_efuse_desc_t USB_PHY_SEL[] = { {EFUSE_BLK0, 57, 1}, // [] TBD, }; -static const esp_efuse_desc_t KM_HUK_GEN_STATE_LOW[] = { - {EFUSE_BLK0, 58, 6}, // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid, -}; - -static const esp_efuse_desc_t KM_HUK_GEN_STATE_HIGH[] = { - {EFUSE_BLK0, 64, 3}, // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid, +static const esp_efuse_desc_t KM_HUK_GEN_STATE[] = { + {EFUSE_BLK0, 58, 9}, // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid, }; static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE[] = { @@ -400,13 +452,60 @@ static const esp_efuse_desc_t MAC[] = { {EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address, }; -static const esp_efuse_desc_t MAC_EXT[] = { - {EFUSE_BLK1, 48, 8}, // [] Stores the extended bits of MAC address [0], - {EFUSE_BLK1, 56, 8}, // [] Stores the extended bits of MAC address [1], +static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { + {EFUSE_BLK1, 64, 4}, // [] Minor chip version, }; -static const esp_efuse_desc_t BLOCK_SYS_DATA1[] = { - {EFUSE_BLK2, 0, 256}, // [SYS_DATA_PART1] System data part 1, +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 68, 2}, // [] Major chip version, +}; + +static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 70, 1}, // [] Disables check of wafer version major, +}; + +static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK1, 71, 1}, // [] Disables check of blk version major, +}; + +static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { + {EFUSE_BLK1, 72, 3}, // [] BLK_VERSION_MINOR of BLOCK2, +}; + +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK1, 75, 2}, // [] BLK_VERSION_MAJOR of BLOCK2, +}; + +static const esp_efuse_desc_t FLASH_CAP[] = { + {EFUSE_BLK1, 77, 3}, // [] Flash capacity, +}; + +static const esp_efuse_desc_t FLASH_TEMP[] = { + {EFUSE_BLK1, 80, 2}, // [] Flash temperature, +}; + +static const esp_efuse_desc_t FLASH_VENDOR[] = { + {EFUSE_BLK1, 82, 3}, // [] Flash vendor, +}; + +static const esp_efuse_desc_t PSRAM_CAP[] = { + {EFUSE_BLK1, 85, 2}, // [] PSRAM capacity, +}; + +static const esp_efuse_desc_t PSRAM_TEMP[] = { + {EFUSE_BLK1, 87, 2}, // [] PSRAM temperature, +}; + +static const esp_efuse_desc_t PSRAM_VENDOR[] = { + {EFUSE_BLK1, 89, 2}, // [] PSRAM vendor, +}; + +static const esp_efuse_desc_t PKG_VERSION[] = { + {EFUSE_BLK1, 91, 3}, // [] Package version, +}; + +static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, }; static const esp_efuse_desc_t USER_DATA[] = { @@ -414,7 +513,7 @@ static const esp_efuse_desc_t USER_DATA[] = { }; static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { - {EFUSE_BLK3, 200, 48}, // [MAC_CUSTOM CUSTOM_MAC] Custom MAC (TODO, + {EFUSE_BLK3, 200, 48}, // [MAC_CUSTOM CUSTOM_MAC] Custom MAC, }; static const esp_efuse_desc_t KEY0[] = { @@ -524,13 +623,78 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = { - &WR_DIS_MAC_EXT[0], // [] wr_dis of MAC_EXT +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { + &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[] = { - &WR_DIS_BLOCK_SYS_DATA1[0], // [WR_DIS.SYS_DATA_PART1] wr_dis of BLOCK_SYS_DATA1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { + &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { + &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { + &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = { + &WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = { + &WR_DIS_FLASH_TEMP[0], // [] wr_dis of FLASH_TEMP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = { + &WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = { + &WR_DIS_PSRAM_CAP[0], // [] wr_dis of PSRAM_CAP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[] = { + &WR_DIS_PSRAM_TEMP[0], // [] wr_dis of PSRAM_TEMP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[] = { + &WR_DIS_PSRAM_VENDOR[0], // [] wr_dis of PSRAM_VENDOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { + &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { + &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { + &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID NULL }; @@ -539,6 +703,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = { + &WR_DIS_CUSTOM_MAC[0], // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = { &WR_DIS_BLOCK_KEY0[0], // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 NULL @@ -674,13 +843,8 @@ const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE_LOW[] = { - &KM_HUK_GEN_STATE_LOW[0], // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE_HIGH[] = { - &KM_HUK_GEN_STATE_HIGH[0], // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid +const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE[] = { + &KM_HUK_GEN_STATE[0], // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid NULL }; @@ -929,14 +1093,73 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { - &MAC_EXT[0], // [] Stores the extended bits of MAC address [0] - &MAC_EXT[1], // [] Stores the extended bits of MAC address [1] +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { + &WAFER_VERSION_MINOR[0], // [] Minor chip version NULL }; -const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[] = { - &BLOCK_SYS_DATA1[0], // [SYS_DATA_PART1] System data part 1 +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { + &WAFER_VERSION_MAJOR[0], // [] Major chip version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { + &DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { + &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { + &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = { + &FLASH_CAP[0], // [] Flash capacity + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = { + &FLASH_TEMP[0], // [] Flash temperature + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { + &FLASH_VENDOR[0], // [] Flash vendor + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = { + &PSRAM_CAP[0], // [] PSRAM capacity + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[] = { + &PSRAM_TEMP[0], // [] PSRAM temperature + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = { + &PSRAM_VENDOR[0], // [] PSRAM vendor + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { + &PKG_VERSION[0], // [] Package version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { + &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID NULL }; @@ -946,7 +1169,7 @@ const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { }; const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { - &USER_DATA_MAC_CUSTOM[0], // [MAC_CUSTOM CUSTOM_MAC] Custom MAC (TODO + &USER_DATA_MAC_CUSTOM[0], // [MAC_CUSTOM CUSTOM_MAC] Custom MAC NULL }; diff --git a/components/efuse/esp32p4/esp_efuse_table.csv b/components/efuse/esp32p4/esp_efuse_table.csv index 7bc44e0b51..18cf111402 100644 --- a/components/efuse/esp32p4/esp_efuse_table.csv +++ b/components/efuse/esp32p4/esp_efuse_table.csv @@ -9,7 +9,7 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# This file was generated by regtools.py based on the efuses.yaml file with the version: 552d7a824581925566213ca4f4d488dc +# This file was generated by regtools.py based on the efuses.yaml file with the version: 6b72374c237a3473c8832aadee437405 WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS @@ -26,9 +26,23 @@ WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.K WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC -WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT -WR_DIS.BLOCK_SYS_DATA1, EFUSE_BLK0, 21, 1, [WR_DIS.SYS_DATA_PART1] wr_dis of BLOCK_SYS_DATA1 +WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR +WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR +WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR +WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR +WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR +WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR +WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP +WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP +WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR +WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP +WR_DIS.PSRAM_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_TEMP +WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR +WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION +WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 +WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA +WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 @@ -56,8 +70,7 @@ SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Repres DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled USB_PHY_SEL, EFUSE_BLK0, 57, 1, [] TBD -KM_HUK_GEN_STATE_LOW, EFUSE_BLK0, 58, 6, [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid -KM_HUK_GEN_STATE_HIGH, EFUSE_BLK0, 64, 3, [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid +KM_HUK_GEN_STATE, EFUSE_BLK0, 58, 9, [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 67, 2, [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 69, 4, [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 73, 4, [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds @@ -111,11 +124,22 @@ MAC, EFUSE_BLK1, 40, 8, [MAC_FACT , EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address -MAC_EXT, EFUSE_BLK1, 48, 8, [] Stores the extended bits of MAC address [0] -, EFUSE_BLK1, 56, 8, [] Stores the extended bits of MAC address [1] -BLOCK_SYS_DATA1, EFUSE_BLK2, 0, 256, [SYS_DATA_PART1] System data part 1 +WAFER_VERSION_MINOR, EFUSE_BLK1, 64, 4, [] Minor chip version +WAFER_VERSION_MAJOR, EFUSE_BLK1, 68, 2, [] Major chip version +DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 70, 1, [] Disables check of wafer version major +DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 71, 1, [] Disables check of blk version major +BLK_VERSION_MINOR, EFUSE_BLK1, 72, 3, [] BLK_VERSION_MINOR of BLOCK2 +BLK_VERSION_MAJOR, EFUSE_BLK1, 75, 2, [] BLK_VERSION_MAJOR of BLOCK2 +FLASH_CAP, EFUSE_BLK1, 77, 3, [] Flash capacity +FLASH_TEMP, EFUSE_BLK1, 80, 2, [] Flash temperature +FLASH_VENDOR, EFUSE_BLK1, 82, 3, [] Flash vendor +PSRAM_CAP, EFUSE_BLK1, 85, 2, [] PSRAM capacity +PSRAM_TEMP, EFUSE_BLK1, 87, 2, [] PSRAM temperature +PSRAM_VENDOR, EFUSE_BLK1, 89, 2, [] PSRAM vendor +PKG_VERSION, EFUSE_BLK1, 91, 3, [] Package version +OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC (TODO, not defined yet) +USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data diff --git a/components/efuse/esp32p4/include/esp_efuse_table.h b/components/efuse/esp32p4/include/esp_efuse_table.h index 048b788a84..9cbeb26359 100644 --- a/components/efuse/esp32p4/include/esp_efuse_table.h +++ b/components/efuse/esp32p4/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 78dff63df528392f0f37f4880b83c6db +// md5_digest_table 2eb36a43d52e9922e08cf545d0e23381 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -39,11 +39,26 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; #define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[]; -#define ESP_EFUSE_WR_DIS_SYS_DATA_PART1 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; #define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; @@ -85,8 +100,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE_LOW[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE_HIGH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE[]; extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[]; extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[]; @@ -142,9 +156,20 @@ extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; #define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[]; -#define ESP_EFUSE_SYS_DATA_PART1 ESP_EFUSE_BLOCK_SYS_DATA1 +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; diff --git a/components/hal/esp32p4/include/hal/efuse_ll.h b/components/hal/esp32p4/include/hal/efuse_ll.h index c5d44d2cab..3032dd041b 100644 --- a/components/hal/esp32p4/include/hal/efuse_ll.h +++ b/components/hal/esp32p4/include/hal/efuse_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -48,39 +48,38 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en // use efuse_hal_get_major_chip_version() to get major chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) { - // return EFUSE.rd_mac_sys_5; - return 0; + return EFUSE.rd_mac_sys_2.wafer_version_major; } // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return 0; + return EFUSE.rd_mac_sys_2.wafer_version_minor; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) { - return 0; + return EFUSE.rd_mac_sys_2.disable_wafer_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) { - return 0; + return EFUSE.rd_mac_sys_2.disable_blk_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) { - return 0; + return EFUSE.rd_mac_sys_2.blk_version_minor; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) { - return 0; + return EFUSE.rd_mac_sys_2.blk_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) { - return 0; + return EFUSE.rd_mac_sys_2.pkg_version; } __attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) diff --git a/components/soc/esp32p4/include/soc/efuse_reg.h b/components/soc/esp32p4/include/soc/efuse_reg.h index 8f9eee05e8..17c2aa5a1a 100644 --- a/components/soc/esp32p4/include/soc/efuse_reg.h +++ b/components/soc/esp32p4/include/soc/efuse_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -735,32 +735,116 @@ extern "C" { #define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) #define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 -/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; +/** EFUSE_RESERVED_1_16 : RO; bitpos: [31:16]; default: 0; * Stores the extended bits of MAC address. */ -#define EFUSE_MAC_EXT 0x0000FFFFU -#define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) -#define EFUSE_MAC_EXT_V 0x0000FFFFU -#define EFUSE_MAC_EXT_S 16 +#define EFUSE_RESERVED_1_16 0x0000FFFFU +#define EFUSE_RESERVED_1_16_M (EFUSE_RESERVED_1_16_V << EFUSE_RESERVED_1_16_S) +#define EFUSE_RESERVED_1_16_V 0x0000FFFFU +#define EFUSE_RESERVED_1_16_S 16 /** EFUSE_RD_MAC_SYS_2_REG register * BLOCK1 data register $n. */ #define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [13:0]; default: 0; - * Reserved. +/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0; + * Minor chip version */ -#define EFUSE_MAC_RESERVED_1 0x00003FFFU -#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) -#define EFUSE_MAC_RESERVED_1_V 0x00003FFFU -#define EFUSE_MAC_RESERVED_1_S 0 -/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [31:14]; default: 0; - * Reserved. +#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU +#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) +#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU +#define EFUSE_WAFER_VERSION_MINOR_S 0 +/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0; + * Major chip version */ -#define EFUSE_MAC_RESERVED_0 0x0003FFFFU -#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) -#define EFUSE_MAC_RESERVED_0_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_0_S 14 +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 4 +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0; + * Disables check of wafer version major + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(6)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 6 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0; + * BLK_VERSION_MINOR of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 8 +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 11 +/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0; + * Flash capacity + */ +#define EFUSE_FLASH_CAP 0x00000007U +#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) +#define EFUSE_FLASH_CAP_V 0x00000007U +#define EFUSE_FLASH_CAP_S 13 +/** EFUSE_FLASH_TEMP : R; bitpos: [17:16]; default: 0; + * Flash temperature + */ +#define EFUSE_FLASH_TEMP 0x00000003U +#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S) +#define EFUSE_FLASH_TEMP_V 0x00000003U +#define EFUSE_FLASH_TEMP_S 16 +/** EFUSE_FLASH_VENDOR : R; bitpos: [20:18]; default: 0; + * Flash vendor + */ +#define EFUSE_FLASH_VENDOR 0x00000007U +#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) +#define EFUSE_FLASH_VENDOR_V 0x00000007U +#define EFUSE_FLASH_VENDOR_S 18 +/** EFUSE_PSRAM_CAP : R; bitpos: [22:21]; default: 0; + * PSRAM capacity + */ +#define EFUSE_PSRAM_CAP 0x00000003U +#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S) +#define EFUSE_PSRAM_CAP_V 0x00000003U +#define EFUSE_PSRAM_CAP_S 21 +/** EFUSE_PSRAM_TEMP : R; bitpos: [24:23]; default: 0; + * PSRAM temperature + */ +#define EFUSE_PSRAM_TEMP 0x00000003U +#define EFUSE_PSRAM_TEMP_M (EFUSE_PSRAM_TEMP_V << EFUSE_PSRAM_TEMP_S) +#define EFUSE_PSRAM_TEMP_V 0x00000003U +#define EFUSE_PSRAM_TEMP_S 23 +/** EFUSE_PSRAM_VENDOR : R; bitpos: [26:25]; default: 0; + * PSRAM vendor + */ +#define EFUSE_PSRAM_VENDOR 0x00000003U +#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S) +#define EFUSE_PSRAM_VENDOR_V 0x00000003U +#define EFUSE_PSRAM_VENDOR_S 25 +/** EFUSE_PKG_VERSION : R; bitpos: [29:27]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x00000007U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000007U +#define EFUSE_PKG_VERSION_S 27 +/** EFUSE_RESERVED_1_94 : R; bitpos: [31:30]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_94 0x00000003U +#define EFUSE_RESERVED_1_94_M (EFUSE_RESERVED_1_94_V << EFUSE_RESERVED_1_94_S) +#define EFUSE_RESERVED_1_94_V 0x00000003U +#define EFUSE_RESERVED_1_94_S 30 /** EFUSE_RD_MAC_SYS_3_REG register * BLOCK1 data register $n. @@ -809,49 +893,49 @@ extern "C" { * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) -/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of the first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 /** EFUSE_RD_SYS_PART1_DATA1_REG register * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 /** EFUSE_RD_SYS_PART1_DATA2_REG register * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 /** EFUSE_RD_SYS_PART1_DATA3_REG register * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of the first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 /** EFUSE_RD_SYS_PART1_DATA4_REG register * Register $n of BLOCK2 (system). @@ -977,25 +1061,39 @@ extern "C" { * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of BLOCK3 (user). +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved */ -#define EFUSE_USR_DATA6 0xFFFFFFFFU -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFFU -#define EFUSE_USR_DATA6_S 0 +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 /** EFUSE_RD_USR_DATA7_REG register * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of BLOCK3 (user). +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC */ -#define EFUSE_USR_DATA7 0xFFFFFFFFU -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFFU -#define EFUSE_USR_DATA7_S 0 +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 /** EFUSE_RD_KEY0_DATA0_REG register * Register $n of BLOCK4 (KEY0). diff --git a/components/soc/esp32p4/include/soc/efuse_struct.h b/components/soc/esp32p4/include/soc/efuse_struct.h index 99d8f8cfda..21a6f9f404 100644 --- a/components/soc/esp32p4/include/soc/efuse_struct.h +++ b/components/soc/esp32p4/include/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -554,10 +554,10 @@ typedef union { * Stores the high 16 bits of MAC address. */ uint32_t mac_1:16; - /** mac_ext : RO; bitpos: [31:16]; default: 0; + /** reserved_1_16 : RO; bitpos: [31:16]; default: 0; * Stores the extended bits of MAC address. */ - uint32_t mac_ext:16; + uint32_t reserved_1_16:16; }; uint32_t val; } efuse_rd_mac_sys_1_reg_t; @@ -567,14 +567,62 @@ typedef union { */ typedef union { struct { - /** mac_reserved_1 : RO; bitpos: [13:0]; default: 0; - * Reserved. + /** wafer_version_minor : R; bitpos: [3:0]; default: 0; + * Minor chip version */ - uint32_t mac_reserved_1:14; - /** mac_reserved_0 : RO; bitpos: [31:14]; default: 0; - * Reserved. + uint32_t wafer_version_minor:4; + /** wafer_version_major : R; bitpos: [5:4]; default: 0; + * Major chip version */ - uint32_t mac_reserved_0:18; + uint32_t wafer_version_major:2; + /** disable_wafer_version_major : R; bitpos: [6]; default: 0; + * Disables check of wafer version major + */ + uint32_t disable_wafer_version_major:1; + /** disable_blk_version_major : R; bitpos: [7]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** blk_version_minor : R; bitpos: [10:8]; default: 0; + * BLK_VERSION_MINOR of BLOCK2 + */ + uint32_t blk_version_minor:3; + /** blk_version_major : R; bitpos: [12:11]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ + uint32_t blk_version_major:2; + /** flash_cap : R; bitpos: [15:13]; default: 0; + * Flash capacity + */ + uint32_t flash_cap:3; + /** flash_temp : R; bitpos: [17:16]; default: 0; + * Flash temperature + */ + uint32_t flash_temp:2; + /** flash_vendor : R; bitpos: [20:18]; default: 0; + * Flash vendor + */ + uint32_t flash_vendor:3; + /** psram_cap : R; bitpos: [22:21]; default: 0; + * PSRAM capacity + */ + uint32_t psram_cap:2; + /** psram_temp : R; bitpos: [24:23]; default: 0; + * PSRAM temperature + */ + uint32_t psram_temp:2; + /** psram_vendor : R; bitpos: [26:25]; default: 0; + * PSRAM vendor + */ + uint32_t psram_vendor:2; + /** pkg_version : R; bitpos: [29:27]; default: 0; + * Package version + */ + uint32_t pkg_version:3; + /** reserved_1_94 : R; bitpos: [31:30]; default: 0; + * reserved + */ + uint32_t reserved_1_94:2; }; uint32_t val; } efuse_rd_mac_sys_2_reg_t; @@ -627,10 +675,10 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of the first part of system data. + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_0:32; + uint32_t optional_unique_id:32; }; uint32_t val; } efuse_rd_sys_part1_data0_reg_t; @@ -640,10 +688,10 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the first part of system data. + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_1:32; + uint32_t optional_unique_id_1:32; }; uint32_t val; } efuse_rd_sys_part1_data1_reg_t; @@ -653,10 +701,10 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the first part of system data. + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_2:32; + uint32_t optional_unique_id_2:32; }; uint32_t val; } efuse_rd_sys_part1_data2_reg_t; @@ -666,10 +714,10 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of the first part of system data. + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_3:32; + uint32_t optional_unique_id_3:32; }; uint32_t val; } efuse_rd_sys_part1_data3_reg_t; @@ -809,10 +857,14 @@ typedef union { */ typedef union { struct { - /** usr_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of BLOCK3 (user). + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved */ - uint32_t usr_data6:32; + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; }; uint32_t val; } efuse_rd_usr_data6_reg_t; @@ -822,10 +874,14 @@ typedef union { */ typedef union { struct { - /** usr_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of BLOCK3 (user). + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC */ - uint32_t usr_data7:32; + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; }; uint32_t val; } efuse_rd_usr_data7_reg_t; diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-P4.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-P4.rst index 86fb6e37c3..082d02e120 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-P4.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-P4.rst @@ -2,7 +2,7 @@ espefuse.py -p PORT summary - espefuse.py v4.7.dev1 + espefuse.py v4.7.0 Connecting.... Detecting chip type... ESP32-P4 @@ -16,9 +16,7 @@ d. 1: enabled. 0: disabled DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0) abled. 1: disabled. 0: enabled - KM_HUK_GEN_STATE_LOW (BLOCK0) Set this bit to control validation of HUK generate = 0 R/W (0b000000) - mode. Odd of 1 is invalid; even of 1 is valid - KM_HUK_GEN_STATE_HIGH (BLOCK0) Set this bit to control validation of HUK generate = 0 R/W (0b000) + KM_HUK_GEN_STATE (BLOCK0) Set this bit to control validation of HUK generate = 0 R/W (0b000000000) mode. Odd of 1 is invalid; even of 1 is valid KM_RND_SWITCH_CYCLE (BLOCK0) Set bits to control key manager random number swit = 0 R/W (0b00) ch cycle. 0: control by register. 1: 8 km clk cycl @@ -43,8 +41,9 @@ HP_PWR_SRC_SEL (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) DCDC_VSET_EN (BLOCK0) Select dcdc vset use efuse_dcdc_vset = False R/W (0b0) DIS_SWD (BLOCK0) Set this bit to disable super-watchdog = False R/W (0b0) - BLOCK_SYS_DATA1 (BLOCK2) System data part 1 - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + PSRAM_CAP (BLOCK1) PSRAM capacity = 0 R/W (0b00) + PSRAM_TEMP (BLOCK1) PSRAM temperature = 0 R/W (0b00) + PSRAM_VENDOR (BLOCK1) PSRAM vendor = 0 R/W (0b00) BLOCK_USR_DATA (BLOCK3) User data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) @@ -62,6 +61,20 @@ FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0) sume command during SPI boot. 1: forced. 0:not for ced + FLASH_CAP (BLOCK1) Flash capacity = 0 R/W (0b000) + FLASH_TEMP (BLOCK1) Flash temperature = 0 R/W (0b00) + FLASH_VENDOR (BLOCK1) Flash vendor = 0 R/W (0b000) + + Identity fuses: + WAFER_VERSION_MINOR (BLOCK1) Minor chip version = 0 R/W (0x0) + WAFER_VERSION_MAJOR (BLOCK1) Major chip version = 0 R/W (0b00) + DISABLE_WAFER_VERSION_MAJOR (BLOCK1) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK1) Disables check of blk version major = False R/W (0b0) + BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR of BLOCK2 = 0 R/W (0b000) + BLK_VERSION_MAJOR (BLOCK1) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Jtag fuses: JTAG_SEL_ENABLE (BLOCK0) Represents whether the selection between usb_to_jt = False R/W (0b0) @@ -76,11 +89,9 @@ Mac fuses: MAC (BLOCK1) MAC address + = 60:55:f9:f8:80:40 (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC = 00:00:00:00:00:00 (OK) R/W - MAC_EXT (BLOCK1) Stores the extended bits of MAC address = 00:00 (OK) R/W - MAC_EUI64 (BLOCK1) calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:M - = 00:00:00:00:00:00:00:00 (OK) R/W - AC_EXT[1]:MAC[3]:MAC[4]:MAC[5] Security fuses: DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) diff --git a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-P4.rst b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-P4.rst index 890ef8305c..5f62b76bf2 100644 --- a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-P4.rst +++ b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-P4.rst @@ -23,116 +23,139 @@ 13 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1 14 WR_DIS.BLK1 EFUSE_BLK0 20 1 15 WR_DIS.MAC EFUSE_BLK0 20 1 - 16 WR_DIS.MAC_EXT EFUSE_BLK0 20 1 - 17 WR_DIS.BLOCK_SYS_DATA1 EFUSE_BLK0 21 1 - 18 WR_DIS.BLOCK_USR_DATA EFUSE_BLK0 22 1 - 19 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 23 1 - 20 WR_DIS.BLOCK_KEY1 EFUSE_BLK0 24 1 - 21 WR_DIS.BLOCK_KEY2 EFUSE_BLK0 25 1 - 22 WR_DIS.BLOCK_KEY3 EFUSE_BLK0 26 1 - 23 WR_DIS.BLOCK_KEY4 EFUSE_BLK0 27 1 - 24 WR_DIS.BLOCK_KEY5 EFUSE_BLK0 28 1 - 25 WR_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 29 1 - 26 RD_DIS EFUSE_BLK0 32 7 - 27 RD_DIS.BLOCK_KEY0 EFUSE_BLK0 32 1 - 28 RD_DIS.BLOCK_KEY1 EFUSE_BLK0 33 1 - 29 RD_DIS.BLOCK_KEY2 EFUSE_BLK0 34 1 - 30 RD_DIS.BLOCK_KEY3 EFUSE_BLK0 35 1 - 31 RD_DIS.BLOCK_KEY4 EFUSE_BLK0 36 1 - 32 RD_DIS.BLOCK_KEY5 EFUSE_BLK0 37 1 - 33 RD_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 38 1 - 34 USB_DEVICE_EXCHG_PINS EFUSE_BLK0 39 1 - 35 USB_OTG11_EXCHG_PINS EFUSE_BLK0 40 1 - 36 DIS_USB_JTAG EFUSE_BLK0 41 1 - 37 POWERGLITCH_EN EFUSE_BLK0 42 1 - 38 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 - 39 SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 45 1 - 40 DIS_TWAI EFUSE_BLK0 46 1 - 41 JTAG_SEL_ENABLE EFUSE_BLK0 47 1 - 42 SOFT_DIS_JTAG EFUSE_BLK0 48 3 - 43 DIS_PAD_JTAG EFUSE_BLK0 51 1 - 44 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1 - 45 USB_PHY_SEL EFUSE_BLK0 57 1 - 46 KM_HUK_GEN_STATE_LOW EFUSE_BLK0 58 6 - 47 KM_HUK_GEN_STATE_HIGH EFUSE_BLK0 64 3 - 48 KM_RND_SWITCH_CYCLE EFUSE_BLK0 67 2 - 49 KM_DEPLOY_ONLY_ONCE EFUSE_BLK0 69 4 - 50 FORCE_USE_KEY_MANAGER_KEY EFUSE_BLK0 73 4 - 51 FORCE_DISABLE_SW_INIT_KEY EFUSE_BLK0 77 1 - 52 XTS_KEY_LENGTH_256 EFUSE_BLK0 78 1 - 53 WDT_DELAY_SEL EFUSE_BLK0 80 2 - 54 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3 - 55 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1 - 56 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1 - 57 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1 - 58 KEY_PURPOSE_0 EFUSE_BLK0 88 4 - 59 KEY_PURPOSE_1 EFUSE_BLK0 92 4 - 60 KEY_PURPOSE_2 EFUSE_BLK0 96 4 - 61 KEY_PURPOSE_3 EFUSE_BLK0 100 4 - 62 KEY_PURPOSE_4 EFUSE_BLK0 104 4 - 63 KEY_PURPOSE_5 EFUSE_BLK0 108 4 - 64 SEC_DPA_LEVEL EFUSE_BLK0 112 2 - 65 ECDSA_ENABLE_SOFT_K EFUSE_BLK0 114 1 - 66 CRYPT_DPA_ENABLE EFUSE_BLK0 115 1 - 67 SECURE_BOOT_EN EFUSE_BLK0 116 1 - 68 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1 - 69 FLASH_TYPE EFUSE_BLK0 119 1 - 70 FLASH_PAGE_SIZE EFUSE_BLK0 120 2 - 71 FLASH_ECC_EN EFUSE_BLK0 122 1 - 72 DIS_USB_OTG_DOWNLOAD_MODE EFUSE_BLK0 123 1 - 73 FLASH_TPUW EFUSE_BLK0 124 4 - 74 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1 - 75 DIS_DIRECT_BOOT EFUSE_BLK0 129 1 - 76 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 130 1 - 77 LOCK_KM_KEY EFUSE_BLK0 131 1 - 78 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 132 1 - 79 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1 - 80 UART_PRINT_CONTROL EFUSE_BLK0 134 2 - 81 FORCE_SEND_RESUME EFUSE_BLK0 136 1 - 82 SECURE_VERSION EFUSE_BLK0 137 16 - 83 SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 153 1 - 84 HYS_EN_PAD EFUSE_BLK0 154 1 - 85 DCDC_VSET EFUSE_BLK0 155 5 - 86 PXA0_TIEH_SEL_0 EFUSE_BLK0 160 2 - 87 PXA0_TIEH_SEL_1 EFUSE_BLK0 162 2 - 88 PXA0_TIEH_SEL_2 EFUSE_BLK0 164 2 - 89 PXA0_TIEH_SEL_3 EFUSE_BLK0 166 2 - 90 KM_DISABLE_DEPLOY_MODE EFUSE_BLK0 168 4 - 91 HP_PWR_SRC_SEL EFUSE_BLK0 178 1 - 92 DCDC_VSET_EN EFUSE_BLK0 179 1 - 93 DIS_WDT EFUSE_BLK0 180 1 - 94 DIS_SWD EFUSE_BLK0 181 1 - 95 MAC EFUSE_BLK1 0 8 - 96 MAC EFUSE_BLK1 8 8 - 97 MAC EFUSE_BLK1 16 8 - 98 MAC EFUSE_BLK1 24 8 - 99 MAC EFUSE_BLK1 32 8 - 100 MAC EFUSE_BLK1 40 8 - 101 MAC_EXT EFUSE_BLK1 48 8 - 102 MAC_EXT EFUSE_BLK1 56 8 - 103 SYS_DATA_PART2 EFUSE_BLK10 0 256 - 104 BLOCK_SYS_DATA1 EFUSE_BLK2 0 256 - 105 USER_DATA EFUSE_BLK3 0 256 - 106 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 - 107 KEY0 EFUSE_BLK4 0 256 - 108 KEY1 EFUSE_BLK5 0 256 - 109 KEY2 EFUSE_BLK6 0 256 - 110 KEY3 EFUSE_BLK7 0 256 - 111 KEY4 EFUSE_BLK8 0 256 - 112 KEY5 EFUSE_BLK9 0 256 + 16 WR_DIS.WAFER_VERSION_MINOR EFUSE_BLK0 20 1 + 17 WR_DIS.WAFER_VERSION_MAJOR EFUSE_BLK0 20 1 + 18 WR_DIS.DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 20 1 + 19 WR_DIS.DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 20 1 + 20 WR_DIS.BLK_VERSION_MINOR EFUSE_BLK0 20 1 + 21 WR_DIS.BLK_VERSION_MAJOR EFUSE_BLK0 20 1 + 22 WR_DIS.FLASH_CAP EFUSE_BLK0 20 1 + 23 WR_DIS.FLASH_TEMP EFUSE_BLK0 20 1 + 24 WR_DIS.FLASH_VENDOR EFUSE_BLK0 20 1 + 25 WR_DIS.PSRAM_CAP EFUSE_BLK0 20 1 + 26 WR_DIS.PSRAM_TEMP EFUSE_BLK0 20 1 + 27 WR_DIS.PSRAM_VENDOR EFUSE_BLK0 20 1 + 28 WR_DIS.PKG_VERSION EFUSE_BLK0 20 1 + 29 WR_DIS.OPTIONAL_UNIQUE_ID EFUSE_BLK0 21 1 + 30 WR_DIS.BLOCK_USR_DATA EFUSE_BLK0 22 1 + 31 WR_DIS.CUSTOM_MAC EFUSE_BLK0 22 1 + 32 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 23 1 + 33 WR_DIS.BLOCK_KEY1 EFUSE_BLK0 24 1 + 34 WR_DIS.BLOCK_KEY2 EFUSE_BLK0 25 1 + 35 WR_DIS.BLOCK_KEY3 EFUSE_BLK0 26 1 + 36 WR_DIS.BLOCK_KEY4 EFUSE_BLK0 27 1 + 37 WR_DIS.BLOCK_KEY5 EFUSE_BLK0 28 1 + 38 WR_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 29 1 + 39 RD_DIS EFUSE_BLK0 32 7 + 40 RD_DIS.BLOCK_KEY0 EFUSE_BLK0 32 1 + 41 RD_DIS.BLOCK_KEY1 EFUSE_BLK0 33 1 + 42 RD_DIS.BLOCK_KEY2 EFUSE_BLK0 34 1 + 43 RD_DIS.BLOCK_KEY3 EFUSE_BLK0 35 1 + 44 RD_DIS.BLOCK_KEY4 EFUSE_BLK0 36 1 + 45 RD_DIS.BLOCK_KEY5 EFUSE_BLK0 37 1 + 46 RD_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 38 1 + 47 USB_DEVICE_EXCHG_PINS EFUSE_BLK0 39 1 + 48 USB_OTG11_EXCHG_PINS EFUSE_BLK0 40 1 + 49 DIS_USB_JTAG EFUSE_BLK0 41 1 + 50 POWERGLITCH_EN EFUSE_BLK0 42 1 + 51 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 + 52 SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 45 1 + 53 DIS_TWAI EFUSE_BLK0 46 1 + 54 JTAG_SEL_ENABLE EFUSE_BLK0 47 1 + 55 SOFT_DIS_JTAG EFUSE_BLK0 48 3 + 56 DIS_PAD_JTAG EFUSE_BLK0 51 1 + 57 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1 + 58 USB_PHY_SEL EFUSE_BLK0 57 1 + 59 KM_HUK_GEN_STATE EFUSE_BLK0 58 9 + 60 KM_RND_SWITCH_CYCLE EFUSE_BLK0 67 2 + 61 KM_DEPLOY_ONLY_ONCE EFUSE_BLK0 69 4 + 62 FORCE_USE_KEY_MANAGER_KEY EFUSE_BLK0 73 4 + 63 FORCE_DISABLE_SW_INIT_KEY EFUSE_BLK0 77 1 + 64 XTS_KEY_LENGTH_256 EFUSE_BLK0 78 1 + 65 WDT_DELAY_SEL EFUSE_BLK0 80 2 + 66 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3 + 67 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1 + 68 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1 + 69 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1 + 70 KEY_PURPOSE_0 EFUSE_BLK0 88 4 + 71 KEY_PURPOSE_1 EFUSE_BLK0 92 4 + 72 KEY_PURPOSE_2 EFUSE_BLK0 96 4 + 73 KEY_PURPOSE_3 EFUSE_BLK0 100 4 + 74 KEY_PURPOSE_4 EFUSE_BLK0 104 4 + 75 KEY_PURPOSE_5 EFUSE_BLK0 108 4 + 76 SEC_DPA_LEVEL EFUSE_BLK0 112 2 + 77 ECDSA_ENABLE_SOFT_K EFUSE_BLK0 114 1 + 78 CRYPT_DPA_ENABLE EFUSE_BLK0 115 1 + 79 SECURE_BOOT_EN EFUSE_BLK0 116 1 + 80 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1 + 81 FLASH_TYPE EFUSE_BLK0 119 1 + 82 FLASH_PAGE_SIZE EFUSE_BLK0 120 2 + 83 FLASH_ECC_EN EFUSE_BLK0 122 1 + 84 DIS_USB_OTG_DOWNLOAD_MODE EFUSE_BLK0 123 1 + 85 FLASH_TPUW EFUSE_BLK0 124 4 + 86 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1 + 87 DIS_DIRECT_BOOT EFUSE_BLK0 129 1 + 88 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 130 1 + 89 LOCK_KM_KEY EFUSE_BLK0 131 1 + 90 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 132 1 + 91 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1 + 92 UART_PRINT_CONTROL EFUSE_BLK0 134 2 + 93 FORCE_SEND_RESUME EFUSE_BLK0 136 1 + 94 SECURE_VERSION EFUSE_BLK0 137 16 + 95 SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 153 1 + 96 HYS_EN_PAD EFUSE_BLK0 154 1 + 97 DCDC_VSET EFUSE_BLK0 155 5 + 98 PXA0_TIEH_SEL_0 EFUSE_BLK0 160 2 + 99 PXA0_TIEH_SEL_1 EFUSE_BLK0 162 2 + 100 PXA0_TIEH_SEL_2 EFUSE_BLK0 164 2 + 101 PXA0_TIEH_SEL_3 EFUSE_BLK0 166 2 + 102 KM_DISABLE_DEPLOY_MODE EFUSE_BLK0 168 4 + 103 HP_PWR_SRC_SEL EFUSE_BLK0 178 1 + 104 DCDC_VSET_EN EFUSE_BLK0 179 1 + 105 DIS_WDT EFUSE_BLK0 180 1 + 106 DIS_SWD EFUSE_BLK0 181 1 + 107 MAC EFUSE_BLK1 0 8 + 108 MAC EFUSE_BLK1 8 8 + 109 MAC EFUSE_BLK1 16 8 + 110 MAC EFUSE_BLK1 24 8 + 111 MAC EFUSE_BLK1 32 8 + 112 MAC EFUSE_BLK1 40 8 + 113 WAFER_VERSION_MINOR EFUSE_BLK1 64 4 + 114 WAFER_VERSION_MAJOR EFUSE_BLK1 68 2 + 115 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK1 70 1 + 116 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK1 71 1 + 117 BLK_VERSION_MINOR EFUSE_BLK1 72 3 + 118 BLK_VERSION_MAJOR EFUSE_BLK1 75 2 + 119 FLASH_CAP EFUSE_BLK1 77 3 + 120 FLASH_TEMP EFUSE_BLK1 80 2 + 121 FLASH_VENDOR EFUSE_BLK1 82 3 + 122 PSRAM_CAP EFUSE_BLK1 85 2 + 123 PSRAM_TEMP EFUSE_BLK1 87 2 + 124 PSRAM_VENDOR EFUSE_BLK1 89 2 + 125 PKG_VERSION EFUSE_BLK1 91 3 + 126 SYS_DATA_PART2 EFUSE_BLK10 0 256 + 127 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128 + 128 USER_DATA EFUSE_BLK3 0 256 + 129 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 + 130 KEY0 EFUSE_BLK4 0 256 + 131 KEY1 EFUSE_BLK5 0 256 + 132 KEY2 EFUSE_BLK6 0 256 + 133 KEY3 EFUSE_BLK7 0 256 + 134 KEY4 EFUSE_BLK8 0 256 + 135 KEY5 EFUSE_BLK9 0 256 Used bits in efuse table: EFUSE_BLK0 [0 31] [0 0] [4 13] [15 15] [20 20] [20 20] [20 29] [32 38] [32 42] [44 52] [57 78] [80 117] [119 171] [178 181] EFUSE_BLK1 - [0 63] + [0 47] [64 93] EFUSE_BLK10 [0 255] EFUSE_BLK2 - [0 255] + [0 127] EFUSE_BLK3 [0 255] [200 247]