fix(mmu): fixed esp_mmu_vaddr_to_paddr cannot figure out psram vaddr issue on esp32p4

This commit is contained in:
Armando 2025-02-14 11:53:58 +08:00
parent 0902e70e94
commit 299d8115ed
4 changed files with 69 additions and 15 deletions

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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -186,13 +186,6 @@ static void s_reserve_drom_region(mem_region_t *hw_mem_regions, int region_nums)
} }
#endif //#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS #endif //#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
#if SOC_MMU_PER_EXT_MEM_TARGET
FORCE_INLINE_ATTR uint32_t s_get_mmu_id_from_target(mmu_target_t target)
{
return (target == MMU_TARGET_FLASH0) ? MMU_LL_FLASH_MMU_ID : MMU_LL_PSRAM_MMU_ID;
}
#endif
void esp_mmu_map_init(void) void esp_mmu_map_init(void)
{ {
mem_region_t hw_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {}; mem_region_t hw_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {};
@ -393,7 +386,7 @@ static void IRAM_ATTR NOINLINE_ATTR s_do_cache_invalidate(uint32_t vaddr_start,
FORCE_INLINE_ATTR uint32_t s_mapping_operation(mmu_target_t target, uint32_t vaddr_start, esp_paddr_t paddr_start, uint32_t size) FORCE_INLINE_ATTR uint32_t s_mapping_operation(mmu_target_t target, uint32_t vaddr_start, esp_paddr_t paddr_start, uint32_t size)
{ {
uint32_t actual_mapped_len = 0; uint32_t actual_mapped_len = 0;
uint32_t mmu_id = s_get_mmu_id_from_target(target); uint32_t mmu_id = mmu_hal_get_id_from_target(target);
mmu_hal_map_region(mmu_id, target, vaddr_start, paddr_start, size, &actual_mapped_len); mmu_hal_map_region(mmu_id, target, vaddr_start, paddr_start, size, &actual_mapped_len);
return actual_mapped_len; return actual_mapped_len;
@ -599,7 +592,7 @@ err:
FORCE_INLINE_ATTR void s_unmapping_operation(uint32_t vaddr_start, uint32_t size) FORCE_INLINE_ATTR void s_unmapping_operation(uint32_t vaddr_start, uint32_t size)
{ {
mmu_target_t target = mmu_ll_vaddr_to_target(vaddr_start); mmu_target_t target = mmu_ll_vaddr_to_target(vaddr_start);
uint32_t mmu_id = s_get_mmu_id_from_target(target); uint32_t mmu_id = mmu_hal_get_id_from_target(target);
mmu_hal_unmap_region(mmu_id, vaddr_start, size); mmu_hal_unmap_region(mmu_id, vaddr_start, size);
} }
#else #else
@ -753,10 +746,14 @@ esp_err_t IRAM_ATTR esp_mmu_map_dump_mapped_blocks_private(void)
---------------------------------------------------------------*/ ---------------------------------------------------------------*/
static bool NOINLINE_ATTR IRAM_ATTR s_vaddr_to_paddr(uint32_t vaddr, esp_paddr_t *out_paddr, mmu_target_t *out_target) static bool NOINLINE_ATTR IRAM_ATTR s_vaddr_to_paddr(uint32_t vaddr, esp_paddr_t *out_paddr, mmu_target_t *out_target)
{ {
uint32_t mmu_id = 0;
//we call this for now, but this will be refactored to move out of `spi_flash` //we call this for now, but this will be refactored to move out of `spi_flash`
spi_flash_disable_interrupts_caches_and_other_cpu(); spi_flash_disable_interrupts_caches_and_other_cpu();
bool is_mapped = mmu_hal_vaddr_to_paddr(0, vaddr, out_paddr, out_target);
#if SOC_MMU_PER_EXT_MEM_TARGET #if SOC_MMU_PER_EXT_MEM_TARGET
mmu_id = mmu_hal_get_id_from_vaddr(vaddr);
#endif
bool is_mapped = mmu_hal_vaddr_to_paddr(mmu_id, vaddr, out_paddr, out_target);
#if SPIRAM_FLASH_LOAD_TO_PSRAM
if (!is_mapped) { if (!is_mapped) {
is_mapped = mmu_hal_vaddr_to_paddr(1, vaddr, out_paddr, out_target); is_mapped = mmu_hal_vaddr_to_paddr(1, vaddr, out_paddr, out_target);
} }
@ -789,7 +786,7 @@ static bool NOINLINE_ATTR IRAM_ATTR s_paddr_to_vaddr(esp_paddr_t paddr, mmu_targ
spi_flash_disable_interrupts_caches_and_other_cpu(); spi_flash_disable_interrupts_caches_and_other_cpu();
uint32_t mmu_id = 0; uint32_t mmu_id = 0;
#if SOC_MMU_PER_EXT_MEM_TARGET #if SOC_MMU_PER_EXT_MEM_TARGET
mmu_id = s_get_mmu_id_from_target(target); mmu_id = mmu_hal_get_id_from_target(target);
#endif #endif
bool found = mmu_hal_paddr_to_vaddr(mmu_id, paddr, target, type, out_vaddr); bool found = mmu_hal_paddr_to_vaddr(mmu_id, paddr, target, type, out_vaddr);
spi_flash_enable_interrupts_caches_and_other_cpu(); spi_flash_enable_interrupts_caches_and_other_cpu();

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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -84,6 +84,28 @@ static inline mmu_target_t mmu_ll_vaddr_to_target(uint32_t vaddr)
return target; return target;
} }
/**
* Convert MMU virtual address to MMU ID
*
* @param vaddr virtual address
*
* @return MMU ID
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_vaddr_to_id(uint32_t vaddr)
{
uint32_t id = 0;
if (vaddr >= SOC_DRAM_FLASH_ADDRESS_LOW && vaddr < SOC_DRAM_FLASH_ADDRESS_HIGH) {
id = MMU_LL_FLASH_MMU_ID;
} else if (vaddr >= SOC_DRAM_PSRAM_ADDRESS_LOW && vaddr < SOC_DRAM_PSRAM_ADDRESS_HIGH) {
id = MMU_LL_PSRAM_MMU_ID;
} else {
HAL_ASSERT(0);
}
return id;
}
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void) __attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
{ {
unsigned cnt = efuse_ll_get_flash_crypt_cnt(); unsigned cnt = efuse_ll_get_flash_crypt_cnt();

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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2010-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -7,6 +7,7 @@
#pragma once #pragma once
#include <esp_types.h> #include <esp_types.h>
#include "soc/soc_caps.h"
#include "hal/mmu_types.h" #include "hal/mmu_types.h"
#ifdef __cplusplus #ifdef __cplusplus
@ -118,6 +119,28 @@ bool mmu_hal_paddr_to_vaddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target
*/ */
bool mmu_hal_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type); bool mmu_hal_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type);
#if SOC_MMU_PER_EXT_MEM_TARGET
/**
* Get MMU ID from MMU target
*
* @param target MMU target
*
* @return
* MMU ID
*/
uint32_t mmu_hal_get_id_from_target(mmu_target_t target);
/**
* Get MMU ID from vaddr
*
* @param vaddr Virtual address
*
* @return
* MMU ID
*/
uint32_t mmu_hal_get_id_from_vaddr(uint32_t vaddr);
#endif
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -161,3 +161,15 @@ bool mmu_hal_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start,
{ {
return mmu_ll_check_valid_ext_vaddr_region(mmu_id, vaddr_start, len, type); return mmu_ll_check_valid_ext_vaddr_region(mmu_id, vaddr_start, len, type);
} }
#if SOC_MMU_PER_EXT_MEM_TARGET
uint32_t mmu_hal_get_id_from_target(mmu_target_t target)
{
return (target == MMU_TARGET_FLASH0) ? MMU_LL_FLASH_MMU_ID : MMU_LL_PSRAM_MMU_ID;
}
uint32_t mmu_hal_get_id_from_vaddr(uint32_t vaddr)
{
return mmu_ll_vaddr_to_id(vaddr);
}
#endif