diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c
index bcd36bc6dc..a3654ec3dd 100644
--- a/components/bootloader_support/src/bootloader_clock_init.c
+++ b/components/bootloader_support/src/bootloader_clock_init.c
@@ -66,19 +66,22 @@ __attribute__((weak)) void bootloader_clock_configure(void)
         }
 #endif
 
-//TODO: [ESP32C61] IDF-9274, basic rtc support
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
-        // TODO: IDF-5781 Some of esp32c6 SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue
-        // Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
-        clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
-#else
         // Use RTC_FAST clock source sel register field's default value, XTAL_DIV, for 2nd stage bootloader
         // RTC_FAST clock source will be switched to RC_FAST at application startup
         clk_cfg.fast_clk_src = rtc_clk_fast_src_get();
         if (clk_cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_INVALID) {
             clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_XTAL_DIV;
         }
+
+#if CONFIG_IDF_TARGET_ESP32C6
+        if (efuse_hal_chip_revision() == 0) {
+            // Some of ESP32C6-ECO0 chip's SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue,
+            // which will cause the chip to be unable to capture the reset reason when it is reset.
+            // Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
+            clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
+        }
 #endif
+
         rtc_clk_init(clk_cfg);
     }
 
diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h
index 971280ed8f..8aeb061173 100644
--- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h
@@ -405,15 +405,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
  */
 uint64_t rtc_time_get(void);
 
-/**
- * @brief Busy loop until next RTC_SLOW_CLK cycle
- *
- * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
- * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
- * one RTC_SLOW_CLK cycle later.
- */
-void rtc_clk_wait_for_slow_cycle(void);
-
 /**
  * @brief Enable the rtc digital 8M clock
  *
diff --git a/components/esp_hw_support/port/esp32c5/rtc_time.c b/components/esp_hw_support/port/esp32c5/rtc_time.c
index 0f4a512e01..ec157f07d1 100644
--- a/components/esp_hw_support/port/esp32c5/rtc_time.c
+++ b/components/esp_hw_support/port/esp32c5/rtc_time.c
@@ -18,7 +18,7 @@
 #include "soc/chip_revision.h"
 #include "esp_private/periph_ctrl.h"
 
-static const char *TAG = "rtc_time";
+__attribute__((unused)) static const char *TAG = "rtc_time";
 
 /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
  * This feature counts the number of XTAL clock cycles within a given number of
@@ -250,12 +250,6 @@ uint64_t rtc_time_get(void)
     return 0;
 }
 
-void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
-{
-    // TODO: IDF-5781
-    ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
-}
-
 uint32_t rtc_clk_freq_cal(uint32_t cal_val)
 {
     if (cal_val == 0) {
diff --git a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h
index 81a3fa9711..8d508d5df3 100644
--- a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h
@@ -413,15 +413,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
  */
 uint64_t rtc_time_get(void);
 
-/**
- * @brief Busy loop until next RTC_SLOW_CLK cycle
- *
- * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
- * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
- * one RTC_SLOW_CLK cycle later.
- */
-void rtc_clk_wait_for_slow_cycle(void);
-
 /**
  * @brief Enable the rtc digital 8M clock
  *
diff --git a/components/esp_hw_support/port/esp32c6/rtc_time.c b/components/esp_hw_support/port/esp32c6/rtc_time.c
index 98896e786c..40b535eefd 100644
--- a/components/esp_hw_support/port/esp32c6/rtc_time.c
+++ b/components/esp_hw_support/port/esp32c6/rtc_time.c
@@ -18,7 +18,7 @@
 #include "soc/chip_revision.h"
 #include "esp_private/periph_ctrl.h"
 
-static const char *TAG = "rtc_time";
+__attribute__((unused)) static const char *TAG = "rtc_time";
 
 /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
  * This feature counts the number of XTAL clock cycles within a given number of
@@ -257,12 +257,6 @@ uint64_t rtc_time_get(void)
     return lp_timer_hal_get_cycle_count();
 }
 
-void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
-{
-    // TODO: IDF-5781
-    ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
-}
-
 uint32_t rtc_clk_freq_cal(uint32_t cal_val)
 {
     if (cal_val == 0) {
diff --git a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h
index 50a428daf8..cdf1e422b4 100644
--- a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h
@@ -413,15 +413,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
  */
 uint64_t rtc_time_get(void);
 
-/**
- * @brief Busy loop until next RTC_SLOW_CLK cycle
- *
- * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
- * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
- * one RTC_SLOW_CLK cycle later.
- */
-void rtc_clk_wait_for_slow_cycle(void);
-
 /**
  * @brief Enable the rtc digital 8M clock
  *
diff --git a/components/esp_hw_support/port/esp32c61/rtc_time.c b/components/esp_hw_support/port/esp32c61/rtc_time.c
index 182d32ee3f..c3c6f35661 100644
--- a/components/esp_hw_support/port/esp32c61/rtc_time.c
+++ b/components/esp_hw_support/port/esp32c61/rtc_time.c
@@ -17,7 +17,7 @@
 #include "soc/chip_revision.h"
 #include "esp_private/periph_ctrl.h"
 
-static const char *TAG = "rtc_time";
+__attribute__((unused)) static const char *TAG = "rtc_time";
 
 /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
  * This feature counts the number of XTAL clock cycles within a given number of
@@ -254,12 +254,6 @@ uint64_t rtc_time_get(void)
     return 0;
 }
 
-void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
-{
-    // TODO: IDF-5781
-    ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
-}
-
 uint32_t rtc_clk_freq_cal(uint32_t cal_val)
 {
     if (cal_val == 0) {
diff --git a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h
index ae763dc4a8..dfd1f96f01 100644
--- a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h
@@ -411,15 +411,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
  */
 uint64_t rtc_time_get(void);
 
-/**
- * @brief Busy loop until next RTC_SLOW_CLK cycle
- *
- * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
- * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
- * one RTC_SLOW_CLK cycle later.
- */
-void rtc_clk_wait_for_slow_cycle(void);
-
 /**
  * @brief Enable the rtc digital 8M clock
  *
diff --git a/components/esp_hw_support/port/esp32h2/pmu_param.c b/components/esp_hw_support/port/esp32h2/pmu_param.c
index b15e97b78e..995c02a243 100644
--- a/components/esp_hw_support/port/esp32h2/pmu_param.c
+++ b/components/esp_hw_support/port/esp32h2/pmu_param.c
@@ -22,7 +22,6 @@ static __attribute__((unused)) const char *TAG = "pmu_param";
 #define ARRAY_SIZE(a)   (sizeof(a) / sizeof((a)[0]))
 #endif
 
-//TODO: IDF-6254
 #define PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT() { \
     .dig_power = {          \
         .vdd_spi_pd_en = 0, \
diff --git a/components/esp_hw_support/port/esp32h2/rtc_time.c b/components/esp_hw_support/port/esp32h2/rtc_time.c
index 708fedcb20..395be4dc4a 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_time.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_time.c
@@ -18,7 +18,7 @@
 #include "soc/chip_revision.h"
 #include "esp_private/periph_ctrl.h"
 
-static const char *TAG = "rtc_time";
+__attribute__((unused)) static const char *TAG = "rtc_time";
 
 /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
  * This feature counts the number of XTAL clock cycles within a given number of
@@ -257,12 +257,6 @@ uint64_t rtc_time_get(void)
     return lp_timer_hal_get_cycle_count();
 }
 
-void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
-{
-    // TODO: IDF-6254
-    ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
-}
-
 uint32_t rtc_clk_freq_cal(uint32_t cal_val)
 {
     if (cal_val == 0) {
diff --git a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h
index ba2ede21c1..183f8a79fe 100644
--- a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h
@@ -432,15 +432,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
  */
 uint64_t rtc_time_get(void);
 
-/**
- * @brief Busy loop until next RTC_SLOW_CLK cycle
- *
- * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
- * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
- * one RTC_SLOW_CLK cycle later.
- */
-void rtc_clk_wait_for_slow_cycle(void);
-
 /**
  * @brief Enable the rtc digital 8M clock
  *
@@ -494,7 +485,7 @@ void rtc_clk_apll_enable(bool enable);
  *
  * @return
  *      - 0 Failed
- *      - else Sucess
+ *      - else Success
  */
 uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2);
 
diff --git a/components/esp_hw_support/port/esp32p4/rtc_time.c b/components/esp_hw_support/port/esp32p4/rtc_time.c
index b1a5ae6674..44c1242f4c 100644
--- a/components/esp_hw_support/port/esp32p4/rtc_time.c
+++ b/components/esp_hw_support/port/esp32p4/rtc_time.c
@@ -16,7 +16,7 @@
 #include "esp_rom_sys.h"
 #include "esp_private/periph_ctrl.h"
 
-static const char *TAG = "rtc_time";
+__attribute__((unused)) static const char *TAG = "rtc_time";
 
 /* Calibration of clock frequency is performed using a special feature of TIMG0.
  * This feature counts the number of XTAL clock cycles within a given number of
@@ -214,12 +214,6 @@ uint64_t rtc_time_get(void)
     return lp_timer_hal_get_cycle_count();
 }
 
-void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
-{
-    // TODO: IDF-5781
-    ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
-}
-
 uint32_t rtc_clk_freq_cal(uint32_t cal_val)
 {
     if (cal_val == 0) {