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change(esp_phy): fix some wifi power save issues and optimize phy sleep for esp32c5 eco1 and beta5

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This commit is contained in:
Li Shuai 2024-11-09 19:15:29 +08:00
parent e8d96c77a1
commit 2fce894c82
7 changed files with 54 additions and 18 deletions
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2
components/esp_hw_support/linker.lf
View File

@ -48,3 +48,5 @@ archive: libsoc.a
entries:
if PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND:
gpio_periph: GPIO_HOLD_MASK (noflash)
if PM_SLP_IRAM_OPT = y && SOC_TEMP_SENSOR_SUPPORTED = y:
temperature_sensor_periph:temperature_sensor_attributes (noflash)

16
components/esp_hw_support/port/esp32c5/private_include/pmu_param.h
View File

@ -438,7 +438,7 @@ typedef struct pmu_sleep_machine_constant {
} lp;
struct {
uint16_t min_slp_time_us; /* Minimum sleep protection time (unit: microsecond) */
uint16_t clock_domain_sync_time_us; /* The Slow OSC clock domain synchronizes time with the Fast OSC domain, at least 4 slow clock cycles (unit: microsecond) */
uint16_t clock_domain_sync_time_us; /* Synchronizing the rtc clock timer to modem system requires at least 1 us (unit: microsecond) */
uint16_t system_dfs_up_work_time_us; /* System DFS up scaling work time (unit: microsecond) */
uint16_t analog_wait_time_us; /* HP LDO power up wait time (unit: microsecond) */
uint8_t isolate_wait_time_us; /* Waiting for all isolate signals to be ready (unit: microsecond) */
@ -471,19 +471,19 @@ typedef struct pmu_sleep_machine_constant {
}, \
.hp = { \
.min_slp_time_us = 450, \
.clock_domain_sync_time_us = 150, \
.clock_domain_sync_time_us = 2, \
.system_dfs_up_work_time_us = 124, \
.analog_wait_time_us = 154, \
.isolate_wait_time_us = 1, \
.reset_wait_time_us = 1, \
.power_supply_wait_time_us = 2, \
.power_up_wait_time_us = 2, \
.regdma_s2m_work_time_us = 172, \
.regdma_s2a_work_time_us = 480, \
.regdma_m2a_work_time_us = 278, \
.regdma_a2s_work_time_us = 382, \
.regdma_rf_on_work_time_us = 70, \
.regdma_rf_off_work_time_us = 23, \
.regdma_s2m_work_time_us = 275, \
.regdma_s2a_work_time_us = 587, \
.regdma_m2a_work_time_us = 320, \
.regdma_a2s_work_time_us = 494, \
.regdma_rf_on_work_time_us = 60, \
.regdma_rf_off_work_time_us = 25, \
.xtal_wait_stable_time_us = 250, \
.pll_wait_stable_time_us = 300 \
} \

2
components/esp_phy/lib

@ -1 +1 @@
Subproject commit 1e3487dc778d48c15229af05ce0f03f78e15528c
Subproject commit 7114c37cbc163e373e8dd4a7ecfdeacddc9fa8c2

2
components/esp_phy/linker.lf
View File

@ -29,3 +29,5 @@ entries:
phy_init:esp_phy_enable (noflash)
phy_init:esp_phy_disable (noflash)
phy_init:esp_wifi_bt_power_domain_off (noflash)
if PM_SLP_IRAM_OPT = y:
phy_override:phy_get_tsens_value (noflash)

38
components/esp_phy/src/phy_init.c
View File

@ -487,16 +487,38 @@ static bool s_mac_bb_pu = true;
#elif SOC_PM_MODEM_RETENTION_BY_REGDMA
static esp_err_t sleep_retention_wifi_bb_init(void *arg)
{
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C61
#define N_REGS_WIFI_AGC() (121)
#define N_REGS_WIFI_TX() (14)
#define N_REGS_WIFI_NRX() (136)
#define N_REGS_WIFI_BB() (53)
#define N_REGS_WIFI_BRX() (39)
#define N_REGS_WIFI_FE_COEX() (58)
#define N_REGS_WIFI_FE_DATA() (41)
#define N_REGS_WIFI_FE_CTRL() (87)
#elif CONFIG_IDF_TARGET_ESP32C5
#define N_REGS_WIFI_AGC() (126)
#define N_REGS_WIFI_TX() (20)
#define N_REGS_WIFI_NRX() (141)
#define N_REGS_WIFI_BB() (63)
#define N_REGS_WIFI_BRX() (39)
#define N_REGS_WIFI_FE_COEX() (19)
#define N_REGS_WIFI_FE_DATA() (31)
#define N_REGS_WIFI_FE_CTRL() (55)
#endif
const static sleep_retention_entries_config_t bb_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b00, 0x600a7000, 0x600a7000, 121, 0, 0), .owner = BIT(0) | BIT(1) }, /* AGC */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, 14, 0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, 136, 0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, 53, 0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, 58, 0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b00, 0x600a7000, 0x600a7000, N_REGS_WIFI_AGC(), 0, 0), .owner = BIT(0) | BIT(1) }, /* AGC */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, N_REGS_WIFI_TX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, N_REGS_WIFI_NRX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, N_REGS_WIFI_BB(), 0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, N_REGS_WIFI_FE_COEX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
#ifndef SOC_PM_RETENTION_HAS_CLOCK_BUG
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x000a8000, 39, 0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, 41, 0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, 87, 0, 0), .owner = BIT(0) | BIT(1) } /* FE CTRL */
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x600a8000, N_REGS_WIFI_BRX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, N_REGS_WIFI_FE_DATA(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, N_REGS_WIFI_FE_CTRL(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE CTRL */
#endif
#if CONFIG_IDF_TARGET_ESP32C5
[8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b09, 0x600a0c00, 0x600a0c00, 20, 0, 0), .owner = BIT(0) | BIT(1) } /* FE WIFI DATA */
#endif
};
esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB);

10
components/esp_pm/linker.lf
View File

@ -39,6 +39,16 @@ entries:
sleep_modem:modem_domain_pd_allowed (noflash)
sleep_modem:periph_inform_out_light_sleep_overhead (noflash)
sar_periph_ctrl:sar_periph_ctrl_power_disable (noflash)
if SOC_TEMP_SENSOR_SUPPORTED = y:
sar_periph_ctrl_common:temperature_sensor_power_acquire (noflash)
sar_periph_ctrl_common:temperature_sensor_power_release (noflash)
sar_periph_ctrl_common:temperature_sensor_get_raw_value (noflash)
sar_periph_ctrl_common:temp_sensor_get_raw_value (noflash)
regi2c_ctrl:regi2c_saradc_enable (noflash)
regi2c_ctrl:regi2c_saradc_disable (noflash)
if SOC_ADC_SUPPORTED = y:
adc_share_hw_ctrl:adc_apb_periph_claim (noflash)
adc_share_hw_ctrl:adc_apb_periph_free (noflash)
[mapping:esp_system_pm]
archive: libesp_system.a

2
components/esp_wifi/lib

@ -1 +1 @@
Subproject commit 73ba41ad38632ee8e36e5354aa565487fbfb156c
Subproject commit dfbd8b0145a604bcd4c0b57feff18cd1e62197cb