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Merge branch 'bugfix/rmt_hw_issue' into 'master'

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rmt: only use register to control the IDLE state (hardware issue workaround)

See merge request espressif/esp-idf!19344
This commit is contained in:
morris 2022-08-03 17:01:44 +08:00
commit 307d26659e
7 changed files with 21 additions and 20 deletions
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13
components/driver/rmt/rmt_tx.c
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@ -268,8 +268,8 @@ esp_err_t rmt_new_tx_channel(const rmt_tx_channel_config_t *config, rmt_channel_
rmt_ll_tx_set_limit(hal->regs, channel_id, tx_channel->ping_pong_symbols);
// disable carrier modulation by default, can reenable by `rmt_apply_carrier()`
rmt_ll_tx_enable_carrier_modulation(hal->regs, channel_id, false);
// idle level is determind by eof encoder, not set to a fixed value
rmt_ll_tx_fix_idle_level(hal->regs, channel_id, 0, false);
// idle level is determined by register value
rmt_ll_tx_fix_idle_level(hal->regs, channel_id, 0, true);
// always enable tx wrap, both DMA mode and ping-pong mode rely this feature
rmt_ll_tx_enable_wrap(hal->regs, channel_id, true);
@ -662,6 +662,7 @@ static void IRAM_ATTR rmt_tx_do_transaction(rmt_tx_channel_t *tx_chan, rmt_tx_tr
#endif
// turn on the TX machine
portENTER_CRITICAL_ISR(&channel->spinlock);
rmt_ll_tx_fix_idle_level(hal->regs, channel_id, t->flags.eot_level, true);
rmt_ll_tx_start(hal->regs, channel_id);
portEXIT_CRITICAL_ISR(&channel->spinlock);
}
@ -720,9 +721,6 @@ static esp_err_t rmt_tx_disable(rmt_channel_handle_t channel)
int channel_id = channel->channel_id;
portENTER_CRITICAL(&channel->spinlock);
// when this function called, the transaction might be middle-way, the output level when we stop the transmitter is nondeterministic,
// so we fix the idle level temporarily
rmt_ll_tx_fix_idle_level(hal->regs, channel->channel_id, tx_chan->cur_trans ? tx_chan->cur_trans->flags.eot_level : 0, true);
rmt_ll_tx_enable_loop(hal->regs, channel->channel_id, false);
#if SOC_RMT_SUPPORT_TX_ASYNC_STOP
rmt_ll_tx_stop(hal->regs, channel->channel_id);
@ -740,11 +738,6 @@ static esp_err_t rmt_tx_disable(rmt_channel_handle_t channel)
rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_TX_MASK(channel_id));
portEXIT_CRITICAL(&group->spinlock);
portENTER_CRITICAL(&channel->spinlock);
// restore the idle level selection, to be determind by eof symbol
rmt_ll_tx_fix_idle_level(hal->regs, channel_id, 0, false);
portEXIT_CRITICAL(&channel->spinlock);
#if SOC_RMT_SUPPORT_DMA
if (channel->dma_chan) {
gdma_stop(channel->dma_chan);

3
components/esp_gdbstub/src/packet.c
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@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <assert.h>
#include "esp_gdbstub_common.h"
// GDB command input buffer
@ -45,6 +46,8 @@ void esp_gdbstub_send_str(const char *c)
// 'bits'/4 dictates the number of hex chars sent.
void esp_gdbstub_send_hex(int val, int bits)
{
// sanity check, in case the following (i - 4) is a negative value
assert(bits >= 4);
const char *hex_chars = "0123456789abcdef";
for (int i = bits; i > 0; i -= 4) {
esp_gdbstub_send_char(hex_chars[(val >> (i - 4)) & 0xf]);

4
components/esp_hw_support/port/esp32h2/systimer.c
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@ -7,8 +7,8 @@
#include "esp_private/systimer.h"
/**
* @brief systimer's clock source is fixed to XTAL (40MHz), and has a fixed fractional divider (2.5).
* So the resolution of the systimer is 40MHz/2.5 = 16MHz.
* @brief systimer's clock source is fixed to XTAL (32MHz), and has a fixed fractional divider (2.0).
* So the resolution of the systimer is 32MHz/2.0 = 16MHz.
*/
uint64_t systimer_ticks_to_us(uint64_t ticks)

10
components/esp_hw_support/rtc_wdt.c
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@ -78,7 +78,7 @@ static uint32_t get_addr_reg(rtc_wdt_stage_t stage)
} else if (stage == RTC_WDT_STAGE2) {
reg = RTC_CNTL_WDTCONFIG3_REG;
} else {
reg = RTC_CNTL_WDTCONFIG4_REG;
reg = RTC_CNTL_WDTCONFIG4_REG;
}
return reg;
}
@ -98,14 +98,18 @@ esp_err_t rtc_wdt_set_time(rtc_wdt_stage_t stage, unsigned int timeout_ms)
return ESP_OK;
}
esp_err_t rtc_wdt_get_timeout(rtc_wdt_stage_t stage, unsigned int* timeout_ms)
esp_err_t rtc_wdt_get_timeout(rtc_wdt_stage_t stage, unsigned int *timeout_ms)
{
if (stage > 3) {
return ESP_ERR_INVALID_ARG;
}
uint32_t time_tick;
uint32_t rtc_slow_freq = rtc_clk_slow_freq_get_hz();
if (rtc_slow_freq == 0) {
return ESP_ERR_INVALID_STATE;
}
time_tick = READ_PERI_REG(get_addr_reg(stage));
*timeout_ms = time_tick * 1000 / rtc_clk_slow_freq_get_hz();
*timeout_ms = time_tick * 1000 / rtc_slow_freq;
return ESP_OK;
}

4
components/esp_ringbuf/ringbuf.c
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@ -782,7 +782,7 @@ static BaseType_t prvReceiveGeneric(Ringbuffer_t *pxRingbuffer,
portENTER_CRITICAL(&pxRingbuffer->mux);
if (prvCheckItemAvail(pxRingbuffer) == pdTRUE) {
//Item is available for retrieval
BaseType_t xIsSplit;
BaseType_t xIsSplit = pdFALSE;
if (pxRingbuffer->uxRingbufferFlags & rbBYTE_BUFFER_FLAG) {
//Second argument (pxIsSplit) is unused for byte buffers
*pvItem1 = pxRingbuffer->pvGetItem(pxRingbuffer, NULL, xMaxSize, xItemSize1);
@ -836,7 +836,7 @@ static BaseType_t prvReceiveGenericFromISR(Ringbuffer_t *pxRingbuffer,
portENTER_CRITICAL_ISR(&pxRingbuffer->mux);
if(prvCheckItemAvail(pxRingbuffer) == pdTRUE) {
BaseType_t xIsSplit;
BaseType_t xIsSplit = pdFALSE;
if (pxRingbuffer->uxRingbufferFlags & rbBYTE_BUFFER_FLAG) {
//Second argument (pxIsSplit) is unused for byte buffers
*pvItem1 = pxRingbuffer->pvGetItem(pxRingbuffer, NULL, xMaxSize, xItemSize1);

6
components/esp_serial_slave_link/essl_sdio.c
View File

@ -133,7 +133,7 @@ esp_err_t essl_sdio_init(void *arg, uint32_t wait_ms)
{
essl_sdio_context_t* ctx = arg;
esp_err_t err;
uint8_t ioe;
uint8_t ioe = 0;
sdmmc_card_t* card = ctx->card;
err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_ENABLE, &ioe);
@ -159,7 +159,7 @@ esp_err_t essl_sdio_init(void *arg, uint32_t wait_ms)
}
// get interrupt status
uint8_t ie;
uint8_t ie = 0;
err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_INT_ENABLE, &ie);
if (err != ESP_OK) return err;
ESP_LOGD(TAG,"IE: 0x%02x", ie);
@ -171,7 +171,7 @@ esp_err_t essl_sdio_init(void *arg, uint32_t wait_ms)
ESP_LOGD(TAG, "IE: 0x%02x", ie);
// get bus width register
uint8_t bus_width;
uint8_t bus_width = 0;
err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_BUS_WIDTH, &bus_width);
if (err != ESP_OK) return err;
ESP_LOGD(TAG,"BUS_WIDTH: 0x%02x", bus_width);

1
tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c
View File

@ -107,6 +107,7 @@ void ref_clock_init(void)
};
rmt_transmit_config_t trans_config = {
.loop_count = 0, // no loop
.flags.eot_level = 1,
};
TEST_ESP_OK(rmt_transmit(s_rmt_chan, s_rmt_encoder, &data, sizeof(data), &trans_config));