blackbeard420/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf synced 2025-03-08 15:49:08 -05:00
Code Issues Projects Releases Wiki Activity

fix(esp32h4): fix g0 component build

Browse Source
This commit is contained in:
Chen Jichang 2025-03-04 15:30:16 +08:00
parent b16095cf00
commit 30f2578e75
13 changed files with 156 additions and 123 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
components/hal/esp32h4/include/hal/clk_tree_ll.h
View File

@ -9,7 +9,7 @@
#include <stdint.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/rtc.h"
#include "rom/rtc.h"
#include "soc/pcr_struct.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/pmu_reg.h"
@ -17,7 +17,6 @@
#include "soc/regi2c_bbpll.h"
#include "hal/assert.h"
#include "hal/log.h"
#include "esp32h4/rom/rtc.h"
#include "hal/misc.h"
//TODO: [ESP32H4] IDF-12285 inherited from verification branch, need check
@ -309,7 +308,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
/* Configure 480M PLL */
switch (xtal_freq_mhz) {
case RTC_XTAL_FREQ_32M:
case SOC_XTAL_FREQ_32M:
default:
div_ref = 0;
div7_0 = 8;

88
components/hal/esp32h4/include/hal/gpio_ll.h
View File

@ -20,8 +20,8 @@
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/lp_aon_struct.h"
#include "soc/lp_io_struct.h"
#include "soc/pmu_struct.h"
#include "soc/io_mux_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
@ -41,36 +41,28 @@ extern "C" {
#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0))
#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1))
#define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTERRUPT_PRO_SOURCE
/**
* @brief Get the configuration for an IO
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
* @param pu Pull-up enabled or not
* @param pd Pull-down enabled or not
* @param ie Input enabled or not
* @param oe Output enabled or not
* @param od Open-drain enabled or not
* @param drv Drive strength value
* @param fun_sel IOMUX function selection value
* @param sig_out Outputting peripheral signal index
* @param slp_sel Pin sleep mode enabled or not
* @param[out] io_config Pointer to the structure that saves the specific IO configuration
*/
static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv,
uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, gpio_io_config_t *io_config)
{
uint32_t bit_mask = 1 << gpio_num;
uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]);
*pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
*pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;
*ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S;
*oe = (hw->enable.val & bit_mask) >> gpio_num;
*od = hw->pinn[gpio_num].pinn_pad_driver;
*drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
*sig_out = hw->funcn_out_sel_cfg[gpio_num].funcn_out_sel;
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
io_config->pu = IO_MUX.gpio[gpio_num].fun_wpu;
io_config->pd = IO_MUX.gpio[gpio_num].fun_wpd;
io_config->ie = IO_MUX.gpio[gpio_num].fun_ie;
io_config->oe = (hw->enable.val & (1 << gpio_num)) >> gpio_num;
io_config->oe_ctrl_by_periph = !(hw->funcn_out_sel_cfg[gpio_num].oe_sel);
io_config->oe_inv = hw->funcn_out_sel_cfg[gpio_num].oe_inv_sel;
io_config->od = hw->pinn[gpio_num].pinn_pad_driver;
io_config->drv = (gpio_drive_cap_t)IO_MUX.gpio[gpio_num].fun_drv;
io_config->fun_sel = IO_MUX.gpio[gpio_num].mcu_sel;
io_config->sig_out = hw->funcn_out_sel_cfg[gpio_num].out_sel;
io_config->slp_sel = IO_MUX.gpio[gpio_num].slp_sel;
}
/**
@ -469,44 +461,16 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
}
/**
* @brief Set pad input to a peripheral signal through the IOMUX.
* @brief Configure peripheral signal input whether to bypass GPIO matrix.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number of the pad.
* @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``.
* @param from_gpio_matrix True if not to bypass GPIO matrix, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal_idx, bool from_gpio_matrix)
{
REG_CLR_BIT(GPIO_FUNC0_IN_SEL_CFG_REG + signal_idx * 4, GPIO_SIG0_IN_SEL);
PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4));
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
// Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO27_REG || pin_name == IO_MUX_GPIO32_REG) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
}
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Control the pin in the IOMUX
*
* @param bmap write mask of control value
* @param val Control value
* @param shift write mask shift of control value
*/
static inline __attribute__((always_inline)) void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
{
SET_PERI_REG_BITS(PIN_CTRL, bmap, val, shift);
hw->func_in_sel_cfg[signal_idx].sig_in_sel = from_gpio_matrix;
}
/**
@ -530,16 +494,14 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f
* @brief Set peripheral output to an GPIO pad through the IOMUX.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num gpio_num GPIO number of the pad.
* @param func The function number of the peripheral pin to output pin.
* One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``.
* @param gpio_num GPIO number of the pad.
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->funcn_out_sel_cfg[gpio_num].funcn_oe_sel = 0;
hw->funcn_out_sel_cfg[gpio_num].funcn_oe_inv_sel = oen_inv;
gpio_ll_func_sel(hw, gpio_num, func);
hw->funcn_out_sel_cfg[gpio_num].oe_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
hw->funcn_out_sel_cfg[gpio_num].oe_sel = !ctrl_by_periph;
}
/**

4
components/riscv/include/esp_private/interrupt_clic.h
View File

@ -56,9 +56,9 @@ extern "C" {
#define INTTHRESH_STANDARD 0
#define MINTSTATUS_CSR 0x346
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4
/* The ESP32-C5 (MP) and C61 use the standard CLIC specification, for example, it defines the mintthresh CSR */
/* The ESP32-C5 (MP), C61 and H4 use the standard CLIC specification, for example, it defines the mintthresh CSR */
#define INTTHRESH_STANDARD 1
#define MINTSTATUS_CSR 0xFB1
#define MINTTHRESH_CSR 0x347

72
components/soc/esp32h4/include/soc/periph_defs.h Normal file
View File

@ -0,0 +1,72 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/interrupts.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
/* HP peripherals */
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_UHCI0_MODULE,
PERIPH_RMT_MODULE,
PERIPH_PCNT_MODULE,
PERIPH_SPI_MODULE, //SPI1
PERIPH_SPI2_MODULE, //SPI2
PERIPH_TWAI0_MODULE,
PERIPH_TWAI1_MODULE,
PERIPH_RNG_MODULE,
PERIPH_AES_MODULE,
PERIPH_SHA_MODULE,
PERIPH_ECC_MODULE,
PERIPH_HMAC_MODULE,
PERIPH_DS_MODULE,
PERIPH_SDIO_SLAVE_MODULE,
PERIPH_GDMA_MODULE,
PERIPH_MCPWM0_MODULE,
PERIPH_MCPWM1_MODULE,
PERIPH_ETM_MODULE,
PERIPH_PARLIO_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_SARADC_MODULE,
PERIPH_TEMPSENSOR_MODULE,
PERIPH_REGDMA_MODULE,
PERIPH_ASSIST_DEBUG_MODULE,
/* LP peripherals */
PERIPH_LP_I2C0_MODULE,
PERIPH_LP_UART0_MODULE,
/* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */
PERIPH_BT_MODULE,
PERIPH_IEEE802154_MODULE,
PERIPH_COEX_MODULE,
PERIPH_PHY_MODULE,
PERIPH_ANA_I2C_MASTER_MODULE,
PERIPH_MODEM_ETM_MODULE,
PERIPH_MODEM_ADC_COMMON_FE_MODULE,
PERIPH_MODULE_MAX
/* !!! Don't append soc modules here !!! */
} periph_module_t;
#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))
#ifdef __cplusplus
}
#endif

18
components/soc/esp32h4/register/soc/gpio_struct.h
View File

@ -641,12 +641,12 @@ typedef union {
} gpio_func_in_sel_cfg_reg_t;
/** Group: Output Configuration Registers */
/** Type of funcn_out_sel_cfg register
/** Type of out_sel_cfg register
* Configuration register for GPIOn output
*/
typedef union {
struct {
/** funcn_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
/** out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIOn.
* 0: Select signal 0
@ -661,25 +661,25 @@ typedef union {
* For the detailed signal list, see Table .
* "
*/
uint32_t funcn_out_sel:9;
/** funcn_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
uint32_t out_sel:9;
/** out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.
* 0: Not invert
* 1: Invert
*/
uint32_t funcn_out_inv_sel:1;
/** funcn_oe_sel : R/W; bitpos: [10]; default: 0;
uint32_t out_inv_sel:1;
/** oe_sel : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.
* 0: Use output enable signal from peripheral.
* 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG.
*/
uint32_t funcn_oe_sel:1;
/** funcn_oe_inv_sel : R/W; bitpos: [11]; default: 0;
uint32_t oe_sel:1;
/** oe_inv_sel : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.
* 0: Not invert
* 1: Invert
*/
uint32_t funcn_oe_inv_sel:1;
uint32_t oe_inv_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;

4
components/soc/esp32h4/register/soc/huk_struct.h
View File

@ -149,10 +149,10 @@ typedef union {
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
/** conti : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
uint32_t continue:1;
uint32_t conti:1;
uint32_t reserved_2:30;
};
uint32_t val;

66
components/soc/esp32h4/register/soc/io_mux_struct.h
View File

@ -16,96 +16,96 @@ extern "C" {
*/
typedef union {
struct {
/** mux_gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
/** mcu_oe : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of GPIOn in sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_mcu_oe:1;
/** mux_gpion_slp_sel : R/W; bitpos: [1]; default: 0;
uint32_t mcu_oe:1;
/** slp_sel : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for GPIOn.
* 0: Not enter
* 1: Enter
*/
uint32_t mux_gpion_slp_sel:1;
/** mux_gpion_mcu_wpd : R/W; bitpos: [2]; default: 0;
uint32_t slp_sel:1;
/** mcu_wpd : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of GPIOn in sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_mcu_wpd:1;
/** mux_gpion_mcu_wpu : R/W; bitpos: [3]; default: 0;
uint32_t mcu_wpd:1;
/** mcu_wpu : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of GPIOn during sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_mcu_wpu:1;
/** mux_gpion_mcu_ie : R/W; bitpos: [4]; default: 0;
uint32_t mcu_wpu:1;
/** mcu_ie : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of GPIOn during sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_mcu_ie:1;
/** mux_gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0;
uint32_t mcu_ie:1;
/** mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of GPIOn during sleep mode.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
uint32_t mux_gpion_mcu_drv:2;
/** mux_gpion_fun_wpd : R/W; bitpos: [7]; default: 0;
uint32_t mcu_drv:2;
/** fun_wpd : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_fun_wpd:1;
/** mux_gpion_fun_wpu : R/W; bitpos: [8]; default: 0;
uint32_t fun_wpd:1;
/** fun_wpu : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_fun_wpu:1;
/** mux_gpion_fun_ie : R/W; bitpos: [9]; default: 0;
uint32_t fun_wpu:1;
/** fun_ie : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_fun_ie:1;
/** mux_gpion_fun_drv : R/W; bitpos: [11:10]; default: 2;
uint32_t fun_ie:1;
/** fun_drv : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of GPIOn.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
uint32_t mux_gpion_fun_drv:2;
/** mux_gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1;
uint32_t fun_drv:2;
/** mcu_sel : R/W; bitpos: [14:12]; default: 1;
* Configures to select IO MUX function for this signal.
* 0: Select Function 0
* 1: Select Function 1
* ......
*/
uint32_t mux_gpion_mcu_sel:3;
/** mux_gpion_filter_en : R/W; bitpos: [15]; default: 0;
uint32_t mcu_sel:3;
/** filter_en : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_filter_en:1;
/** mux_gpion_hys_en : R/W; bitpos: [16]; default: 0;
uint32_t filter_en:1;
/** hys_en : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* IO_MUX_GPIOn_HYS_SEL is set to 1.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_hys_en:1;
/** mux_gpion_hys_sel : R/W; bitpos: [17]; default: 0;
uint32_t hys_en:1;
/** hys_sel : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for GPIOn.
* 0: Choose the output enable signal of eFuse
* 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN
*/
uint32_t mux_gpion_hys_sel:1;
uint32_t hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
@ -129,15 +129,15 @@ typedef union {
typedef struct {
volatile io_mux_gpion_reg_t mux_gpion[40];
volatile io_mux_gpion_reg_t gpio[40];
uint32_t reserved_0a0[87];
volatile io_mux_date_reg_t mux_date;
} io_dev_t;
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern io_dev_t IO_MUX;
extern io_mux_dev_t IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_dev_t) == 0x200, "Invalid size of io_dev_t structure");
_Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");
#endif
#ifdef __cplusplus

8
components/soc/esp32h4/register/soc/keymng_struct.h
View File

@ -221,13 +221,13 @@ typedef union {
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
* Write 1 to conti Key Manager operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
/** conti : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
uint32_t continue:1;
uint32_t conti:1;
uint32_t reserved_2:30;
};
uint32_t val;
@ -349,7 +349,7 @@ typedef struct {
volatile keymng_int_st_reg_t int_st;
volatile keymng_int_ena_reg_t int_ena;
volatile keymng_int_clr_reg_t int_clr;
volatile keymng_static_reg_t static;
volatile keymng_static_reg_t static_cfg;
volatile keymng_lock_reg_t lock;
volatile keymng_conf_reg_t conf;
volatile keymng_start_reg_t start;

0
components/soc/esp32h4/register/soc/lp_peri_reg.h → components/soc/esp32h4/register/soc/lpperi_reg.h
View File

0
components/soc/esp32h4/register/soc/lp_peri_struct.h → components/soc/esp32h4/register/soc/lpperi_struct.h
View File

10
components/soc/esp32h4/register/soc/sha_struct.h
View File

@ -73,10 +73,10 @@ typedef union {
*/
typedef union {
struct {
/** continue : WO; bitpos: [0]; default: 0;
/** conti : WO; bitpos: [0]; default: 0;
* Continue typical sha.
*/
uint32_t continue:1;
uint32_t conti:1;
uint32_t reserved_1:31;
};
uint32_t val;
@ -196,7 +196,7 @@ typedef struct {
uint32_t reserved_004[2];
volatile sha_dma_block_num_reg_t dma_block_num;
volatile sha_start_reg_t start;
volatile sha_continue_reg_t continue;
volatile sha_continue_reg_t conti;
volatile sha_busy_reg_t busy;
volatile sha_dma_start_reg_t dma_start;
volatile sha_dma_continue_reg_t dma_continue;
@ -205,8 +205,8 @@ typedef struct {
volatile sha_date_reg_t date;
volatile sha_dma_rx_reset_reg_t dma_rx_reset;
uint32_t reserved_034[3];
volatile uint32_t 2_sm_3_h[16];
volatile uint32_t 2_sm_3_m[32];
volatile uint32_t h[16];
volatile uint32_t m[32];
} sha_dev_t;
extern sha_dev_t SHA;

2
components/soc/esp32h4/register/soc/timer_group_reg.h
View File

@ -11,7 +11,7 @@
extern "C" {
#endif
#define DR_REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define DR_REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i)*0x1000)
/** TIMG_T0CONFIG_REG register
* Timer 0 configuration register

2
components/soc/include/soc/rtc_cntl_periph.h
View File

@ -30,7 +30,7 @@
#endif
// TODO: IDF-5645
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4
#include "soc/lp_analog_peri_reg.h"
#include "soc/lp_clkrst_reg.h"
#include "soc/lp_clkrst_struct.h"