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https://github.com/espressif/esp-idf
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doc(spi_flash): hide unsupported optional features
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Xiao Xufeng
Michael (XIAO Xufeng)
parent
c32a56fe3b
commit
31201cc947
@ -101,7 +101,6 @@ menu "Bootloader config"
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config BOOTLOADER_FLASH_XMC_SUPPORT
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bool "Enable the support for flash chips of XMC (READ DOCS FIRST)"
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default y
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depends on !IDF_ENV_BRINGUP
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help
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Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow.
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XMC chips will be forbidden to be used, when this option is disabled.
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@ -119,7 +118,7 @@ menu "Bootloader config"
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config BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
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bool
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default y if ESPTOOLPY_OCT_FLASH && SPI_FLASH_32BIT_ADDRESS
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default y if ESPTOOLPY_OCT_FLASH && BOOTLOADER_FLASH_32BIT_ADDR
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default n
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endmenu
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@ -24,6 +24,4 @@ CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_CACHE CONFIG_SECURE_FLASH_
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# Secure Boot Scheme
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CONFIG_SECURE_BOOT_ENABLED CONFIG_SECURE_BOOT_V1_ENABLED
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CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
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CONFIG_SPI_FLASH_QUAD_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
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CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
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@ -109,7 +109,7 @@ extern const bootloader_qio_info_t __attribute__((weak)) bootloader_flash_qe_sup
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*/
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esp_err_t __attribute__((weak)) bootloader_flash_unlock(void);
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#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
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#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
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/**
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* @brief Enable 32bits address flash(larger than 16MB) can map to cache.
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*
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@ -415,7 +415,7 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
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return spi_to_esp_err(rc);
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}
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#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
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#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
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void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t flash_mode)
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{
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esp_rom_opiflash_spi0rd_t cache_rd = {};
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@ -220,7 +220,7 @@ static esp_err_t bootloader_init_spi_flash(void)
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#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
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bootloader_enable_qio_mode();
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#endif
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#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
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#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
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bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode());
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#endif
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print_flash_info(&bootloader_image_hdr);
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@ -28,28 +28,29 @@ Some features are not supported on all ESP chips and Flash chips. You can check
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Auto Suspend & Resume
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---------------------
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This feature is only supported on ESP32-C3 for now.
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The support for ESP32-S3, ESP32-C2 may be added in the future.
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.. only:: esp32c3
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You can refer to :ref:`auto-suspend` for more information about this feature. The support list is as follows.
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ESP Chips List:
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1. ESP32C3
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Flash Chips List:
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List of Flash chips that support this feature:
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1. XM25QxxC series.
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.. attention::
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There are multiple limitations about the auto-suspend feature, please do read :ref:`auto-suspend` for more information before you enable this feature.
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Flash unique ID
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---------------
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This feature is supported on all Espressif chips.
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Unique ID is not flash id, which means flash has 64-Bit unique ID for each device. The instruction to read the unique ID (4Bh) accesses a factory-set read-only 64-bit number that is unique to each flash device. This ID number helps you to recognize each single device. Not all flash vendors support this feature. If you try to read the unique ID on a chip which does not have this feature, the behavior is not determined. The support list is as follows.
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ESP Chips Lists:
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ALL
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Flash Chips List:
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List of Flash chips that support this feature:
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1. ISSI
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2. GD
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@ -62,6 +63,12 @@ Flash Chips List:
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High performance mode
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---------------------
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This featuer is only supported on ESP32-S3 for now.
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The support for ESP32-S2, ESP32-C3 may be added in the future.
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.. only:: esp32s3
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.. note::
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This section is provided for Dual mode (DOUT/DIO) and Quad mode (QIO/QOUT) flash chips. Octal flash used on ESP-chips support High performance mode by default so far, you can refer to the octal flash support list below.
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@ -102,12 +109,6 @@ Check whether the bootloader supports `DC Aware` in the following way:
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- For versions below v4.4.4, the bootloader doesn't support `DC Aware`.
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ESP Chips List:
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1. ESP32S3
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(The SW support for other chips haven't been done yet)
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.. _hpm_dc_support_list:
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Quad Flash HPM support list
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@ -118,7 +119,6 @@ Flash chips that don't need HPM-DC:
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1. GD25Q64C (ID: 0xC84017)
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2. GD25Q32C (ID: 0xC84016)
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3. ZB25VQ32B (ID: 0x5E4016)
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4. GD25LQ255E (ID: 0xC86019)
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Following flash chips also have HPM feature, but requires the bootloader to support `DC Aware`:
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@ -130,6 +130,8 @@ Following flash chips also have HPM feature, but requires the bootloader to supp
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OPI flash support
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-----------------
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This feature is only supporetd on ESP32-S3 for now.
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OPI flash means that the flash chip supports octal peripheral interface, which has octal I/O pins. Different octal flash has different configurations and different commands. Hence, it is necessary to carefully check the support list.
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.. only:: esp32s3
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@ -138,24 +140,19 @@ OPI flash means that the flash chip supports octal peripheral interface, which h
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To know how to configure menuconfig for a board with different Flash and PSRAM, please refer to the :ref:`SPI Flash and External SPI RAM Configuration <flash-psram-configuration>`
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ESP Chips List:
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1. ESP32S3
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Flash Chips List:
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List of Flash chips that support this feature:
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1. MX25UM25645G
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2. MX25UM12345G
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32-bit Address Flash Chips
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--------------------------
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This feature is supported on all Espressif chips (with various restrictions to application).
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Most NOR flash chips used by Espressif chips use 24-bits address, which can cover 16 MBytes memory. However, for larger memory (usually equal to or larger than 16 MBytes), flash uses a 32-bits address to address larger memory. Regretfully, 32-bits address chips have vendor-specific commands, so we need to support the chips one by one.
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ESP Chips List:
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ALL ESP Chips support this.
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Flash Chips List:
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List of Flash chips that support this feature:
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1. W25Q256
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2. GD25Q256
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