Merge branch 'refactor/support_esp32c5_beta3_mp_coexistence' into 'master'

refactor(esp32c5): support esp32c5 beta3 & mp coexistence

See merge request espressif/esp-idf!29248

.gitlab/ci/pre_check.yml

@@ -75,7 +75,7 @@ check_chip_support_components:
     expire_in: 1 week
   script:
     - python tools/ci/check_soc_headers_leak.py
-    - find ${IDF_PATH}/components/soc/*/include/soc/ -name "*_struct.h" -print0 | xargs -0 -n1 ./tools/ci/check_soc_struct_headers.py
+    - find ${IDF_PATH}/components/soc/**/include/soc/ -name "*_struct.h" -print0 | xargs -0 -n1 ./tools/ci/check_soc_struct_headers.py
     - tools/ci/check_esp_memory_utils_headers.sh
 
 check_esp_err_to_name:

Kconfig

@@ -119,6 +119,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
         select FREERTOS_UNICORE
         select IDF_TARGET_ARCH_RISCV
 
+    # TODO: IDF-9197
     choice IDF_TARGET_ESP32C5_VERSION
         prompt "ESP32-C5 version"
         depends on IDF_TARGET_ESP32C5
@@ -132,6 +133,11 @@ mainmenu "Espressif IoT Development Framework Configuration"
             bool
             prompt "ESP32-C5 beta3"
             select ESPTOOLPY_NO_STUB
+
+        config IDF_TARGET_ESP32C5_MP_VERSION
+            bool
+            prompt "ESP32-C5 MP"
+            select ESPTOOLPY_NO_STUB
     endchoice
 
     config IDF_TARGET_ESP32P4
@@ -159,7 +165,8 @@ mainmenu "Espressif IoT Development Framework Configuration"
         default 0x000D if IDF_TARGET_ESP32C6
         default 0x0010 if IDF_TARGET_ESP32H2
         default 0x0012 if IDF_TARGET_ESP32P4
-        default 0x0011 if IDF_TARGET_ESP32C5
+        default 0x0011 if IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32C5_BETA3_VERSION  # TODO: IDF-9197
+        default 0x0017 if IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32C5_MP_VERSION     # TODO: IDF-9197
         default 0xFFFF
 
 

components/bootloader/subproject/main/CMakeLists.txt

@@ -1,10 +1,18 @@
 idf_component_register(SRCS "bootloader_start.c"
                     REQUIRES bootloader bootloader_support)
 
-idf_build_get_property(target IDF_TARGET)
-set(scripts "ld/${target}/bootloader.ld")
+if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
+    set(target_folder "esp32c5/beta3")
+elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
+    set(target_folder "esp32c5/mp")
+else()
+    set(target_folder "${target}")
+endif()
 
-list(APPEND scripts "ld/${target}/bootloader.rom.ld")
+idf_build_get_property(target IDF_TARGET)
+set(scripts "ld/${target_folder}/bootloader.ld")
+
+list(APPEND scripts "ld/${target_folder}/bootloader.rom.ld")
 target_linker_script(${COMPONENT_LIB} INTERFACE "${scripts}")
 
 target_link_libraries(${COMPONENT_LIB} INTERFACE "-u bootloader_hooks_include")

components/bootloader_support/include/esp_app_format.h

@@ -8,6 +8,9 @@
 #include <inttypes.h>
 #include "esp_assert.h"
 
+// TODO: IDF-9197
+#include "sdkconfig.h"
+
 /**
  * @brief ESP chip ID
  *
@@ -21,7 +24,11 @@ typedef enum {
     ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
     ESP_CHIP_ID_ESP32H2 = 0x0010, /*!< chip ID: ESP32-H2 */
     ESP_CHIP_ID_ESP32P4 = 0x0012, /*!< chip ID: ESP32-P4 */
-    ESP_CHIP_ID_ESP32C5 = 0x0011, /*!< chip ID: ESP32-C5 */
+#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION  // TODO: IDF-9197
+    ESP_CHIP_ID_ESP32C5 = 0x0011, /*!< chip ID: ESP32-C5 beta3 (MPW)*/
+#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+    ESP_CHIP_ID_ESP32C5 = 0x0017, /*!< chip ID: ESP32-C5 MP */
+#endif
     ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
 } __attribute__((packed)) esp_chip_id_t;
 

components/esp_hw_support/include/esp_chip_info.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,7 +27,11 @@ typedef enum {
     CHIP_ESP32C2 = 12, //!< ESP32-C2
     CHIP_ESP32C6 = 13, //!< ESP32-C6
     CHIP_ESP32H2 = 16, //!< ESP32-H2
-    CHIP_ESP32C5 = 17, //!< ESP32-C5 beta3 TODO: [ESP32-C5] update when MP supported
+#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION  // TODO: IDF-9197
+    CHIP_ESP32C5 = 17, //!< ESP32-C5 beta3 (MPW)
+#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+    CHIP_ESP32C5 = 23, //!< ESP32-C5 MP
+#endif
     CHIP_ESP32P4 = 18, //!< ESP32-P4
     CHIP_POSIX_LINUX = 999, //!< The code is running on POSIX/Linux simulator
 } esp_chip_model_t;

components/esp_rom/CMakeLists.txt

@@ -1,6 +1,15 @@
 idf_build_get_property(target IDF_TARGET)
 
-set(include_dirs "include" "include/${target}")
+# TODO: IDF-9197
+if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
+    set(target_folder "esp32c5/beta3/esp32c5")
+elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
+    set(target_folder "esp32c5/mp/esp32c5")
+else()
+    set(target_folder "${target}")
+endif()
+
+set(include_dirs "include" "include/${target_folder}")
 
 set(private_required_comp "")
 
@@ -12,7 +21,10 @@ if(target STREQUAL "linux")
                         "${target}/esp_rom_md5.c"
                         "${target}/esp_rom_efuse.c")
 else()
-    list(APPEND include_dirs "${target}")
+    list(APPEND include_dirs "${target_folder}")
+    if(CONFIG_IDF_TARGET_ESP32C5)
+        list(APPEND include_dirs "include/${target_folder}/..")
+    endif()
     list(APPEND sources "patches/esp_rom_crc.c"
                         "patches/esp_rom_sys.c"
                         "patches/esp_rom_uart.c"
@@ -67,7 +79,7 @@ set(ld_folder "ld")
 # Append a target linker script at the target-specific path,
 # only the 'name' part is different for each script
 function(rom_linker_script name)
-    target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/${ld_folder}/${target}.rom.${name}.ld")
+    target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.${name}.ld")
 endfunction()
 
 if(target STREQUAL "linux")
@@ -79,7 +91,7 @@ if(target STREQUAL "linux")
         target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-integer-overflow -Wno-shift-count-overflow)
     endif()
 else()
-    target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/${ld_folder}/${target}.rom.ld")
+    target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.ld")
     rom_linker_script("api")
 
     if(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB)

components/esp_rom/esp32c5/Kconfig.soc_caps.in

@@ -3,78 +3,10 @@
 # using gen_soc_caps_kconfig.py, do not edit manually
 #####################################################
 
-config ESP_ROM_HAS_CRC_LE
-    bool
-    default y
+if IDF_TARGET_ESP32C5_BETA3_VERSION
+    source "$IDF_PATH/components/esp_rom/esp32c5/beta3/esp32c5/Kconfig.soc_caps.in"
+endif
 
-config ESP_ROM_HAS_CRC_BE
-    bool
-    default y
-
-config ESP_ROM_HAS_JPEG_DECODE
-    bool
-    default y
-
-config ESP_ROM_UART_CLK_IS_XTAL
-    bool
-    default y
-
-config ESP_ROM_USB_SERIAL_DEVICE_NUM
-    int
-    default 3
-
-config ESP_ROM_HAS_RETARGETABLE_LOCKING
-    bool
-    default y
-
-config ESP_ROM_GET_CLK_FREQ
-    bool
-    default y
-
-config ESP_ROM_HAS_RVFPLIB
-    bool
-    default y
-
-config ESP_ROM_HAS_HAL_WDT
-    bool
-    default y
-
-config ESP_ROM_HAS_HAL_SYSTIMER
-    bool
-    default y
-
-config ESP_ROM_HAS_HEAP_TLSF
-    bool
-    default y
-
-config ESP_ROM_TLSF_CHECK_PATCH
-    bool
-    default y
-
-config ESP_ROM_HAS_LAYOUT_TABLE
-    bool
-    default y
-
-config ESP_ROM_HAS_SPI_FLASH
-    bool
-    default y
-
-config ESP_ROM_WITHOUT_REGI2C
-    bool
-    default y
-
-config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT
-    bool
-    default y
-
-config ESP_ROM_WDT_INIT_PATCH
-    bool
-    default y
-
-config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
-    bool
-    default y
-
-config ESP_ROM_USB_OTG_NUM
-    int
-    default -1
+if IDF_TARGET_ESP32C5_MP_VERSION
+    source "$IDF_PATH/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in"
+endif

components/esp_rom/esp32c5/beta3/esp32c5/Kconfig.soc_caps.in

@@ -0,0 +1,80 @@
+#####################################################
+# This file is auto-generated from SoC caps
+# using gen_soc_caps_kconfig.py, do not edit manually
+#####################################################
+
+config ESP_ROM_HAS_CRC_LE
+    bool
+    default y
+
+config ESP_ROM_HAS_CRC_BE
+    bool
+    default y
+
+config ESP_ROM_HAS_JPEG_DECODE
+    bool
+    default y
+
+config ESP_ROM_UART_CLK_IS_XTAL
+    bool
+    default y
+
+config ESP_ROM_USB_SERIAL_DEVICE_NUM
+    int
+    default 3
+
+config ESP_ROM_HAS_RETARGETABLE_LOCKING
+    bool
+    default y
+
+config ESP_ROM_GET_CLK_FREQ
+    bool
+    default y
+
+config ESP_ROM_HAS_RVFPLIB
+    bool
+    default y
+
+config ESP_ROM_HAS_HAL_WDT
+    bool
+    default y
+
+config ESP_ROM_HAS_HAL_SYSTIMER
+    bool
+    default y
+
+config ESP_ROM_HAS_HEAP_TLSF
+    bool
+    default y
+
+config ESP_ROM_TLSF_CHECK_PATCH
+    bool
+    default y
+
+config ESP_ROM_HAS_LAYOUT_TABLE
+    bool
+    default y
+
+config ESP_ROM_HAS_SPI_FLASH
+    bool
+    default y
+
+config ESP_ROM_WITHOUT_REGI2C
+    bool
+    default y
+
+config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT
+    bool
+    default y
+
+config ESP_ROM_WDT_INIT_PATCH
+    bool
+    default y
+
+config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
+    bool
+    default y
+
+config ESP_ROM_USB_OTG_NUM
+    int
+    default -1

components/esp_rom/esp32c5/beta3/esp32c5/esp_rom_caps.h

@@ -0,0 +1,27 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define ESP_ROM_HAS_CRC_LE                  (1) // ROM CRC library supports Little Endian
+#define ESP_ROM_HAS_CRC_BE                  (1) // ROM CRC library supports Big Endian
+#define ESP_ROM_HAS_JPEG_DECODE             (1) // ROM has JPEG decode library
+#define ESP_ROM_UART_CLK_IS_XTAL            (1) // UART clock source is selected to XTAL in ROM
+#define ESP_ROM_USB_SERIAL_DEVICE_NUM       (3) // UART uses USB_SERIAL_JTAG port in ROM.
+#define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
+#define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
+#define ESP_ROM_HAS_RVFPLIB                 (1) // ROM has the rvfplib
+#define ESP_ROM_HAS_HAL_WDT                 (1) // ROM has the implementation of Watchdog HAL driver
+#define ESP_ROM_HAS_HAL_SYSTIMER            (1) // ROM has the implementation of Systimer HAL driver
+#define ESP_ROM_HAS_HEAP_TLSF               (1) // ROM has the implementation of the tlsf and multi-heap library
+#define ESP_ROM_TLSF_CHECK_PATCH            (1) // ROM does not contain the patch of tlsf_check_pool()
+#define ESP_ROM_HAS_LAYOUT_TABLE            (1) // ROM has the layout table
+#define ESP_ROM_HAS_SPI_FLASH               (1) // ROM has the implementation of SPI Flash driver
+#define ESP_ROM_WITHOUT_REGI2C              (1) // ROM has no regi2c APIs
+#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT    (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions)
+#define ESP_ROM_WDT_INIT_PATCH              (1) // ROM version does not configure the clock
+#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
+#define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.heap.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.heap.ld for esp32c5
  *
  *

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.ld for esp32c5
  *
  *
@@ -575,4 +580,3 @@ slc_reattach = 0x40000c64;
 slc_send_to_host_chain = 0x40000c68;
 slc_set_host_io_max_window = 0x40000c6c;
 slc_to_host_chain_recycle = 0x40000c70;
-

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.libgcc.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.libgcc.ld for esp32c5
  *
  *
@@ -112,4 +117,3 @@ __umodsi3 = 0x400009d0;
 __unorddf2 = 0x400009d4;
 __extenddftf2 = 0x400009d8;
 __trunctfdf2 = 0x400009dc;
-

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.newlib-normal.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.newlib-normal.ld for esp32c5
  *
  *
@@ -34,4 +39,3 @@ vsnprintf = 0x40000614;
 vsniprintf = 0x40000618;
 sscanf = 0x4000061c;
 siscanf = 0x40000620;
-

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.newlib.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.newlib.ld for esp32c5
  *
  *
@@ -92,4 +97,3 @@ __swsetup_r = 0x400005cc;
 /* Data (.data, .bss, .rodata) */
 syscall_table_ptr = 0x4087ffd4;
 _global_impure_ptr = 0x4087ffd0;
-

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.rvfp.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.rvfp.ld for esp32c5
  *
  *

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.spiflash.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.spiflash.ld for esp32c5
  *
  *
@@ -158,4 +163,3 @@ spi_flash_encryption_hal_prepare = 0x40000380;
 spi_flash_encryption_hal_done = 0x40000384;
 spi_flash_encryption_hal_destroy = 0x40000388;
 spi_flash_encryption_hal_check = 0x4000038c;
-

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.version.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM version variables for esp32c5
  *
  * These addresses should be compatible with any ROM version for this chip.

components/esp_rom/esp32c5/esp_rom_caps.h

@@ -1,27 +1,17 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
-#define ESP_ROM_HAS_CRC_LE                  (1) // ROM CRC library supports Little Endian
-#define ESP_ROM_HAS_CRC_BE                  (1) // ROM CRC library supports Big Endian
-#define ESP_ROM_HAS_JPEG_DECODE             (1) // ROM has JPEG decode library
-#define ESP_ROM_UART_CLK_IS_XTAL            (1) // UART clock source is selected to XTAL in ROM
-#define ESP_ROM_USB_SERIAL_DEVICE_NUM       (3) // UART uses USB_SERIAL_JTAG port in ROM.
-#define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
-#define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
-#define ESP_ROM_HAS_RVFPLIB                 (1) // ROM has the rvfplib
-#define ESP_ROM_HAS_HAL_WDT                 (1) // ROM has the implementation of Watchdog HAL driver
-#define ESP_ROM_HAS_HAL_SYSTIMER            (1) // ROM has the implementation of Systimer HAL driver
-#define ESP_ROM_HAS_HEAP_TLSF               (1) // ROM has the implementation of the tlsf and multi-heap library
-#define ESP_ROM_TLSF_CHECK_PATCH            (1) // ROM does not contain the patch of tlsf_check_pool()
-#define ESP_ROM_HAS_LAYOUT_TABLE            (1) // ROM has the layout table
-#define ESP_ROM_HAS_SPI_FLASH               (1) // ROM has the implementation of SPI Flash driver
-#define ESP_ROM_WITHOUT_REGI2C              (1) // ROM has no regi2c APIs
-#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT    (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions)
-#define ESP_ROM_WDT_INIT_PATCH              (1) // ROM version does not configure the clock
-#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
-#define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
+#include "sdkconfig.h"
+
+// TODO: IDF-9197 This file is created to glob the version specific soc_caps correctly
+
+#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
+#include "beta3/esp32c5/esp_rom_caps.h"   // recursive, condition: IDF_TARGET_ESP32C5_BETA3_VERSION
+#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+#include "mp/esp32c5/esp_rom_caps.h"      // recursive, condition: IDF_TARGET_ESP32C5_MP_VERSION
+#endif

components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in

@@ -0,0 +1,4 @@
+#####################################################
+# This file is auto-generated from SoC caps
+# using gen_soc_caps_kconfig.py, do not edit manually
+#####################################################

components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h

@@ -0,0 +1,7 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/miniz.h

@@ -5,4 +5,4 @@
  */
 
 #warning "{target}/rom/miniz.h is deprecated, please use (#include "miniz.h") instead"
-#include "../../miniz.h"
+#include "../../../../miniz.h"

components/esp_system/ld/ld.cmake

@@ -19,8 +19,16 @@ string(REPLACE "\\n" "\n" TEXT "${PREPROCESSED_LINKER_SCRIPT}")
 file(WRITE "${TARGET}" "${TEXT}")
 ]=])
 
+if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
+    set(target_folder "esp32c5/beta3")
+elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
+    set(target_folder "esp32c5/mp")
+else()
+    set(target_folder "${target}")
+endif()
+
 function(preprocess_linker_file name_in name_out out_path)
-    set(script_in "${CMAKE_CURRENT_LIST_DIR}/${target}/${name_in}")
+    set(script_in "${CMAKE_CURRENT_LIST_DIR}/${target_folder}/${name_in}")
     set(script_out "${CMAKE_CURRENT_BINARY_DIR}/ld/${name_out}")
     set(${out_path} ${script_out} PARENT_SCOPE)
 

components/esptool_py/project_include.cmake

@@ -8,10 +8,12 @@ idf_build_get_property(idf_path IDF_PATH)
 
 set(chip_model ${target})
 
-# TODO: [ESP32C5] remove this 'if' block when esp32C5 beta3 is no longer supported
+# TODO: [ESP32C5] IDF-9197 remove this 'if' block when esp32C5 beta3 is no longer supported
 if(target STREQUAL "esp32c5")
     if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
         set(chip_model esp32c5beta3)
+    elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
+        set(chip_model esp32c5)
     endif()
 endif()
 

components/soc/CMakeLists.txt

@@ -1,143 +1,151 @@
 idf_build_get_property(target IDF_TARGET)
 
+if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
+    set(target_folder "esp32c5/beta3")
+elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
+    set(target_folder "esp32c5/mp")
+else()
+    set(target_folder "${target}")
+endif()
+
 # On Linux the soc component is a simple wrapper, without much functionality
 if(NOT ${target} STREQUAL "linux")
     set(srcs "lldesc.c"
              "dport_access_common.c"
-             "${target}/interrupts.c"
-             "${target}/gpio_periph.c"
-             "${target}/uart_periph.c")
+             "${target_folder}/interrupts.c"
+             "${target_folder}/gpio_periph.c"
+             "${target_folder}/uart_periph.c")
 endif()
 
-set(includes "include" "${target}")
+set(includes "include" "${target_folder}")
 
-if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target}/include")
-    list(APPEND includes "${target}/include")
+if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/include")
+    list(APPEND includes "${target_folder}/include")
 endif()
 
 if(target STREQUAL "esp32")
-    list(APPEND srcs "${target}/dport_access.c")
+    list(APPEND srcs "${target_folder}/dport_access.c")
 endif()
 
 if(CONFIG_SOC_ADC_SUPPORTED)
-    list(APPEND srcs "${target}/adc_periph.c")
+    list(APPEND srcs "${target_folder}/adc_periph.c")
 endif()
 
 if(CONFIG_SOC_ANA_CMPR_SUPPORTED)
-    list(APPEND srcs "${target}/ana_cmpr_periph.c")
+    list(APPEND srcs "${target_folder}/ana_cmpr_periph.c")
 endif()
 
 if(CONFIG_SOC_DEDICATED_GPIO_SUPPORTED)
-    list(APPEND srcs "${target}/dedic_gpio_periph.c")
+    list(APPEND srcs "${target_folder}/dedic_gpio_periph.c")
 endif()
 
 if(CONFIG_SOC_GDMA_SUPPORTED)
-    list(APPEND srcs "${target}/gdma_periph.c")
+    list(APPEND srcs "${target_folder}/gdma_periph.c")
 endif()
 
 if(CONFIG_SOC_DMA2D_SUPPORTED)
-    list(APPEND srcs "${target}/dma2d_periph.c")
+    list(APPEND srcs "${target_folder}/dma2d_periph.c")
 endif()
 
 if(CONFIG_SOC_GPSPI_SUPPORTED)
-    list(APPEND srcs "${target}/spi_periph.c")
+    list(APPEND srcs "${target_folder}/spi_periph.c")
 endif()
 
 if(CONFIG_SOC_LEDC_SUPPORTED)
-    list(APPEND srcs "${target}/ledc_periph.c")
+    list(APPEND srcs "${target_folder}/ledc_periph.c")
 endif()
 
 if(CONFIG_SOC_PCNT_SUPPORTED)
-    list(APPEND srcs "${target}/pcnt_periph.c")
+    list(APPEND srcs "${target_folder}/pcnt_periph.c")
 endif()
 
 if(CONFIG_SOC_RMT_SUPPORTED)
-    list(APPEND srcs "${target}/rmt_periph.c")
+    list(APPEND srcs "${target_folder}/rmt_periph.c")
 endif()
 
 if(CONFIG_SOC_SDM_SUPPORTED)
-    list(APPEND srcs "${target}/sdm_periph.c")
+    list(APPEND srcs "${target_folder}/sdm_periph.c")
 endif()
 
 if(CONFIG_SOC_I2S_SUPPORTED)
-    list(APPEND srcs "${target}/i2s_periph.c")
+    list(APPEND srcs "${target_folder}/i2s_periph.c")
 endif()
 
 if(CONFIG_SOC_I2C_SUPPORTED)
-    list(APPEND srcs "${target}/i2c_periph.c")
+    list(APPEND srcs "${target_folder}/i2c_periph.c")
 endif()
 
 if(CONFIG_SOC_TEMP_SENSOR_SUPPORTED)
-    list(APPEND srcs "${target}/temperature_sensor_periph.c")
+    list(APPEND srcs "${target_folder}/temperature_sensor_periph.c")
 endif()
 
 if(CONFIG_SOC_GPTIMER_SUPPORTED)
-    list(APPEND srcs "${target}/timer_periph.c")
+    list(APPEND srcs "${target_folder}/timer_periph.c")
 endif()
 
 if(CONFIG_SOC_LCDCAM_SUPPORTED OR CONFIG_SOC_LCD_I80_SUPPORTED)
-    list(APPEND srcs "${target}/lcd_periph.c")
+    list(APPEND srcs "${target_folder}/lcd_periph.c")
 endif()
 
 if(CONFIG_SOC_MIPI_DSI_SUPPORTED)
-    list(APPEND srcs "${target}/mipi_dsi_periph.c")
+    list(APPEND srcs "${target_folder}/mipi_dsi_periph.c")
 endif()
 
 if(CONFIG_SOC_MIPI_CSI_SUPPORTED)
-    list(APPEND srcs "${target}/mipi_csi_periph.c")
+    list(APPEND srcs "${target_folder}/mipi_csi_periph.c")
 endif()
 
 if(CONFIG_SOC_PARLIO_SUPPORTED)
-    list(APPEND srcs "${target}/parlio_periph.c")
+    list(APPEND srcs "${target_folder}/parlio_periph.c")
 endif()
 
 if(CONFIG_SOC_MCPWM_SUPPORTED)
-    list(APPEND srcs "${target}/mcpwm_periph.c")
+    list(APPEND srcs "${target_folder}/mcpwm_periph.c")
 endif()
 
 if(CONFIG_SOC_MPI_SUPPORTED)
-    list(APPEND srcs "${target}/mpi_periph.c")
+    list(APPEND srcs "${target_folder}/mpi_periph.c")
 endif()
 
 if(CONFIG_SOC_SDMMC_HOST_SUPPORTED)
-    list(APPEND srcs "${target}/sdmmc_periph.c")
+    list(APPEND srcs "${target_folder}/sdmmc_periph.c")
 endif()
 
 if(CONFIG_SOC_TOUCH_SENSOR_SUPPORTED)
-    list(APPEND srcs "${target}/touch_sensor_periph.c")
+    list(APPEND srcs "${target_folder}/touch_sensor_periph.c")
 endif()
 
 if(CONFIG_SOC_TWAI_SUPPORTED)
-    list(APPEND srcs "${target}/twai_periph.c")
+    list(APPEND srcs "${target_folder}/twai_periph.c")
 endif()
 
 if(CONFIG_SOC_IEEE802154_SUPPORTED)
     if(NOT target STREQUAL "esp32h4")
-        list(APPEND srcs "${target}/ieee802154_periph.c")
+        list(APPEND srcs "${target_folder}/ieee802154_periph.c")
     endif()
 endif()
 
 if(CONFIG_SOC_USB_OTG_SUPPORTED)
     if(NOT ${target} STREQUAL "esp32p4")
-        list(APPEND srcs "${target}/usb_periph.c"
-                         "${target}/usb_dwc_periph.c")
+        list(APPEND srcs "${target_folder}/usb_periph.c"
+                         "${target_folder}/usb_dwc_periph.c")
     endif()
 endif()
 
 if(CONFIG_SOC_DAC_SUPPORTED)
-    list(APPEND srcs "${target}/dac_periph.c")
+    list(APPEND srcs "${target_folder}/dac_periph.c")
 endif()
 
 if(CONFIG_SOC_RTCIO_PIN_COUNT GREATER 0)
-    list(APPEND srcs "${target}/rtc_io_periph.c")
+    list(APPEND srcs "${target_folder}/rtc_io_periph.c")
 endif()
 
 if(CONFIG_SOC_SDIO_SLAVE_SUPPORTED)
-    list(APPEND srcs "${target}/sdio_slave_periph.c")
+    list(APPEND srcs "${target_folder}/sdio_slave_periph.c")
 endif()
 
 if(CONFIG_SOC_PAU_SUPPORTED)
-    list(APPEND srcs "${target}/system_retention_periph.c")
+    list(APPEND srcs "${target_folder}/system_retention_periph.c")
 endif()
 
 idf_component_register(SRCS ${srcs}
@@ -158,5 +166,5 @@ if(target STREQUAL "esp32")
 endif()
 
 if(NOT CONFIG_IDF_TARGET_LINUX)
-     target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/ld/${target}.peripherals.ld")
+     target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.ld")
 endif()

components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in

@@ -0,0 +1,456 @@
+#####################################################
+# This file is auto-generated from SoC caps
+# using gen_soc_caps_kconfig.py, do not edit manually
+#####################################################
+
+config SOC_UART_SUPPORTED
+    bool
+    default y
+
+config SOC_GDMA_SUPPORTED
+    bool
+    default y
+
+config SOC_AHB_GDMA_SUPPORTED
+    bool
+    default y
+
+config SOC_GPTIMER_SUPPORTED
+    bool
+    default y
+
+config SOC_ASYNC_MEMCPY_SUPPORTED
+    bool
+    default y
+
+config SOC_EFUSE_KEY_PURPOSE_FIELD
+    bool
+    default y
+
+config SOC_EFUSE_SUPPORTED
+    bool
+    default y
+
+config SOC_RTC_FAST_MEM_SUPPORTED
+    bool
+    default y
+
+config SOC_RTC_MEM_SUPPORTED
+    bool
+    default y
+
+config SOC_I2C_SUPPORTED
+    bool
+    default y
+
+config SOC_SYSTIMER_SUPPORTED
+    bool
+    default y
+
+config SOC_ECC_SUPPORTED
+    bool
+    default y
+
+config SOC_ECC_EXTENDED_MODES_SUPPORTED
+    bool
+    default y
+
+config SOC_FLASH_ENC_SUPPORTED
+    bool
+    default y
+
+config SOC_LP_PERIPHERALS_SUPPORTED
+    bool
+    default y
+
+config SOC_SPI_FLASH_SUPPORTED
+    bool
+    default y
+
+config SOC_XTAL_SUPPORT_40M
+    bool
+    default y
+
+config SOC_XTAL_SUPPORT_48M
+    bool
+    default y
+
+config SOC_ADC_PERIPH_NUM
+    int
+    default 1
+
+config SOC_ADC_MAX_CHANNEL_NUM
+    int
+    default 7
+
+config SOC_SHARED_IDCACHE_SUPPORTED
+    bool
+    default y
+
+config SOC_CACHE_FREEZE_SUPPORTED
+    bool
+    default y
+
+config SOC_CPU_CORES_NUM
+    int
+    default 1
+
+config SOC_CPU_INTR_NUM
+    int
+    default 32
+
+config SOC_CPU_HAS_FLEXIBLE_INTC
+    bool
+    default y
+
+config SOC_INT_CLIC_SUPPORTED
+    bool
+    default y
+
+config SOC_INT_HW_NESTED_SUPPORTED
+    bool
+    default y
+
+config SOC_BRANCH_PREDICTOR_SUPPORTED
+    bool
+    default y
+
+config SOC_CPU_BREAKPOINTS_NUM
+    int
+    default 4
+
+config SOC_CPU_WATCHPOINTS_NUM
+    int
+    default 4
+
+config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
+    hex
+    default 0x100
+
+config SOC_CPU_HAS_PMA
+    bool
+    default y
+
+config SOC_CPU_IDRAM_SPLIT_USING_PMP
+    bool
+    default y
+
+config SOC_AHB_GDMA_VERSION
+    int
+    default 1
+
+config SOC_GDMA_NUM_GROUPS_MAX
+    int
+    default 1
+
+config SOC_GDMA_PAIRS_PER_GROUP_MAX
+    int
+    default 3
+
+config SOC_GPIO_PORT
+    int
+    default 1
+
+config SOC_GPIO_PIN_COUNT
+    int
+    default 27
+
+config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
+    bool
+    default y
+
+config SOC_GPIO_ETM_EVENTS_PER_GROUP
+    int
+    default 8
+
+config SOC_GPIO_ETM_TASKS_PER_GROUP
+    int
+    default 8
+
+config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
+    bool
+    default y
+
+config SOC_GPIO_IN_RANGE_MAX
+    int
+    default 26
+
+config SOC_GPIO_OUT_RANGE_MAX
+    int
+    default 26
+
+config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
+    int
+    default 0
+
+config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
+    hex
+    default 0x0000000007FFFF00
+
+config SOC_GPIO_SUPPORT_FORCE_HOLD
+    bool
+    default y
+
+config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+    bool
+    default y
+
+config SOC_RTCIO_PIN_COUNT
+    bool
+    default n
+
+config SOC_I2C_NUM
+    int
+    default 1
+
+config SOC_I2C_FIFO_LEN
+    int
+    default 32
+
+config SOC_I2C_CMD_REG_NUM
+    int
+    default 8
+
+config SOC_I2C_SUPPORT_SLAVE
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_HW_FSM_RST
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_HW_CLR_BUS
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_10BIT_ADDR
+    bool
+    default y
+
+config SOC_I2C_SLAVE_SUPPORT_BROADCAST
+    bool
+    default y
+
+config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
+    bool
+    default y
+
+config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
+    bool
+    default y
+
+config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+    bool
+    default y
+
+config SOC_LEDC_SUPPORT_XTAL_CLOCK
+    bool
+    default y
+
+config SOC_LEDC_CHANNEL_NUM
+    int
+    default 6
+
+config SOC_MMU_PERIPH_NUM
+    int
+    default 1
+
+config SOC_MMU_LINEAR_ADDRESS_REGION_NUM
+    int
+    default 1
+
+config SOC_MMU_DI_VADDR_SHARED
+    bool
+    default y
+
+config SOC_RSA_MAX_BIT_LEN
+    int
+    default 3072
+
+config SOC_SPI_PERIPH_NUM
+    int
+    default 2
+
+config SOC_SPI_MAX_CS_NUM
+    int
+    default 6
+
+config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
+    bool
+    default y
+
+config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
+    bool
+    default y
+
+config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
+    bool
+    default y
+
+config SOC_SYSTIMER_COUNTER_NUM
+    int
+    default 2
+
+config SOC_SYSTIMER_ALARM_NUM
+    int
+    default 3
+
+config SOC_SYSTIMER_BIT_WIDTH_LO
+    int
+    default 32
+
+config SOC_SYSTIMER_BIT_WIDTH_HI
+    int
+    default 20
+
+config SOC_SYSTIMER_FIXED_DIVIDER
+    bool
+    default y
+
+config SOC_SYSTIMER_SUPPORT_RC_FAST
+    bool
+    default y
+
+config SOC_SYSTIMER_INT_LEVEL
+    bool
+    default y
+
+config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
+    bool
+    default y
+
+config SOC_TIMER_GROUPS
+    int
+    default 2
+
+config SOC_TIMER_GROUP_TIMERS_PER_GROUP
+    int
+    default 1
+
+config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
+    int
+    default 54
+
+config SOC_TIMER_GROUP_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_TIMER_GROUP_TOTAL_TIMERS
+    int
+    default 2
+
+config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
+    int
+    default 3
+
+config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
+    int
+    default 64
+
+config SOC_FLASH_ENCRYPTION_XTS_AES
+    bool
+    default y
+
+config SOC_FLASH_ENCRYPTION_XTS_AES_128
+    bool
+    default y
+
+config SOC_UART_NUM
+    int
+    default 3
+
+config SOC_UART_HP_NUM
+    int
+    default 2
+
+config SOC_UART_LP_NUM
+    int
+    default 1
+
+config SOC_UART_FIFO_LEN
+    int
+    default 128
+
+config SOC_LP_UART_FIFO_LEN
+    int
+    default 16
+
+config SOC_UART_BITRATE_MAX
+    int
+    default 5000000
+
+config SOC_UART_SUPPORT_PLL_F80M_CLK
+    bool
+    default y
+
+config SOC_UART_SUPPORT_XTAL_CLK
+    bool
+    default y
+
+config SOC_UART_SUPPORT_WAKEUP_INT
+    bool
+    default y
+
+config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
+    bool
+    default y
+
+config SOC_PM_SUPPORT_CPU_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_MODEM_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_XTAL32K_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_RC32K_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_RC_FAST_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_VDDSDIO_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_HP_AON_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_RTC_PERIPH_PD
+    bool
+    default y
+
+config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
+    bool
+    default y
+
+config SOC_MODEM_CLOCK_IS_INDEPENDENT
+    bool
+    default y
+
+config SOC_CLK_XTAL32K_SUPPORTED
+    bool
+    default y
+
+config SOC_CLK_OSC_SLOW_SUPPORTED
+    bool
+    default y
+
+config SOC_CLK_RC32K_SUPPORTED
+    bool
+    default y
+
+config SOC_RCC_IS_INDEPENDENT
+    bool
+    default y