Merge branch 'feat/private_api_to_get_cache_line_size' into 'master'

cache: added private API to get cache alignment requirements

See merge request espressif/esp-idf!26285

components/esp_mm/esp_cache.c

@@ -108,15 +108,11 @@ esp_err_t esp_cache_aligned_malloc(size_t size, uint32_t flags, void **out_ptr,
         }
     }
 
-#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
     data_cache_line_size = cache_hal_get_cache_line_size(cache_level, CACHE_TYPE_DATA);
-#else
+    if (data_cache_line_size == 0) {
-    if (cache_level == CACHE_LL_LEVEL_EXT_MEM) {
+        //default alignment
-        data_cache_line_size = cache_hal_get_cache_line_size(cache_level, CACHE_TYPE_DATA);
-    } else {
         data_cache_line_size = 4;
     }
-#endif
 
     size = ALIGN_UP_BY(size, data_cache_line_size);
     ptr = heap_caps_aligned_alloc(data_cache_line_size, size, heap_caps);
@@ -150,3 +146,25 @@ esp_err_t esp_cache_aligned_calloc(size_t n, size_t size, uint32_t flags, void *
 
     return ret;
 }
+
+esp_err_t esp_cache_get_alignment(uint32_t flags, size_t *out_alignment)
+{
+    ESP_RETURN_ON_FALSE(out_alignment, ESP_ERR_INVALID_ARG, TAG, "null pointer");
+
+    uint32_t cache_level = CACHE_LL_LEVEL_INT_MEM;
+    uint32_t data_cache_line_size = 0;
+
+    if (flags & ESP_CACHE_MALLOC_FLAG_PSRAM) {
+        cache_level = CACHE_LL_LEVEL_EXT_MEM;
+    }
+
+    data_cache_line_size = cache_hal_get_cache_line_size(cache_level, CACHE_TYPE_DATA);
+    if (data_cache_line_size == 0) {
+        //default alignment
+        data_cache_line_size = 4;
+    }
+
+    *out_alignment = data_cache_line_size;
+
+    return ESP_OK;
+}

components/esp_mm/include/esp_private/esp_cache_private.h

@@ -28,7 +28,7 @@ extern "C" {
 #define ESP_CACHE_MALLOC_FLAG_DMA          BIT(1)
 
 /**
- * @brief Helper function for malloc a cache aligned memory buffer
+ * @brief Helper function for malloc a cache aligned data memory buffer
  *
  * @param[in]  size         Size in bytes, the amount of memory to allocate
  * @param[in]  flags        Flags, see `ESP_CACHE_MALLOC_FLAG_x`
@@ -43,7 +43,7 @@ extern "C" {
 esp_err_t esp_cache_aligned_malloc(size_t size, uint32_t flags, void **out_ptr, size_t *actual_size);
 
 /**
- * @brief Helper function for calloc a cache aligned memory buffer
+ * @brief Helper function for calloc a cache aligned data memory buffer
  *
  * @param[in]  n            Number of continuing chunks of memory to allocate
  * @param[in]  size         Size of one chunk, in bytes
@@ -58,6 +58,18 @@ esp_err_t esp_cache_aligned_malloc(size_t size, uint32_t flags, void **out_ptr,
  */
 esp_err_t esp_cache_aligned_calloc(size_t n, size_t size, uint32_t flags, void **out_ptr, size_t *actual_size);
 
+/**
+ * @brief Get Cache alignment requirement for data
+ *
+ * @param[in]  flags          Flags, see `ESP_CACHE_MALLOC_FLAG_x`
+ * @param[out] out_alignment  Alignment
+ *
+ * @return
+ *        - ESP_OK:
+ *        - ESP_ERR_INVALID_ARG: Invalid argument
+ */
+esp_err_t esp_cache_get_alignment(uint32_t flags, size_t *out_alignment);
+
 #ifdef __cplusplus
 }
 #endif

components/hal/cache_hal.c

@@ -287,8 +287,15 @@ void cache_hal_unfreeze(uint32_t cache_level, cache_type_t type)
 uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type)
 {
     HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
+    uint32_t line_size = 0;
 
-    uint32_t line_size = cache_ll_get_line_size(cache_level, type, CACHE_LL_ID_ALL);
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+    line_size = cache_ll_get_line_size(cache_level, type, CACHE_LL_ID_ALL);
+#else
+    if (cache_level == CACHE_LL_LEVEL_EXT_MEM) {
+        line_size = cache_ll_get_line_size(cache_level, type, CACHE_LL_ID_ALL);
+    }
+#endif
 
     return line_size;
 }

components/hal/esp32/cache_hal_esp32.c

@@ -56,7 +56,14 @@ bool cache_hal_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint3
 uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type)
 {
     HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
-    return 4;
+
+    uint32_t line_size = 0;
+
+    if (cache_level == CACHE_LL_LEVEL_EXT_MEM) {
+        line_size = 4;
+    }
+
+    return line_size;
 }
 
 bool cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size)

components/hal/include/hal/cache_hal.h

@@ -129,7 +129,7 @@ void cache_hal_unfreeze(uint32_t cache_level, cache_type_t type);
  * @param cache_level  Level of the Cache(s)
  * @param type         see `cache_type_t`
  *
- * @return cache line size, in bytes
+ * @return cache line size, in bytes. 0 stands for no such cache in this type or level
  */
 uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type);