mirror of
https://github.com/espressif/esp-idf
synced 2025-03-09 17:19:09 -04:00
Merge branch 'feat/h4_introduce_step2_3' into 'master'
feat(esp32h4): add soc register header files (stage 3/8, part 3/3) See merge request espressif/esp-idf!37092
This commit is contained in:
Chen Ji Chang
commit
33e81e572b
@ -9,7 +9,9 @@
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#if SOC_ASSIST_DEBUG_SUPPORTED
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#include "soc/assist_debug_reg.h"
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#endif
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#include "soc/interrupt_reg.h"
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#include "esp_attr.h"
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#include "riscv/csr.h"
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@ -405,7 +407,11 @@ FORCE_INLINE_ATTR bool rv_utils_is_trigger_fired(int id)
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FORCE_INLINE_ATTR bool rv_utils_dbgr_is_attached(void)
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{
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#if SOC_ASSIST_DEBUG_SUPPORTED
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return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE);
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#else
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return false;
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#endif
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}
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FORCE_INLINE_ATTR void rv_utils_dbgr_break(void)
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524
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
Normal file
524
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
Normal file
@ -0,0 +1,524 @@
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#####################################################
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# This file is auto-generated from SoC caps
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# using gen_soc_caps_kconfig.py, do not edit manually
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#####################################################
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|
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config SOC_UART_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
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config SOC_EFUSE_KEY_PURPOSE_FIELD
|
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bool
|
||||
default y
|
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|
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config SOC_EFUSE_SUPPORTED
|
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bool
|
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default y
|
||||
|
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config SOC_SYSTIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_FLASH_ENC_SUPPORTED
|
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bool
|
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default y
|
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|
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config SOC_SPI_FLASH_SUPPORTED
|
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bool
|
||||
default y
|
||||
|
||||
config SOC_XTAL_SUPPORT_32M
|
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bool
|
||||
default y
|
||||
|
||||
config SOC_AES_SUPPORT_DMA
|
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bool
|
||||
default y
|
||||
|
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config SOC_AES_GDMA
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bool
|
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default y
|
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|
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config SOC_AES_SUPPORT_AES_128
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bool
|
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default y
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|
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config SOC_AES_SUPPORT_AES_256
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bool
|
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default y
|
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|
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config SOC_ADC_PERIPH_NUM
|
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int
|
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default 1
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|
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config SOC_ADC_MAX_CHANNEL_NUM
|
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int
|
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default 7
|
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|
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config SOC_ADC_ATTEN_NUM
|
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int
|
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default 4
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|
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config SOC_APB_BACKUP_DMA
|
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bool
|
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default n
|
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|
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config SOC_CPU_CORES_NUM
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int
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default 2
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|
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config SOC_CPU_INTR_NUM
|
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int
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default 32
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|
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config SOC_CPU_HAS_FLEXIBLE_INTC
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bool
|
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default y
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|
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config SOC_INT_PLIC_SUPPORTED
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bool
|
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default n
|
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|
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config SOC_INT_CLIC_SUPPORTED
|
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bool
|
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default y
|
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|
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config SOC_INT_HW_NESTED_SUPPORTED
|
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bool
|
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default y
|
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|
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config SOC_BRANCH_PREDICTOR_SUPPORTED
|
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bool
|
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default y
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|
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config SOC_CPU_HAS_FPU
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bool
|
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default y
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|
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config SOC_CPU_HAS_FPU_EXT_ILL_BUG
|
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bool
|
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default n
|
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|
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config SOC_CPU_COPROC_NUM
|
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int
|
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default 2
|
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|
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config SOC_CPU_BREAKPOINTS_NUM
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int
|
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default 4
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config SOC_CPU_WATCHPOINTS_NUM
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int
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default 4
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config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
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hex
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default 0x80000000
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config SOC_CPU_HAS_PMA
|
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bool
|
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default y
|
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|
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config SOC_CPU_IDRAM_SPLIT_USING_PMP
|
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bool
|
||||
default y
|
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|
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config SOC_GPIO_PORT
|
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int
|
||||
default 1
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|
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config SOC_GPIO_PIN_COUNT
|
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int
|
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default 40
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|
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config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
|
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bool
|
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default y
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config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
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bool
|
||||
default y
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|
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config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
|
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int
|
||||
default 0
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config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
|
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hex
|
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default 0x000000FFFFFFFFC0
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config SOC_GPIO_SUPPORT_FORCE_HOLD
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bool
|
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default y
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config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
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bool
|
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default y
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|
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config SOC_RTCIO_PIN_COUNT
|
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int
|
||||
default 6
|
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|
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config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
|
||||
bool
|
||||
default y
|
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|
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config SOC_RTCIO_HOLD_SUPPORTED
|
||||
bool
|
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default y
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config SOC_RTCIO_WAKE_SUPPORTED
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bool
|
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default y
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config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
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int
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default 8
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config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
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int
|
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default 8
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|
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config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
|
||||
bool
|
||||
default y
|
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|
||||
config SOC_MMU_PERIPH_NUM
|
||||
int
|
||||
default 1
|
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|
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config SOC_MMU_LINEAR_ADDRESS_REGION_NUM
|
||||
int
|
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default 1
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|
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config SOC_MMU_DI_VADDR_SHARED
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bool
|
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default y
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config SOC_SPI_PERIPH_NUM
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int
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default 3
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config SOC_SPI_MAX_CS_NUM
|
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int
|
||||
default 6
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config SOC_MEMSPI_IS_INDEPENDENT
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bool
|
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default y
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config SOC_SPI_MAX_PRE_DIVIDER
|
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int
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default 16
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config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
|
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bool
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default y
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config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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bool
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default y
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config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
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bool
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default y
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config SOC_SPI_MEM_SUPPORT_IDLE_INTR
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bool
|
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default y
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config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
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bool
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default y
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config SOC_SPI_MEM_SUPPORT_CHECK_SUS
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bool
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default y
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config SOC_SPI_MEM_SUPPORT_WRAP
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED
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bool
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default y
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config SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED
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bool
|
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default y
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config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED
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bool
|
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default y
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config SOC_SYSTIMER_COUNTER_NUM
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int
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default 2
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config SOC_SYSTIMER_ALARM_NUM
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int
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default 3
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config SOC_SYSTIMER_BIT_WIDTH_LO
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int
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default 32
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config SOC_SYSTIMER_BIT_WIDTH_HI
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int
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default 20
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config SOC_SYSTIMER_FIXED_DIVIDER
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bool
|
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default y
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config SOC_SYSTIMER_SUPPORT_RC_FAST
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bool
|
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default y
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config SOC_SYSTIMER_INT_LEVEL
|
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bool
|
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default y
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config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
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bool
|
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default y
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|
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config SOC_SYSTIMER_SUPPORT_ETM
|
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bool
|
||||
default y
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config SOC_TIMER_GROUPS
|
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int
|
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default 2
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|
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config SOC_TIMER_GROUP_TIMERS_PER_GROUP
|
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int
|
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default 1
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config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
|
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int
|
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default 54
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|
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config SOC_TIMER_GROUP_SUPPORT_XTAL
|
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bool
|
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default y
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|
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config SOC_TIMER_GROUP_SUPPORT_RC_FAST
|
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bool
|
||||
default y
|
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|
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config SOC_TIMER_GROUP_TOTAL_TIMERS
|
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int
|
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default 2
|
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|
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config SOC_MWDT_SUPPORT_XTAL
|
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bool
|
||||
default y
|
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|
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config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
|
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bool
|
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default n
|
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|
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config SOC_EFUSE_DIS_PAD_JTAG
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bool
|
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default y
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config SOC_EFUSE_DIS_USB_JTAG
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bool
|
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default y
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config SOC_EFUSE_DIS_DIRECT_BOOT
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bool
|
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default y
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|
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config SOC_EFUSE_SOFT_DIS_JTAG
|
||||
bool
|
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default n
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|
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config SOC_EFUSE_DIS_ICACHE
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bool
|
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default n
|
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config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
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bool
|
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default y
|
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config SOC_SECURE_BOOT_V2_RSA
|
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bool
|
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default y
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|
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config SOC_SECURE_BOOT_V2_ECC
|
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bool
|
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default y
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||||
|
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config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
|
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int
|
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default 3
|
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|
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config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
|
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bool
|
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default y
|
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|
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config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
|
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bool
|
||||
default y
|
||||
|
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config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
|
||||
int
|
||||
default 64
|
||||
|
||||
config SOC_FLASH_ENCRYPTION_XTS_AES
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_FLASH_ENCRYPTION_XTS_AES_128
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_UART_NUM
|
||||
int
|
||||
default 3
|
||||
|
||||
config SOC_UART_HP_NUM
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_UART_LP_NUM
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_UART_FIFO_LEN
|
||||
int
|
||||
default 128
|
||||
|
||||
config SOC_LP_UART_FIFO_LEN
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_UART_BITRATE_MAX
|
||||
int
|
||||
default 5000000
|
||||
|
||||
config SOC_UART_SUPPORT_PLL_F80M_CLK
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_UART_SUPPORT_RTC_CLK
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_UART_SUPPORT_XTAL_CLK
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_UART_SUPPORT_WAKEUP_INT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_COEX_HW_PTI
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EXTERNAL_COEX_ADVANCE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_PHY_DIG_REGS_MEM_SIZE
|
||||
int
|
||||
default 21
|
||||
|
||||
config SOC_PM_SUPPORT_BEACON_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_BT_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_EXT1_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_TOUCH_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_CPU_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_MODEM_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_XTAL32K_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_RC32K_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_RC_FAST_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_VDDSDIO_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_TOP_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_HP_AON_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_MAC_BB_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_RTC_PERIPH_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_PAU_LINK_NUM
|
||||
int
|
||||
default 4
|
||||
|
||||
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MODEM_CLOCK_IS_INDEPENDENT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_CLK_XTAL32K_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_CLK_OSC_SLOW_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_CLK_RC32K_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RCC_IS_INDEPENDENT
|
||||
bool
|
||||
default y
|
||||
91
components/soc/esp32h4/include/soc/boot_mode.h
Normal file
91
components/soc/esp32h4/include/soc/boot_mode.h
Normal file
@ -0,0 +1,91 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_BOOT_MODE_H_
|
||||
#define _SOC_BOOT_MODE_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
/*SPI Boot*/
|
||||
#define IS_1XXX(v) (((v)&0x08)==0x08)
|
||||
|
||||
/*Download Boot, SPI(or SDIO_V2)/UART0*/
|
||||
#define IS_00XX(v) (((v)&0x0c)==0x00)
|
||||
|
||||
/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
|
||||
#define IS_0000(v) (((v)&0x0f)==0x00)
|
||||
|
||||
/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
|
||||
#define IS_0001(v) (((v)&0x0f)==0x01)
|
||||
|
||||
/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
|
||||
#define IS_0010(v) (((v)&0x0f)==0x02)
|
||||
|
||||
/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
|
||||
#define IS_0011(v) (((v)&0x0f)==0x03)
|
||||
|
||||
/*legacy SPI Boot*/
|
||||
#define IS_0100(v) (((v)&0x0f)==0x04)
|
||||
|
||||
/*ATE/ANALOG Mode*/
|
||||
#define IS_0101(v) (((v)&0x0f)==0x05)
|
||||
|
||||
/*SPI(or SDIO_V1) download Mode*/
|
||||
#define IS_0110(v) (((v)&0x0f)==0x06)
|
||||
|
||||
/*Diagnostic Mode+UART0 download Mode*/
|
||||
#define IS_0111(v) (((v)&0x0f)==0x07)
|
||||
|
||||
#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG))
|
||||
|
||||
/*do not include download mode*/
|
||||
#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET())
|
||||
|
||||
/*all spi boot including spi/legacy*/
|
||||
#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET()))
|
||||
|
||||
/*all faster spi boot including spi*/
|
||||
#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET())
|
||||
|
||||
#if SUPPORT_SDIO_DOWNLOAD
|
||||
|
||||
/*all sdio V2 of failing edge input, failing edge output*/
|
||||
#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET())
|
||||
|
||||
/*all sdio V2 of failing edge input, raising edge output*/
|
||||
#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET())
|
||||
|
||||
/*all sdio V2 of raising edge input, failing edge output*/
|
||||
#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET())
|
||||
|
||||
/*all sdio V2 of raising edge input, raising edge output*/
|
||||
#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET())
|
||||
|
||||
/*all sdio V1 of raising edge input, failing edge output*/
|
||||
#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET())
|
||||
|
||||
/*do not include joint download mode*/
|
||||
#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET())
|
||||
#else
|
||||
|
||||
/*do not include joint download mode*/
|
||||
#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET())
|
||||
|
||||
#endif
|
||||
|
||||
/*joint download boot*/
|
||||
#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET())
|
||||
|
||||
/*ATE mode*/
|
||||
#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET())
|
||||
|
||||
/*used by ETS_IS_SDIO_UART_BOOT*/
|
||||
#define SEL_NO_BOOT 0
|
||||
#define SEL_SDIO_BOOT BIT0
|
||||
#define SEL_UART_BOOT BIT1
|
||||
#define SEL_SPI_SLAVE_BOOT BIT2
|
||||
|
||||
#endif /* _SOC_BOOT_MODE_H_ */
|
||||
113
components/soc/esp32h4/include/soc/clic_reg.h
Normal file
113
components/soc/esp32h4/include/soc/clic_reg.h
Normal file
@ -0,0 +1,113 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//TODO: [ESP32H4] IDF-12303
|
||||
|
||||
#define NLBITS 3
|
||||
#define CLIC_EXT_INTR_NUM_OFFSET 16
|
||||
#define DUALCORE_CLIC_CTRL_OFF 0x10000
|
||||
|
||||
#define DR_REG_CLIC_BASE ( 0x20800000 )
|
||||
#define DR_REG_CLIC_CTRL_BASE ( 0x20801000 )
|
||||
|
||||
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX0_BASE
|
||||
#define DR_REG_INTERRUPT_CORE1_BASE DR_REG_INTMTX1_BASE
|
||||
|
||||
#define CLIC_INT_CONFIG_REG (DR_REG_CLIC_BASE + 0x0)
|
||||
/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_INT_CONFIG_NMBITS 0x00000003
|
||||
#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V)<<(CLIC_INT_CONFIG_NMBITS_S))
|
||||
#define CLIC_INT_CONFIG_NMBITS_V 0x3
|
||||
#define CLIC_INT_CONFIG_NMBITS_S 5
|
||||
/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_INT_CONFIG_NLBITS 0x0000000F
|
||||
#define CLIC_INT_CONFIG_NLBITS_M ((CLIC_INT_CONFIG_NLBITS_V)<<(CCLIC_INT_CONFIG_NLBITS_S))
|
||||
#define CLIC_INT_CONFIG_NLBITS_V 0xF
|
||||
#define CLIC_INT_CONFIG_NLBITS_S 1
|
||||
/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_INT_CONFIG_NVBITS (BIT(0))
|
||||
#define CLIC_INT_CONFIG_NVBITS_M (BIT(0))
|
||||
#define CLIC_INT_CONFIG_NVBITS_V 0x1
|
||||
#define CLIC_INT_CONFIG_NVBITS_S 0
|
||||
|
||||
#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4)
|
||||
/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_INT_INFO_CTLBITS 0x0000000F
|
||||
#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V)<<(CLIC_INT_INFO_CTLBITS_S))
|
||||
#define CLIC_INT_INFO_CTLBITS_V 0xF
|
||||
#define CLIC_INT_INFO_CTLBITS_S 21
|
||||
/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_INT_INFO_VERSION 0x000000FF
|
||||
#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V)<<(CLIC_INT_INFO_VERSION_S))
|
||||
#define CLIC_INT_INFO_VERSION_V 0xFF
|
||||
#define CLIC_INT_INFO_VERSION_S 13
|
||||
/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_INT_INFO_NUM_INT 0x00001FFF
|
||||
#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V)<<(CLIC_INT_INFO_NUM_INT_S))
|
||||
#define CLIC_INT_INFO_NUM_INT_V 0x1FFF
|
||||
#define CLIC_INT_INFO_NUM_INT_S 0
|
||||
|
||||
#define CLIC_INT_THRESH_REG (DR_REG_CLIC_BASE + 0x8)
|
||||
/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_CPU_INT_THRESH 0x000000FF
|
||||
#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V)<<(CLIC_CPU_INT_THRESH_S))
|
||||
#define CLIC_CPU_INT_THRESH_V 0xFF
|
||||
#define CLIC_CPU_INT_THRESH_S 24
|
||||
|
||||
#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i) * 4)
|
||||
/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_INT_CTL 0x000000FF
|
||||
#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V)<<(CLIC_INT_CTL_S))
|
||||
#define CLIC_INT_CTL_V 0xFF
|
||||
#define CLIC_INT_CTL_S 24
|
||||
/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_INT_ATTR_MODE 0x00000003
|
||||
#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V)<<(CLIC_INT_ATTR_MODE_S))
|
||||
#define CLIC_INT_ATTR_MODE_V 0x3
|
||||
#define CLIC_INT_ATTR_MODE_S 22
|
||||
/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_INT_ATTR_TRIG 0x00000003
|
||||
#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V)<<(CLIC_INT_ATTR_TRIG_S))
|
||||
#define CLIC_INT_ATTR_TRIG_V 0x3
|
||||
#define CLIC_INT_ATTR_TRIG_S 17
|
||||
/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_INT_ATTR_SHV (BIT(16))
|
||||
#define CLIC_INT_ATTR_SHV_M (BIT(16))
|
||||
#define CLIC_INT_ATTR_SHV_V 0x1
|
||||
#define CLIC_INT_ATTR_SHV_S 16
|
||||
/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_INT_IE (BIT(8))
|
||||
#define CLIC_INT_IE_M (BIT(8))
|
||||
#define CLIC_INT_IE_V 0x1
|
||||
#define CLIC_INT_IE_S 8
|
||||
/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define CLIC_INT_IP (BIT(0))
|
||||
#define CLIC_INT_IP_M (BIT(0))
|
||||
#define CLIC_INT_IP_V 0x1
|
||||
#define CLIC_INT_IP_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
78
components/soc/esp32h4/include/soc/clint_reg.h
Normal file
78
components/soc/esp32h4/include/soc/clint_reg.h
Normal file
@ -0,0 +1,78 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//TODO: [ESP32H4] IDF-12303
|
||||
|
||||
/*CLINT MINT*/
|
||||
#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0)
|
||||
/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define CLINT_CPU_MINT_SIP BIT(0)
|
||||
#define CLINT_CPU_MINT_SIP_M BIT(0)
|
||||
#define CLINT_CPU_MINT_SIP_V 1
|
||||
#define CLINT_CPU_MINT_SIP_S 0
|
||||
|
||||
#define CLINT_MINT_MTIMECMP_L_REG (DR_REG_CLINT_M_BASE + 0x4000)
|
||||
/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S))
|
||||
#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIMECMP_L_S 0
|
||||
|
||||
#define CLINT_MINT_MTIMECMP_H_REG (DR_REG_CLINT_M_BASE + 0x4004)
|
||||
/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S))
|
||||
#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIMECMP_H_S 0
|
||||
|
||||
#define CLINT_MINT_TIMECTL_REG (DR_REG_CLINT_M_BASE + 0x4010)
|
||||
/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
|
||||
/*description: .*/
|
||||
#define CLINT_MINT_SAMPLING_MODE 0x00000003
|
||||
#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S))
|
||||
#define CLINT_MINT_SAMPLING_MODE_V 0x3
|
||||
#define CLINT_MINT_SAMPLING_MODE_S 4
|
||||
/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3))
|
||||
#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3))
|
||||
#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1
|
||||
#define CLINT_MINT_COUNTER_OVERFLOW_S 3
|
||||
/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define CLINT_MINT_COUNTER_EN (BIT(0))
|
||||
#define CLINT_MINT_COUNTER_EN_M (BIT(0))
|
||||
#define CLINT_MINT_COUNTER_EN_V 0x1
|
||||
#define CLINT_MINT_COUNTER_EN_S 0
|
||||
|
||||
#define CLINT_MINT_MTIME_L_REG (DR_REG_CLINT_M_BASE + 0xBFF8)
|
||||
/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S))
|
||||
#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIME_L_S 0
|
||||
|
||||
#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xBFFC)
|
||||
/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S))
|
||||
#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIME_H_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
262
components/soc/esp32h4/include/soc/clk_tree_defs.h
Normal file
262
components/soc/esp32h4/include/soc/clk_tree_defs.h
Normal file
@ -0,0 +1,262 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: [ESP32H4] IDF-12285 inherit from verify code, need check
|
||||
|
||||
/*
|
||||
************************* ESP32H4 Root Clock Source ****************************
|
||||
* 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description)
|
||||
*
|
||||
* This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
|
||||
*
|
||||
* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
|
||||
*
|
||||
* 2) External 40MHz Crystal Clock: XTAL
|
||||
*
|
||||
* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description)
|
||||
*
|
||||
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
|
||||
* can be computed in runtime through calibration.
|
||||
*
|
||||
* 4) Internal 32kHz RC Oscillator: RC32K
|
||||
*
|
||||
* The exact frequency of this clock can be computed in runtime through calibration.
|
||||
*
|
||||
* 5) External 32kHz Crystal Clock (optional): XTAL32K
|
||||
*
|
||||
* The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
|
||||
* pins.
|
||||
*
|
||||
* XTAL32K_CLK can also be calibrated to get its exact frequency.
|
||||
*
|
||||
* 6) External Slow Clock (optional): OSC_SLOW
|
||||
*
|
||||
* A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the
|
||||
* RTC_SLOW_CLK.
|
||||
*
|
||||
* OSC_SLOW_CLK can also be calibrated to get its exact frequency.
|
||||
*/
|
||||
|
||||
/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
|
||||
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
|
||||
#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
|
||||
#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */
|
||||
#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
|
||||
#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */
|
||||
|
||||
// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
|
||||
// {loc}: EXT, INT
|
||||
// {type}: XTAL, RC
|
||||
// [attr] - optional: [frequency], FAST, SLOW
|
||||
/**
|
||||
* @brief Root clock
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */
|
||||
SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */
|
||||
SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */
|
||||
SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */
|
||||
SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */
|
||||
SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */
|
||||
} soc_root_clk_t;
|
||||
|
||||
/**
|
||||
* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
|
||||
* @note Enum values are matched with the register field values on purpose
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
|
||||
SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */
|
||||
SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
|
||||
SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
|
||||
} soc_cpu_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
|
||||
* @note Enum values are matched with the register field values on purpose
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
|
||||
SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
|
||||
SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
|
||||
SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
|
||||
SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
|
||||
} soc_rtc_slow_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
|
||||
* @note Enum values are matched with the register field values on purpose
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
|
||||
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
|
||||
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
|
||||
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
|
||||
|
||||
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
|
||||
} soc_rtc_fast_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency options on the target
|
||||
* @note Enum values equal to the frequency value in MHz
|
||||
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
|
||||
* the supported ones.
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_XTAL_FREQ_32M = 32, /*!< 32MHz XTAL */
|
||||
} soc_xtal_freq_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
/**
|
||||
* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
|
||||
*
|
||||
* @note enum starts from 1, to save 0 for special purpose
|
||||
*/
|
||||
typedef enum {
|
||||
// For CPU domain
|
||||
SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
|
||||
// For RTC domain
|
||||
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
|
||||
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
|
||||
// For digital domain: peripherals, WIFI, BLE
|
||||
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
|
||||
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
|
||||
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
|
||||
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
|
||||
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
|
||||
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
|
||||
// For LP peripherals
|
||||
SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
|
||||
|
||||
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
|
||||
} soc_module_clk_t;
|
||||
|
||||
//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Type of SYSTIMER clock source
|
||||
*/
|
||||
typedef enum {
|
||||
SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */
|
||||
SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */
|
||||
SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
|
||||
} soc_periph_systimer_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of GPTimer
|
||||
*
|
||||
* The following code can be used to iterate all possible clocks:
|
||||
* @code{c}
|
||||
* soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
|
||||
* for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
|
||||
* soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
|
||||
* // Test GPTimer with the clock `clk`
|
||||
* }
|
||||
* @endcode
|
||||
*/
|
||||
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Type of GPTimer clock source
|
||||
*/
|
||||
typedef enum {
|
||||
GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
|
||||
GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
|
||||
} soc_periph_gptimer_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
|
||||
*/
|
||||
typedef enum {
|
||||
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
|
||||
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
|
||||
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
|
||||
} soc_periph_tg_clk_src_legacy_t;
|
||||
|
||||
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Type of UART clock source, reserved for the legacy UART driver
|
||||
*/
|
||||
typedef enum {
|
||||
UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
|
||||
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
|
||||
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
|
||||
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */
|
||||
} soc_periph_uart_clk_src_legacy_t;
|
||||
|
||||
/**
|
||||
* @brief Type of LP_UART clock source
|
||||
*/
|
||||
typedef enum {
|
||||
LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */
|
||||
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
|
||||
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
|
||||
} soc_periph_lp_uart_clk_src_t;
|
||||
|
||||
/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of SPI
|
||||
*/
|
||||
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
|
||||
|
||||
/**
|
||||
* @brief Type of SPI clock source.
|
||||
*/
|
||||
typedef enum {
|
||||
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
|
||||
SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
|
||||
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
|
||||
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
|
||||
} soc_periph_spi_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of MWDT
|
||||
*/
|
||||
#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
|
||||
|
||||
/**
|
||||
* @brief MWDT clock source
|
||||
*/
|
||||
typedef enum {
|
||||
MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */
|
||||
MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */
|
||||
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL fixed 80 MHz as the default clock choice */
|
||||
} soc_periph_mwdt_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////FLASH///////////////////////////////////////////////////////////////////
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of FLASH MSPI controller
|
||||
*/
|
||||
#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
|
||||
/**
|
||||
* @brief FLASH MSPI controller clock source
|
||||
*/
|
||||
typedef enum {
|
||||
FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
|
||||
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
|
||||
} soc_periph_flash_clk_src_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
108
components/soc/esp32h4/include/soc/dport_access.h
Normal file
108
components/soc/esp32h4/include/soc/dport_access.h
Normal file
@ -0,0 +1,108 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
|
||||
|
||||
#define DPORT_INTERRUPT_DISABLE()
|
||||
#define DPORT_INTERRUPT_RESTORE()
|
||||
|
||||
/**
|
||||
* @brief Read a sequence of DPORT registers to the buffer.
|
||||
*
|
||||
* @param[out] buff_out Contains the read data.
|
||||
* @param[in] address Initial address for reading registers.
|
||||
* @param[in] num_words The number of words.
|
||||
*/
|
||||
void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
|
||||
|
||||
// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
|
||||
#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
|
||||
#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
|
||||
|
||||
// Write value to DPORT register (does not require protecting)
|
||||
#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
|
||||
|
||||
#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
|
||||
#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
|
||||
|
||||
//get bit or get bits from register
|
||||
#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
|
||||
|
||||
//set bit or set bits to register
|
||||
#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
|
||||
|
||||
//clear bit or clear bits of register
|
||||
#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
|
||||
|
||||
//get field from register, uses field _S & _V to determine mask
|
||||
#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
|
||||
|
||||
//set field to register, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
|
||||
|
||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
|
||||
//get field value from a variable, used when _f is left shifted by _f##_S
|
||||
#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
|
||||
|
||||
//set field value to a variable, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
|
||||
|
||||
//set field value to a variable, used when _f is left shifted by _f##_S
|
||||
#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
|
||||
|
||||
//generate a value from a field value, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
|
||||
|
||||
//generate a value from a field value, used when _f is left shifted by _f##_S
|
||||
#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||
|
||||
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
|
||||
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
|
||||
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
|
||||
#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
|
||||
#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
|
||||
|
||||
#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr)
|
||||
|
||||
//write value to register
|
||||
#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
|
||||
|
||||
//clear bits of register controlled by mask
|
||||
#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
|
||||
|
||||
//get bits of register controlled by mask
|
||||
#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask))
|
||||
|
||||
//get bits of register controlled by highest bit and lowest bit
|
||||
#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
|
||||
|
||||
//set bits of register controlled by mask and shift
|
||||
#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
|
||||
|
||||
//get field of register
|
||||
#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
|
||||
//}}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
17
components/soc/esp32h4/include/soc/efuse_defs.h
Normal file
17
components/soc/esp32h4/include/soc/efuse_defs.h
Normal file
@ -0,0 +1,17 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define EFUSE_WRITE_OP_CODE 0x5a5a
|
||||
#define EFUSE_READ_OP_CODE 0x5aa5
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
114
components/soc/esp32h4/include/soc/ext_mem_defs.h
Normal file
114
components/soc/esp32h4/include/soc/ext_mem_defs.h
Normal file
@ -0,0 +1,114 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: [ESP32H4] IDF-12305 inherit from verify code, need check
|
||||
|
||||
#if !SOC_MMU_PAGE_SIZE
|
||||
/**
|
||||
* We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt.
|
||||
* Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py
|
||||
*/
|
||||
#define SOC_MMU_PAGE_SIZE 0x10000
|
||||
#endif
|
||||
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM))
|
||||
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
|
||||
|
||||
#define SOC_IRAM_FLASH_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_IRAM_FLASH_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH
|
||||
|
||||
#define SOC_DRAM_FLASH_ADDRESS_LOW SOC_DRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_DRAM_FLASH_ADDRESS_HIGH SOC_DRAM0_CACHE_ADDRESS_HIGH
|
||||
|
||||
#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
|
||||
#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
|
||||
|
||||
#define SOC_MMU_ACCESS_FLASH 0
|
||||
#define SOC_MMU_ACCESS_SPIRAM BIT(9)
|
||||
#define SOC_MMU_VALID BIT(10)
|
||||
#define SOC_MMU_SENSITIVE BIT(11)
|
||||
#define SOC_MMU_INVALID_MASK BIT(10)
|
||||
#define SOC_MMU_INVALID 0
|
||||
|
||||
/**
|
||||
* MMU entry valid bit mask for mapping value. For an entry:
|
||||
* valid bit + value bits
|
||||
* valid bit is BIT(9), so value bits are 0x1ff
|
||||
*/
|
||||
#define SOC_MMU_VALID_VAL_MASK (SOC_MMU_ACCESS_SPIRAM-1)
|
||||
/**
|
||||
* Max MMU available paddr page num.
|
||||
* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* 256 * 64KB, means MMU can support 16MB paddr at most
|
||||
*/
|
||||
#define SOC_MMU_MAX_PADDR_PAGE_NUM 512
|
||||
//MMU entry num
|
||||
#define SOC_MMU_ENTRY_NUM 512
|
||||
|
||||
/**
|
||||
* This is the mask used for mapping. e.g.:
|
||||
* 0x4200_0000 & SOC_MMU_VADDR_MASK
|
||||
*/
|
||||
#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
#define SOC_MMU_DBUS_VADDR_BASE 0x42000000
|
||||
#define SOC_MMU_IBUS_VADDR_BASE 0x42000000
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* MMU Linear Address
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* - 64KB MMU page size: the last 0xFFFF, which is the offset
|
||||
* - 512 MMU entries, needs 0x1FF to hold it.
|
||||
*
|
||||
* Therefore, 0x1FF,FFFF
|
||||
*/
|
||||
#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFFF
|
||||
|
||||
/**
|
||||
* - If high linear address isn't 0, this means MMU can recognize these addresses
|
||||
* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
|
||||
* Under this condition, we use the max linear space.
|
||||
*/
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* I/D share the MMU linear address range
|
||||
*/
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
63
components/soc/esp32h4/include/soc/gpio_num.h
Normal file
63
components/soc/esp32h4/include/soc/gpio_num.h
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO number
|
||||
*/
|
||||
typedef enum {
|
||||
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
|
||||
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
|
||||
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
|
||||
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */
|
||||
GPIO_NUM_3 = 3, /*!< GPIO3, input and output */
|
||||
GPIO_NUM_4 = 4, /*!< GPIO4, input and output */
|
||||
GPIO_NUM_5 = 5, /*!< GPIO5, input and output */
|
||||
GPIO_NUM_6 = 6, /*!< GPIO6, input and output */
|
||||
GPIO_NUM_7 = 7, /*!< GPIO7, input and output */
|
||||
GPIO_NUM_8 = 8, /*!< GPIO8, input and output */
|
||||
GPIO_NUM_9 = 9, /*!< GPIO9, input and output */
|
||||
GPIO_NUM_10 = 10, /*!< GPIO10, input and output */
|
||||
GPIO_NUM_11 = 11, /*!< GPIO11, input and output */
|
||||
GPIO_NUM_12 = 12, /*!< GPIO12, input and output */
|
||||
GPIO_NUM_13 = 13, /*!< GPIO13, input and output */
|
||||
GPIO_NUM_14 = 14, /*!< GPIO14, input and output */
|
||||
GPIO_NUM_15 = 15, /*!< GPIO15, input and output */
|
||||
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
|
||||
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
|
||||
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
|
||||
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
|
||||
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
|
||||
GPIO_NUM_21 = 21, /*!< GPIO21, input and output */
|
||||
GPIO_NUM_22 = 22, /*!< GPIO22, input and output */
|
||||
GPIO_NUM_23 = 23, /*!< GPIO23, input and output */
|
||||
GPIO_NUM_24 = 24, /*!< GPIO24, input and output */
|
||||
GPIO_NUM_25 = 25, /*!< GPIO25, input and output */
|
||||
GPIO_NUM_26 = 26, /*!< GPIO26, input and output */
|
||||
GPIO_NUM_27 = 27, /*!< GPIO27, input and output */
|
||||
GPIO_NUM_28 = 28, /*!< GPIO28, input and output */
|
||||
GPIO_NUM_29 = 29, /*!< GPIO29, input and output */
|
||||
GPIO_NUM_30 = 30, /*!< GPIO30, input and output */
|
||||
GPIO_NUM_31 = 31, /*!< GPIO31, input and output */
|
||||
GPIO_NUM_32 = 32, /*!< GPIO32, input and output */
|
||||
GPIO_NUM_33 = 33, /*!< GPIO33, input and output */
|
||||
GPIO_NUM_34 = 34, /*!< GPIO34, input and output */
|
||||
GPIO_NUM_35 = 35, /*!< GPIO35, input and output */
|
||||
GPIO_NUM_36 = 36, /*!< GPIO36, input and output */
|
||||
GPIO_NUM_37 = 37, /*!< GPIO37, input and output */
|
||||
GPIO_NUM_38 = 38, /*!< GPIO38, input and output */
|
||||
GPIO_NUM_39 = 39, /*!< GPIO39, input and output */
|
||||
GPIO_NUM_MAX,
|
||||
} gpio_num_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
20
components/soc/esp32h4/include/soc/gpio_pins.h
Normal file
20
components/soc/esp32h4/include/soc/gpio_pins.h
Normal file
@ -0,0 +1,20 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: [ESP32H4] IDF-12390 inherit from verify code, need check
|
||||
|
||||
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
|
||||
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
222
components/soc/esp32h4/include/soc/i2c_ana_mst_reg.h
Normal file
222
components/soc/esp32h4/include/soc/i2c_ana_mst_reg.h
Normal file
@ -0,0 +1,222 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//TODO: [ESP32H4] IDF-12315 inherit from verify code, need check
|
||||
|
||||
#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
|
||||
/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_BUSY (BIT(25))
|
||||
#define I2C_ANA_MST_I2C0_BUSY_M (BIT(25))
|
||||
#define I2C_ANA_MST_I2C0_BUSY_V 0x1
|
||||
#define I2C_ANA_MST_I2C0_BUSY_S 25
|
||||
/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF
|
||||
#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S))
|
||||
#define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF
|
||||
#define I2C_ANA_MST_I2C0_CTRL_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4)
|
||||
/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_BUSY (BIT(25))
|
||||
#define I2C_ANA_MST_I2C1_BUSY_M (BIT(25))
|
||||
#define I2C_ANA_MST_I2C1_BUSY_V 0x1
|
||||
#define I2C_ANA_MST_I2C1_BUSY_S 25
|
||||
/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF
|
||||
#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S))
|
||||
#define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF
|
||||
#define I2C_ANA_MST_I2C1_CTRL_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
|
||||
/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_STATUS 0x000000FF
|
||||
#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S))
|
||||
#define I2C_ANA_MST_I2C0_STATUS_V 0xFF
|
||||
#define I2C_ANA_MST_I2C0_STATUS_S 24
|
||||
/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF
|
||||
#define I2C_ANA_MST_I2C0_CONF_M ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S))
|
||||
#define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_I2C0_CONF_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC)
|
||||
/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_STATUS 0x000000FF
|
||||
#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S))
|
||||
#define I2C_ANA_MST_I2C1_STATUS_V 0xFF
|
||||
#define I2C_ANA_MST_I2C1_STATUS_S 24
|
||||
/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF
|
||||
#define I2C_ANA_MST_I2C1_CONF_M ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S))
|
||||
#define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_I2C1_CONF_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
|
||||
/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF
|
||||
#define I2C_ANA_MST_BURST_CTRL_M ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S))
|
||||
#define I2C_ANA_MST_BURST_CTRL_V 0xFFFFFFFF
|
||||
#define I2C_ANA_MST_BURST_CTRL_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14)
|
||||
/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF
|
||||
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S))
|
||||
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF
|
||||
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20
|
||||
/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2))
|
||||
#define I2C_ANA_MST1_BURST_ERR_FLAG_M (BIT(2))
|
||||
#define I2C_ANA_MST1_BURST_ERR_FLAG_V 0x1
|
||||
#define I2C_ANA_MST1_BURST_ERR_FLAG_S 2
|
||||
/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1))
|
||||
#define I2C_ANA_MST0_BURST_ERR_FLAG_M (BIT(1))
|
||||
#define I2C_ANA_MST0_BURST_ERR_FLAG_V 0x1
|
||||
#define I2C_ANA_MST0_BURST_ERR_FLAG_S 1
|
||||
/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_BURST_DONE (BIT(0))
|
||||
#define I2C_ANA_MST_BURST_DONE_M (BIT(0))
|
||||
#define I2C_ANA_MST_BURST_DONE_V 0x1
|
||||
#define I2C_ANA_MST_BURST_DONE_S 0
|
||||
|
||||
#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
|
||||
/* I2C_ANA_MST_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_STATUS0 0x000000FF
|
||||
#define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_STATUS0_V)<<(I2C_ANA_MST_STATUS0_S))
|
||||
#define I2C_ANA_MST_ANA_STATUS0_V 0xFF
|
||||
#define I2C_ANA_MST_ANA_STATUS0_S 24
|
||||
/* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S))
|
||||
#define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF0_S 0
|
||||
|
||||
#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C)
|
||||
/* I2C_ANA_MST_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_STATUS1 0x000000FF
|
||||
#define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S))
|
||||
#define I2C_ANA_MST_ANA_STATUS1_V 0xFF
|
||||
#define I2C_ANA_MST_ANA_STATUS1_S 24
|
||||
/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S))
|
||||
#define I2C_ANA_MST_ANA_CONF1_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF1_S 0
|
||||
|
||||
#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
|
||||
/* I2C_ANA_MST_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_STATUS2 0x000000FF
|
||||
#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_STATUS2_V)<<(I2C_ANA_MST_STATUS2_S))
|
||||
#define I2C_ANA_MST_ANA_STATUS2_V 0xFF
|
||||
#define I2C_ANA_MST_ANA_STATUS2_S 24
|
||||
/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF2_M ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S))
|
||||
#define I2C_ANA_MST_ANA_CONF2_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF2_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24)
|
||||
/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F
|
||||
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S))
|
||||
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F
|
||||
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6
|
||||
/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F
|
||||
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S))
|
||||
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F
|
||||
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28)
|
||||
/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F
|
||||
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S))
|
||||
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F
|
||||
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6
|
||||
/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F
|
||||
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S))
|
||||
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F
|
||||
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0
|
||||
|
||||
#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C)
|
||||
/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ARBITER_DIS (BIT(11))
|
||||
#define I2C_ANA_MST_ARBITER_DIS_M (BIT(11))
|
||||
#define I2C_ANA_MST_ARBITER_DIS_V 0x1
|
||||
#define I2C_ANA_MST_ARBITER_DIS_S 11
|
||||
/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F
|
||||
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S))
|
||||
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F
|
||||
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6
|
||||
/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F
|
||||
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S))
|
||||
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F
|
||||
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0
|
||||
|
||||
#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30)
|
||||
/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_NOUSE 0xFFFFFFFF
|
||||
#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S))
|
||||
#define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF
|
||||
#define I2C_ANA_MST_NOUSE_S 0
|
||||
|
||||
#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
|
||||
/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_CLK_EN (BIT(28))
|
||||
#define I2C_ANA_MST_CLK_EN_M (BIT(28))
|
||||
#define I2C_ANA_MST_CLK_EN_V 0x1
|
||||
#define I2C_ANA_MST_CLK_EN_S 28
|
||||
/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_DATE 0x0FFFFFFF
|
||||
#define I2C_ANA_MST_DATE_M ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S))
|
||||
#define I2C_ANA_MST_DATE_V 0xFFFFFFF
|
||||
#define I2C_ANA_MST_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
14
components/soc/esp32h4/include/soc/interrupt_reg.h
Normal file
14
components/soc/esp32h4/include/soc/interrupt_reg.h
Normal file
@ -0,0 +1,14 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/interrupt_matrix_reg.h"
|
||||
#include "soc/clic_reg.h"
|
||||
#include "soc/soc_caps.h"
|
||||
|
||||
// TODO: [ESP32H4] IDF-12303 inherit from verify code, need check
|
||||
|
||||
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
|
||||
#define INTERRUPT_OTHER_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF)
|
||||
@ -8,7 +8,7 @@
|
||||
|
||||
#define DR_REG_TRACE0_BASE 0x60000000
|
||||
#define DR_REG_TRACE1_BASE 0x60001000
|
||||
#define DR_REG_ASSIST_DEBUG_BASE 0x60002000
|
||||
#define DR_REG_BUS_MONITOR_BASE 0x60002000
|
||||
#define DR_REG_INTPRI_BASE 0x60005000
|
||||
#define DR_REG_CACHE_BASE 0x60008000
|
||||
#define DR_REG_GPSPI2_BASE 0x60010000
|
||||
@ -77,3 +77,4 @@
|
||||
#define DR_REG_TOUCH_AON_BASE 0x600B5C00
|
||||
|
||||
#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 // TODO: [ESP32H4] IDF-12315 inherit from verify code, need check
|
||||
#define DR_REG_CLINT_M_BASE 0x20000000 // TODO: [ESP32H4] IDF-12303 inherit from verify code, need check
|
||||
|
||||
175
components/soc/esp32h4/include/soc/regi2c_bbpll.h
Normal file
175
components/soc/esp32h4/include/soc/regi2c_bbpll.h
Normal file
@ -0,0 +1,175 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_bbpll.h
|
||||
* @brief Register definitions for digital PLL (BBPLL)
|
||||
*
|
||||
* This file lists register fields of BBPLL, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
|
||||
* rtc_clk_cpu_freq_set function in rtc_clk.c.
|
||||
*/
|
||||
|
||||
#define I2C_BBPLL 0x66
|
||||
#define I2C_BBPLL_HOSTID 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_DELAY 0
|
||||
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
|
||||
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV 0
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_RSTB 1
|
||||
#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
|
||||
#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_START 1
|
||||
#define I2C_BBPLL_IR_CAL_START_MSB 6
|
||||
#define I2C_BBPLL_IR_CAL_START_LSB 6
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP 1
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_REF_DIV 2
|
||||
#define I2C_BBPLL_OC_REF_DIV_MSB 3
|
||||
#define I2C_BBPLL_OC_REF_DIV_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OC_DCHGP 2
|
||||
#define I2C_BBPLL_OC_DCHGP_MSB 6
|
||||
#define I2C_BBPLL_OC_DCHGP_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OC_ENB_FCAL 2
|
||||
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
|
||||
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DIV_7_0 3
|
||||
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
|
||||
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
|
||||
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC 4
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
|
||||
|
||||
#define I2C_BBPLL_MODE_HF 4
|
||||
#define I2C_BBPLL_MODE_HF_MSB 1
|
||||
#define I2C_BBPLL_MODE_HF_LSB 1
|
||||
|
||||
#define I2C_BBPLL_DIV_ADC 4
|
||||
#define I2C_BBPLL_DIV_ADC_MSB 3
|
||||
#define I2C_BBPLL_DIV_ADC_LSB 2
|
||||
|
||||
#define I2C_BBPLL_DIV_DAC 4
|
||||
#define I2C_BBPLL_DIV_DAC_MSB 4
|
||||
#define I2C_BBPLL_DIV_DAC_LSB 4
|
||||
|
||||
#define I2C_BBPLL_DIV_CPU 4
|
||||
#define I2C_BBPLL_DIV_CPU_MSB 5
|
||||
#define I2C_BBPLL_DIV_CPU_LSB 5
|
||||
|
||||
#define I2C_BBPLL_OC_ENB_VCON 4
|
||||
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
|
||||
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OC_TSCHGP 4
|
||||
#define I2C_BBPLL_OC_TSCHGP_MSB 7
|
||||
#define I2C_BBPLL_OC_TSCHGP_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DR1 5
|
||||
#define I2C_BBPLL_OC_DR1_MSB 2
|
||||
#define I2C_BBPLL_OC_DR1_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OC_DR3 5
|
||||
#define I2C_BBPLL_OC_DR3_MSB 6
|
||||
#define I2C_BBPLL_OC_DR3_LSB 4
|
||||
|
||||
#define I2C_BBPLL_EN_USB 5
|
||||
#define I2C_BBPLL_EN_USB_MSB 7
|
||||
#define I2C_BBPLL_EN_USB_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DCUR 6
|
||||
#define I2C_BBPLL_OC_DCUR_MSB 2
|
||||
#define I2C_BBPLL_OC_DCUR_LSB 0
|
||||
|
||||
#define I2C_BBPLL_INC_CUR 6
|
||||
#define I2C_BBPLL_INC_CUR_MSB 3
|
||||
#define I2C_BBPLL_INC_CUR_LSB 3
|
||||
|
||||
#define I2C_BBPLL_OC_DHREF_SEL 6
|
||||
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
|
||||
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OC_DLREF_SEL 6
|
||||
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
|
||||
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_CAP 8
|
||||
#define I2C_BBPLL_OR_CAL_CAP_MSB 3
|
||||
#define I2C_BBPLL_OR_CAL_CAP_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_UDF 8
|
||||
#define I2C_BBPLL_OR_CAL_UDF_MSB 4
|
||||
#define I2C_BBPLL_OR_CAL_UDF_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_OVF 8
|
||||
#define I2C_BBPLL_OR_CAL_OVF_MSB 5
|
||||
#define I2C_BBPLL_OR_CAL_OVF_LSB 5
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_END 8
|
||||
#define I2C_BBPLL_OR_CAL_END_MSB 6
|
||||
#define I2C_BBPLL_OR_CAL_END_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OR_LOCK 8
|
||||
#define I2C_BBPLL_OR_LOCK_MSB 7
|
||||
#define I2C_BBPLL_OR_LOCK_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_VCO_DBIAS 9
|
||||
#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1
|
||||
#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0
|
||||
|
||||
#define I2C_BBPLL_BBADC_DELAY2 9
|
||||
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
|
||||
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
|
||||
|
||||
#define I2C_BBPLL_BBADC_DVDD 9
|
||||
#define I2C_BBPLL_BBADC_DVDD_MSB 5
|
||||
#define I2C_BBPLL_BBADC_DVDD_LSB 4
|
||||
|
||||
#define I2C_BBPLL_BBADC_DREF 9
|
||||
#define I2C_BBPLL_BBADC_DREF_MSB 7
|
||||
#define I2C_BBPLL_BBADC_DREF_LSB 6
|
||||
|
||||
#define I2C_BBPLL_BBADC_DCUR 10
|
||||
#define I2C_BBPLL_BBADC_DCUR_MSB 1
|
||||
#define I2C_BBPLL_BBADC_DCUR_LSB 0
|
||||
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
|
||||
|
||||
#define I2C_BBPLL_ENT_PLL 10
|
||||
#define I2C_BBPLL_ENT_PLL_MSB 3
|
||||
#define I2C_BBPLL_ENT_PLL_LSB 3
|
||||
|
||||
#define I2C_BBPLL_DTEST 10
|
||||
#define I2C_BBPLL_DTEST_MSB 5
|
||||
#define I2C_BBPLL_DTEST_LSB 4
|
||||
|
||||
#define I2C_BBPLL_ENT_ADC 10
|
||||
#define I2C_BBPLL_ENT_ADC_MSB 7
|
||||
#define I2C_BBPLL_ENT_ADC_LSB 6
|
||||
22
components/soc/esp32h4/include/soc/regi2c_bias.h
Normal file
22
components/soc/esp32h4/include/soc/regi2c_bias.h
Normal file
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_bias.h
|
||||
* @brief Register definitions for bias
|
||||
*
|
||||
* This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
|
||||
* bootloader_hardware_init function in bootloader_esp32c6.c.
|
||||
*/
|
||||
|
||||
#define I2C_BIAS 0X6A
|
||||
#define I2C_BIAS_HOSTID 0
|
||||
|
||||
#define I2C_BIAS_DREG_1P1_PVT 1
|
||||
#define I2C_BIAS_DREG_1P1_PVT_MSB 3
|
||||
#define I2C_BIAS_DREG_1P1_PVT_LSB 0
|
||||
22
components/soc/esp32h4/include/soc/regi2c_brownout.h
Normal file
22
components/soc/esp32h4/include/soc/regi2c_brownout.h
Normal file
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_brownout.h
|
||||
* @brief Register definitions for brownout detector
|
||||
*
|
||||
* This file lists register fields of the brownout detector, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in regi2c_ctrl.h.
|
||||
*/
|
||||
|
||||
#define I2C_BOD 0x61
|
||||
#define I2C_BOD_HOSTID 0
|
||||
|
||||
#define I2C_BOD_THRESHOLD 0x5
|
||||
#define I2C_BOD_THRESHOLD_MSB 2
|
||||
#define I2C_BOD_THRESHOLD_LSB 0
|
||||
27
components/soc/esp32h4/include/soc/regi2c_defs.h
Normal file
27
components/soc/esp32h4/include/soc/regi2c_defs.h
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
/* Analog function control register */
|
||||
#define I2C_MST_ANA_CONF0_REG 0x600AF818
|
||||
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
|
||||
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
|
||||
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
|
||||
|
||||
#define ANA_CONFIG_REG 0x600AF81C
|
||||
#define ANA_CONFIG_S (8)
|
||||
#define ANA_CONFIG_M (0x3FF)
|
||||
|
||||
#define ANA_I2C_SAR_FORCE_PD BIT(18)
|
||||
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
|
||||
|
||||
#define ANA_CONFIG2_REG 0x600AF820
|
||||
#define ANA_CONFIG2_M BIT(18)
|
||||
|
||||
#define ANA_I2C_SAR_FORCE_PU BIT(16)
|
||||
64
components/soc/esp32h4/include/soc/regi2c_dig_reg.h
Normal file
64
components/soc/esp32h4/include/soc/regi2c_dig_reg.h
Normal file
@ -0,0 +1,64 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_dig_reg.h
|
||||
* @brief Register definitions for digital to get rtc voltage & digital voltage
|
||||
* by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
|
||||
*/
|
||||
|
||||
#define I2C_DIG_REG 0x6D
|
||||
#define I2C_DIG_REG_HOSTID 0
|
||||
|
||||
#define I2C_DIG_REG_EXT_RTC_DREG 4
|
||||
#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4
|
||||
#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0
|
||||
|
||||
#define I2C_DIG_REG_ENX_RTC_DREG 4
|
||||
#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7
|
||||
#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7
|
||||
|
||||
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5
|
||||
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4
|
||||
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0
|
||||
|
||||
#define I2C_DIG_REG_ENIF_RTC_DREG 5
|
||||
#define I2C_DIG_REG_ENIF_RTC_DREG_MSB 7
|
||||
#define I2C_DIG_REG_ENIF_RTC_DREG_LSB 7
|
||||
|
||||
#define I2C_DIG_REG_EXT_DIG_DREG 6
|
||||
#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4
|
||||
#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0
|
||||
|
||||
#define I2C_DIG_REG_ENX_DIG_DREG 6
|
||||
#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7
|
||||
#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7
|
||||
|
||||
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7
|
||||
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4
|
||||
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0
|
||||
|
||||
#define I2C_DIG_REG_ENIF_DIG_DREG 7
|
||||
#define I2C_DIG_REG_ENIF_DIG_DREG_MSB 7
|
||||
#define I2C_DIG_REG_ENIF_DIG_DREG_LSB 7
|
||||
|
||||
#define I2C_DIG_REG_OR_EN_CONT_CAL 9
|
||||
#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7
|
||||
#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7
|
||||
|
||||
#define I2C_DIG_REG_XPD_RTC_REG 13
|
||||
#define I2C_DIG_REG_XPD_RTC_REG_MSB 2
|
||||
#define I2C_DIG_REG_XPD_RTC_REG_LSB 2
|
||||
|
||||
#define I2C_DIG_REG_XPD_DIG_REG 13
|
||||
#define I2C_DIG_REG_XPD_DIG_REG_MSB 3
|
||||
#define I2C_DIG_REG_XPD_DIG_REG_LSB 3
|
||||
|
||||
#define I2C_DIG_REG_SCK_DCAP 14
|
||||
#define I2C_DIG_REG_SCK_DCAP_MSB 7
|
||||
#define I2C_DIG_REG_SCK_DCAP_LSB 0
|
||||
55
components/soc/esp32h4/include/soc/regi2c_lp_bias.h
Normal file
55
components/soc/esp32h4/include/soc/regi2c_lp_bias.h
Normal file
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_lp_bias.h
|
||||
* @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
|
||||
*
|
||||
* This file lists register fields of low power dbais, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
|
||||
* rtc_init function in rtc_init.c.
|
||||
*/
|
||||
|
||||
#define I2C_ULP 0x61
|
||||
#define I2C_ULP_HOSTID 0
|
||||
|
||||
#define I2C_ULP_IR_RESETB 0
|
||||
#define I2C_ULP_IR_RESETB_MSB 0
|
||||
#define I2C_ULP_IR_RESETB_LSB 0
|
||||
|
||||
#define I2C_ULP_IR_FORCE_XPD_CK 0
|
||||
#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2
|
||||
#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2
|
||||
|
||||
#define I2C_ULP_IR_FORCE_XPD_IPH 0
|
||||
#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4
|
||||
#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4
|
||||
|
||||
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0
|
||||
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6
|
||||
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6
|
||||
|
||||
#define I2C_ULP_O_DONE_FLAG 3
|
||||
#define I2C_ULP_O_DONE_FLAG_MSB 0
|
||||
#define I2C_ULP_O_DONE_FLAG_LSB 0
|
||||
|
||||
#define I2C_ULP_BG_O_DONE_FLAG 3
|
||||
#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
|
||||
#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
|
||||
|
||||
#define I2C_ULP_OCODE 4
|
||||
#define I2C_ULP_OCODE_MSB 7
|
||||
#define I2C_ULP_OCODE_LSB 0
|
||||
|
||||
#define I2C_ULP_IR_FORCE_CODE 5
|
||||
#define I2C_ULP_IR_FORCE_CODE_MSB 6
|
||||
#define I2C_ULP_IR_FORCE_CODE_LSB 6
|
||||
|
||||
#define I2C_ULP_EXT_CODE 6
|
||||
#define I2C_ULP_EXT_CODE_MSB 7
|
||||
#define I2C_ULP_EXT_CODE_LSB 0
|
||||
0
components/soc/esp32h4/include/soc/regi2c_saradc.h
Normal file
0
components/soc/esp32h4/include/soc/regi2c_saradc.h
Normal file
54
components/soc/esp32h4/include/soc/reset_reasons.h
Normal file
54
components/soc/esp32h4/include/soc/reset_reasons.h
Normal file
@ -0,0 +1,54 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
//+-----------------------------------------------Terminology---------------------------------------------+
|
||||
//| |
|
||||
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
|
||||
//| |
|
||||
//| Core Reset: Reset the whole digital system except RTC sub-system |
|
||||
//| |
|
||||
//| System Reset: Reset the whole digital system, including RTC sub-system |
|
||||
//| |
|
||||
//| Chip Reset: Reset the whole chip, including the analog part |
|
||||
//| |
|
||||
//+-------------------------------------------------------------------------------------------------------+
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//TODO: [ESP32H4] IDF-12307 inherit from verify code, need check
|
||||
|
||||
/**
|
||||
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
|
||||
* @note refer to TRM: <Reset and Clock> chapter
|
||||
*/
|
||||
typedef enum {
|
||||
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
|
||||
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
|
||||
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core (hp system) by LP_AON_HPSYS_SW_RESET
|
||||
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core (hp system)
|
||||
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core (hp system)
|
||||
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core (hp system)
|
||||
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core (hp system)
|
||||
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
|
||||
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by LP_AON_CPU_CORE0_SW_RESET
|
||||
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
|
||||
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
|
||||
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
|
||||
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
|
||||
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
|
||||
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core (hp system)
|
||||
RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core (hp system)
|
||||
RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core (hp system)
|
||||
RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0
|
||||
} soc_reset_reason_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
229
components/soc/esp32h4/include/soc/soc.h
Normal file
229
components/soc/esp32h4/include/soc/soc.h
Normal file
@ -0,0 +1,229 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
#include "esp_assert.h"
|
||||
#endif
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
#include "reg_base.h"
|
||||
|
||||
#define PRO_CPU_NUM (0)
|
||||
|
||||
//Registers Operation {{
|
||||
#define ETS_UNCACHED_ADDR(addr) (addr)
|
||||
#define ETS_CACHED_ADDR(addr) (addr)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
//write value to register
|
||||
#define REG_WRITE(_r, _v) do { \
|
||||
(*(volatile uint32_t *)(_r)) = (_v); \
|
||||
} while(0)
|
||||
|
||||
//read value from register
|
||||
#define REG_READ(_r) ({ \
|
||||
(*(volatile uint32_t *)(_r)); \
|
||||
})
|
||||
|
||||
//get bit or get bits from register
|
||||
#define REG_GET_BIT(_r, _b) ({ \
|
||||
(*(volatile uint32_t*)(_r) & (_b)); \
|
||||
})
|
||||
|
||||
//set bit or set bits to register
|
||||
#define REG_SET_BIT(_r, _b) do { \
|
||||
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \
|
||||
} while(0)
|
||||
|
||||
//clear bit or clear bits of register
|
||||
#define REG_CLR_BIT(_r, _b) do { \
|
||||
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \
|
||||
} while(0)
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define REG_SET_BITS(_r, _b, _m) do { \
|
||||
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \
|
||||
} while(0)
|
||||
|
||||
//get field from register, uses field _S & _V to determine mask
|
||||
#define REG_GET_FIELD(_r, _f) ({ \
|
||||
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
|
||||
})
|
||||
|
||||
//set field of a register from variable, uses field _S & _V to determine mask
|
||||
#define REG_SET_FIELD(_r, _f, _v) do { \
|
||||
REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \
|
||||
} while(0)
|
||||
|
||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
|
||||
//get field value from a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
|
||||
|
||||
//set field value to a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
|
||||
|
||||
//set field value to a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
|
||||
|
||||
//generate a value from a field value, used when _f is not left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
|
||||
|
||||
//generate a value from a field value, used when _f is left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||
|
||||
//read value from register
|
||||
#define READ_PERI_REG(addr) ({ \
|
||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
|
||||
})
|
||||
|
||||
//write value to register
|
||||
#define WRITE_PERI_REG(addr, val) do { \
|
||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
|
||||
} while(0)
|
||||
|
||||
//clear bits of register controlled by mask
|
||||
#define CLEAR_PERI_REG_MASK(reg, mask) do { \
|
||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
|
||||
} while(0)
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define SET_PERI_REG_MASK(reg, mask) do { \
|
||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
|
||||
} while(0)
|
||||
|
||||
//get bits of register controlled by mask
|
||||
#define GET_PERI_REG_MASK(reg, mask) ({ \
|
||||
(READ_PERI_REG(reg) & (mask)); \
|
||||
})
|
||||
|
||||
//get bits of register controlled by highest bit and lowest bit
|
||||
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
|
||||
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
|
||||
})
|
||||
|
||||
//set bits of register controlled by mask and shift
|
||||
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \
|
||||
WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \
|
||||
} while(0)
|
||||
|
||||
//get field of register
|
||||
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
|
||||
((READ_PERI_REG(reg)>>(shift))&(mask)); \
|
||||
})
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
//}}
|
||||
|
||||
//Periheral Clock {{
|
||||
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
|
||||
#define APB_CLK_FREQ ( 40*1000000 )
|
||||
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 )
|
||||
#define REF_CLK_FREQ ( 1000000 )
|
||||
#define XTAL_CLK_FREQ (40*1000000)
|
||||
//}}
|
||||
|
||||
/* Overall memory map */
|
||||
/* Note: We should not use MACROs similar in cache_memory.h
|
||||
* those are defined during run-time. But the MACROs here
|
||||
* should be defined statically!
|
||||
*/
|
||||
|
||||
// TODO：[ESP32H4] IDF-12518 check address
|
||||
#define SOC_IROM_LOW 0x42000000
|
||||
#define SOC_IROM_HIGH 0x44000000
|
||||
#define SOC_EXTRAM_DATA_LOW 0x42000000
|
||||
#define SOC_EXTRAM_DATA_HIGH 0x44000000
|
||||
#define SOC_DROM_LOW SOC_IROM_LOW
|
||||
#define SOC_DROM_HIGH SOC_IROM_HIGH
|
||||
#define SOC_IROM_MASK_LOW 0x40000000
|
||||
#define SOC_IROM_MASK_HIGH 0x40050000
|
||||
#define SOC_DROM_MASK_LOW 0x40000000
|
||||
#define SOC_DROM_MASK_HIGH 0x40050000
|
||||
#define SOC_IRAM_LOW 0x40810000
|
||||
#define SOC_IRAM_HIGH 0x40860000
|
||||
#define SOC_DRAM_LOW 0x40810000
|
||||
#define SOC_DRAM_HIGH 0x40860000
|
||||
#define SOC_RTC_IRAM_LOW 0x50000000 // TODO：[ESP32H4] IDF-12303 inherit from verify code, need remove
|
||||
#define SOC_RTC_IRAM_HIGH 0x50004000
|
||||
#define SOC_RTC_DRAM_LOW 0x50000000
|
||||
#define SOC_RTC_DRAM_HIGH 0x50004000
|
||||
#define SOC_RTC_DATA_LOW 0x50000000
|
||||
#define SOC_RTC_DATA_HIGH 0x50004000
|
||||
|
||||
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
|
||||
#define SOC_DIRAM_IRAM_LOW 0x40810000
|
||||
#define SOC_DIRAM_IRAM_HIGH 0x40860000
|
||||
#define SOC_DIRAM_DRAM_LOW 0x40810000
|
||||
#define SOC_DIRAM_DRAM_HIGH 0x40860000
|
||||
|
||||
#define MAP_DRAM_TO_IRAM(addr) (addr)
|
||||
#define MAP_IRAM_TO_DRAM(addr) (addr)
|
||||
|
||||
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
|
||||
#define SOC_DMA_LOW 0x40810000
|
||||
#define SOC_DMA_HIGH 0x40860000
|
||||
|
||||
// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
|
||||
#define SOC_BYTE_ACCESSIBLE_LOW 0x40810000
|
||||
#define SOC_BYTE_ACCESSIBLE_HIGH 0x40860000
|
||||
|
||||
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
|
||||
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
|
||||
#define SOC_MEM_INTERNAL_LOW 0x40810000
|
||||
#define SOC_MEM_INTERNAL_HIGH 0x40860000
|
||||
#define SOC_MEM_INTERNAL_LOW1 0x40810000
|
||||
#define SOC_MEM_INTERNAL_HIGH1 0x40860000
|
||||
|
||||
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IROM_HIGH - SOC_IROM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
|
||||
|
||||
// Region of address space that holds peripherals
|
||||
#define SOC_PERIPHERAL_LOW 0x60000000
|
||||
#define SOC_PERIPHERAL_HIGH 0x60100000
|
||||
|
||||
// Debug region, not used by software
|
||||
#define SOC_DEBUG_LOW 0x20000000
|
||||
#define SOC_DEBUG_HIGH 0x28000000
|
||||
|
||||
// Start (highest address) of ROM boot stack, only relevant during early boot
|
||||
#define SOC_ROM_STACK_START 0x4085d350
|
||||
#define SOC_ROM_STACK_SIZE 0x2000
|
||||
|
||||
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
|
||||
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
|
||||
|
||||
//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying
|
||||
#define ETS_T1_WDT_INUM 24
|
||||
#define ETS_CACHEERR_INUM 25
|
||||
#define ETS_MEMPROT_ERR_INUM 26
|
||||
#define ETS_ASSIST_DEBUG_INUM 27 // Note: this interrupt can be combined with others (e.g., CACHEERR), as we can identify its trigger is activated
|
||||
#define ETS_IPC_ISR_INUM 28
|
||||
//CPU0 Max valid interrupt number
|
||||
#define ETS_MAX_INUM 31
|
||||
|
||||
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
|
||||
#define ETS_SLC_INUM 1
|
||||
#define ETS_UART0_INUM 5
|
||||
#define ETS_UART1_INUM 5
|
||||
#define ETS_SPI2_INUM 1
|
||||
//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
|
||||
#define ETS_GPIO_INUM 4
|
||||
|
||||
//Other interrupt number should be managed by the user
|
||||
|
||||
//Invalid interrupt for number interrupt matrix
|
||||
#define ETS_INVALID_INUM 0
|
||||
|
||||
//Interrupt medium level, used for INT WDT for example
|
||||
#define SOC_INTERRUPT_LEVEL_MEDIUM 4
|
||||
|
||||
// Interrupt number for the Interrupt watchdog
|
||||
#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM)
|
||||
546
components/soc/esp32h4/include/soc/soc_caps.h
Normal file
546
components/soc/esp32h4/include/soc/soc_caps.h
Normal file
@ -0,0 +1,546 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The long term plan is to have a single soc_caps.h for each peripheral.
|
||||
// During the refactoring and multichip support development process, we
|
||||
// separate these information into periph_caps.h for each peripheral and
|
||||
// include them here.
|
||||
|
||||
/*
|
||||
* These defines are parsed and imported as kconfig variables via the script
|
||||
* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
|
||||
*
|
||||
* If this file is changed the script will automatically run the script
|
||||
* and generate the kconfig variables as part of the pre-commit hooks.
|
||||
*
|
||||
* It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py -d 'components/soc/esp32c6/include/soc/'`
|
||||
*
|
||||
* For more information see `tools/gen_soc_caps_kconfig/README.md`
|
||||
*
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/*-------------------------- COMMON CAPS ---------------------------------------*/
|
||||
// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12368 IDF-12370
|
||||
// #define SOC_ANA_CMPR_SUPPORTED 1 // TODO: [ESP32H4] IDF-12395 big change!!
|
||||
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32H4] IDF-12401
|
||||
#define SOC_UART_SUPPORTED 1 // TODO: [ESP32H4] IDF-12398
|
||||
// #define SOC_GDMA_SUPPORTED 1 // TODO: [ESP32H4] IDF-12382
|
||||
// #define SOC_AHB_GDMA_SUPPORTED 1 // TODO: [ESP32H4] IDF-12382
|
||||
// #define SOC_GPTIMER_SUPPORTED 1 // TODO: [ESP32H4] IDF-12373
|
||||
// #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12338
|
||||
// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12380
|
||||
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32H4] IDF-12352
|
||||
// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12355
|
||||
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32H4] IDF-12345 IDF-12347
|
||||
// #define SOC_BT_SUPPORTED 1
|
||||
// #define SOC_IEEE802154_SUPPORTED 1
|
||||
// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 // TODO: [ESP32H4] IDF-12382
|
||||
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32H4] IDF-12396
|
||||
// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32H4] IDF-12404
|
||||
// #define SOC_SUPPORTS_SECURE_DL_MODE 1
|
||||
// #define SOC_ULP_SUPPORTED 0 // TODO: [ESP32H4] IDF-12396
|
||||
// #define SOC_LP_CORE_SUPPORTED 0
|
||||
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32H4] IDF-12268
|
||||
#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32H4] IDF-12268
|
||||
// #define SOC_RTC_FAST_MEM_SUPPORTED 0
|
||||
// #define SOC_RTC_MEM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12313
|
||||
// #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32H4] IDF-12385
|
||||
// #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12402
|
||||
// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12348
|
||||
// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32H4] IDF-12362 IDF-12364 IDF-12366
|
||||
// #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12343
|
||||
// #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32H4] IDF-12357 IDF-12359
|
||||
#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32H4] IDF-12375 IDF-12377
|
||||
// #define SOC_SUPPORT_COEXISTENCE 1 // TODO: [ESP32H4] IDF-12251 IDF-12252 IDF-12253
|
||||
// #define SOC_AES_SUPPORTED 0 // TODO: [ESP32H4] IDF-12266
|
||||
// #define SOC_MPI_SUPPORTED 0
|
||||
// #define SOC_SHA_SUPPORTED 1 // TODO: [ESP32H4] IDF-12263
|
||||
// #define SOC_HMAC_SUPPORTED 0 // TODO: [ESP32H4] IDF-12257
|
||||
// #define SOC_DIG_SIGN_SUPPORTED 0 // TODO: [ESP32H4] IDF-12443
|
||||
// #define SOC_ECC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12264
|
||||
#define SOC_FLASH_ENC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12261
|
||||
// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12262
|
||||
|
||||
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32H4] IDF-12295
|
||||
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12256
|
||||
// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32H4] IDF-12286
|
||||
// #define SOC_PAU_SUPPORTED 1
|
||||
// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32H4] IDF-12274
|
||||
// #define SOC_LP_AON_SUPPORTED 1
|
||||
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
|
||||
// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32H4] IDF-12449
|
||||
// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32H4] IDF-12445 IDF-12451
|
||||
// #define SOC_CLK_TREE_SUPPORTED 1 // TODO: [ESP32H4] IDF-12285
|
||||
// #define SOC_ASSIST_DEBUG_SUPPORTED 1 // TODO: [ESP32H4] IDF-12310
|
||||
// #define SOC_WDT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12293
|
||||
#define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32H4] IDF-12388
|
||||
// #define SOC_SPIRAM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12351
|
||||
|
||||
/*-------------------------- XTAL CAPS ---------------------------------------*/
|
||||
#define SOC_XTAL_SUPPORT_32M 1
|
||||
|
||||
/*-------------------------- AES CAPS -----------------------------------------*/
|
||||
#define SOC_AES_SUPPORT_DMA (1)
|
||||
|
||||
/* Has a centralized DMA, which is shared with all peripherals */
|
||||
#define SOC_AES_GDMA (1)
|
||||
|
||||
#define SOC_AES_SUPPORT_AES_128 (1)
|
||||
#define SOC_AES_SUPPORT_AES_256 (1)
|
||||
|
||||
/*-------------------------- ADC CAPS -------------------------------*/
|
||||
/*!< SAR ADC Module*/
|
||||
// #define SOC_ADC_DIG_CTRL_SUPPORTED 1
|
||||
// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
|
||||
// #define SOC_ADC_MONITOR_SUPPORTED 1
|
||||
// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
|
||||
// #define SOC_ADC_DMA_SUPPORTED 1
|
||||
#define SOC_ADC_PERIPH_NUM (1U)
|
||||
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7)
|
||||
#define SOC_ADC_MAX_CHANNEL_NUM (7)
|
||||
#define SOC_ADC_ATTEN_NUM (4)
|
||||
|
||||
/*!< Digital */
|
||||
// #define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
|
||||
// #define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
|
||||
// #define SOC_ADC_DIGI_MAX_BITWIDTH (12)
|
||||
// #define SOC_ADC_DIGI_MIN_BITWIDTH (12)
|
||||
// #define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
|
||||
// #define SOC_ADC_DIGI_MONITOR_NUM (2)
|
||||
// #define SOC_ADC_DIGI_RESULT_BYTES (4)
|
||||
// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
|
||||
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
|
||||
// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
|
||||
// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
|
||||
|
||||
/*!< RTC */
|
||||
// #define SOC_ADC_RTC_MIN_BITWIDTH (12)
|
||||
// #define SOC_ADC_RTC_MAX_BITWIDTH (12)
|
||||
|
||||
/*!< Calibration */
|
||||
// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
|
||||
// #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
|
||||
// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
|
||||
|
||||
/*!< Interrupt */
|
||||
// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1)
|
||||
|
||||
/*!< ADC power control is shared by PWDET */
|
||||
// #define SOC_ADC_SHARED_POWER 1
|
||||
|
||||
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
|
||||
#define SOC_APB_BACKUP_DMA (0)
|
||||
|
||||
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
|
||||
// #define SOC_BROWNOUT_RESET_SUPPORTED 1
|
||||
|
||||
/*-------------------------- CACHE CAPS --------------------------------------*/
|
||||
// #define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
|
||||
// #define SOC_CACHE_FREEZE_SUPPORTED 1
|
||||
|
||||
/*-------------------------- CPU CAPS ----------------------------------------*/
|
||||
#define SOC_CPU_CORES_NUM (2U)
|
||||
#define SOC_CPU_INTR_NUM 32
|
||||
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
|
||||
#define SOC_INT_PLIC_SUPPORTED 0 //riscv platform-level interrupt controller
|
||||
#define SOC_INT_CLIC_SUPPORTED 1
|
||||
#define SOC_INT_HW_NESTED_SUPPORTED 1 // Support for hardware interrupts nesting
|
||||
#define SOC_BRANCH_PREDICTOR_SUPPORTED 1
|
||||
#define SOC_CPU_HAS_FPU 1
|
||||
#define SOC_CPU_HAS_FPU_EXT_ILL_BUG 0 // EXT_ILL CSR doesn't support FLW/FSW
|
||||
#define SOC_CPU_COPROC_NUM 2
|
||||
|
||||
#define SOC_CPU_BREAKPOINTS_NUM 4
|
||||
#define SOC_CPU_WATCHPOINTS_NUM 4
|
||||
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
|
||||
|
||||
#define SOC_CPU_HAS_PMA 1
|
||||
#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1
|
||||
|
||||
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
|
||||
/** The maximum length of a Digital Signature in bits. */
|
||||
// #define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
|
||||
|
||||
/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
|
||||
// #define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
|
||||
|
||||
/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
|
||||
See TRM DS chapter for more details */
|
||||
// #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
|
||||
|
||||
/*-------------------------- GDMA CAPS -------------------------------------*/
|
||||
// #define SOC_AHB_GDMA_VERSION 1U
|
||||
// #define SOC_GDMA_NUM_GROUPS_MAX 1U
|
||||
// #define SOC_GDMA_PAIRS_PER_GROUP_MAX 4
|
||||
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
|
||||
|
||||
/*-------------------------- ETM CAPS --------------------------------------*/
|
||||
// #define SOC_ETM_GROUPS 1U // Number of ETM groups
|
||||
// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
|
||||
|
||||
/*-------------------------- GPIO CAPS ---------------------------------------*/
|
||||
// ESP32-H4 has 1 GPIO peripheral
|
||||
#define SOC_GPIO_PORT 1U
|
||||
#define SOC_GPIO_PIN_COUNT 40
|
||||
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 // TODO: [ESP32H4] IDF-12391
|
||||
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 // TODO: [ESP32H4] IDF-12391
|
||||
|
||||
// GPIO peripheral has the ETM extension
|
||||
// #define SOC_GPIO_SUPPORT_ETM 1 // TODO: [ESP32H4] IDF-12394
|
||||
// #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
|
||||
// #define SOC_GPIO_ETM_TASKS_PER_GROUP 8
|
||||
|
||||
// Target has the full LP IO subsystem
|
||||
// On ESP32-H4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
|
||||
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
|
||||
// GPIO0~5 on ESP32h4 can support chip deep sleep wakeup (from verify code, need check)
|
||||
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
|
||||
|
||||
#define SOC_GPIO_VALID_GPIO_MASK ((1ULL<<SOC_GPIO_PIN_COUNT) - 1)
|
||||
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
|
||||
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
|
||||
|
||||
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
|
||||
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000FFFFFFFFC0ULL
|
||||
|
||||
// Support to force hold all IOs
|
||||
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
|
||||
// Support to hold a single digital I/O when the digital domain is powered off
|
||||
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
|
||||
|
||||
// The Clock Out signal is route to the pin by GPIO matrix
|
||||
// #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) TODO: [ESP32H4] IDF-12361
|
||||
|
||||
/*-------------------------- RTCIO CAPS --------------------------------------*/
|
||||
#define SOC_RTCIO_PIN_COUNT 6
|
||||
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
|
||||
* so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
|
||||
* when the pins are switched to RTC function.
|
||||
*/
|
||||
#define SOC_RTCIO_HOLD_SUPPORTED 1
|
||||
#define SOC_RTCIO_WAKE_SUPPORTED 1
|
||||
|
||||
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
|
||||
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
|
||||
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
|
||||
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
|
||||
|
||||
/*-------------------------- I2C CAPS ----------------------------------------*/
|
||||
// ESP32-H4 has 2 I2C
|
||||
// #define SOC_I2C_NUM (2)
|
||||
|
||||
// #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
|
||||
// #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
|
||||
// #define SOC_I2C_SUPPORT_SLAVE (1)
|
||||
|
||||
// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
|
||||
// #define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
|
||||
|
||||
// #define SOC_I2C_SUPPORT_XTAL (1)
|
||||
// #define SOC_I2C_SUPPORT_RTC (1)
|
||||
// #define SOC_I2C_SUPPORT_10BIT_ADDR (1)
|
||||
// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
|
||||
// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
|
||||
// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
|
||||
// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
|
||||
|
||||
/*-------------------------- LP_I2C CAPS -------------------------------------*/
|
||||
// ESP32-H4 has 1 LP_I2C
|
||||
// #define SOC_LP_I2C_NUM (1U)
|
||||
|
||||
// #define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */
|
||||
|
||||
/*-------------------------- I2S CAPS ----------------------------------------*/
|
||||
// #define SOC_I2S_NUM (1U)
|
||||
// #define SOC_I2S_HW_VERSION_2 (1)
|
||||
// #define SOC_I2S_SUPPORTS_XTAL (1)
|
||||
// #define SOC_I2S_SUPPORTS_PLL_F160M (1)
|
||||
// #define SOC_I2S_SUPPORTS_PCM (1)
|
||||
// #define SOC_I2S_SUPPORTS_PDM (1)
|
||||
// #define SOC_I2S_SUPPORTS_PDM_TX (1)
|
||||
// #define SOC_I2S_PDM_MAX_TX_LINES (2)
|
||||
// #define SOC_I2S_SUPPORTS_TDM (1)
|
||||
|
||||
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
||||
// #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
|
||||
// #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
|
||||
// #define SOC_LEDC_CHANNEL_NUM (6)
|
||||
// #define SOC_LEDC_TIMER_BIT_WIDTH (20)
|
||||
// #define SOC_LEDC_SUPPORT_FADE_STOP (1)
|
||||
// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
|
||||
// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
|
||||
// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
|
||||
|
||||
/*-------------------------- MMU CAPS ----------------------------------------*/
|
||||
// #define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1)
|
||||
#define SOC_MMU_PERIPH_NUM (1U)
|
||||
#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (1U)
|
||||
#define SOC_MMU_DI_VADDR_SHARED (1) /*!< D/I vaddr are shared */
|
||||
|
||||
/*-------------------------- MPU CAPS ----------------------------------------*/
|
||||
// #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
|
||||
// #define SOC_MPU_MIN_REGION_SIZE 0x20000000U
|
||||
// #define SOC_MPU_REGIONS_MAX_NUM 8
|
||||
// #define SOC_MPU_REGION_RO_SUPPORTED 0
|
||||
// #define SOC_MPU_REGION_WO_SUPPORTED 0
|
||||
|
||||
/*-------------------------- PCNT CAPS ---------------------------------------*/
|
||||
// #define SOC_PCNT_GROUPS 1U
|
||||
// #define SOC_PCNT_UNITS_PER_GROUP 4
|
||||
// #define SOC_PCNT_CHANNELS_PER_UNIT 2
|
||||
// #define SOC_PCNT_THRES_POINT_PER_UNIT 2
|
||||
// #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
|
||||
|
||||
/*--------------------------- RMT CAPS ---------------------------------------*/
|
||||
// #define SOC_RMT_GROUPS 1U /*!< One RMT group */
|
||||
// #define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */
|
||||
// #define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */
|
||||
// #define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */
|
||||
// #define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
|
||||
// #define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */
|
||||
// #define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */
|
||||
// #define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */
|
||||
// #define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */
|
||||
// #define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */
|
||||
// #define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */
|
||||
// #define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */
|
||||
// #define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */
|
||||
// #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */
|
||||
|
||||
/*-------------------------- MCPWM CAPS --------------------------------------*/
|
||||
// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
|
||||
// #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
|
||||
// #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
|
||||
// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
|
||||
// #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
|
||||
// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
|
||||
// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
|
||||
// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
|
||||
// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
|
||||
// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
|
||||
// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
|
||||
// #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
|
||||
// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
|
||||
|
||||
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
|
||||
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
|
||||
|
||||
/*-------------------------- PARLIO CAPS --------------------------------------*/
|
||||
// #define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
|
||||
// #define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
|
||||
// #define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
|
||||
// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */
|
||||
// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */
|
||||
// #define SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */
|
||||
|
||||
/*--------------------------- MPI CAPS ---------------------------------------*/
|
||||
// #define SOC_MPI_MEM_BLOCKS_NUM (4)
|
||||
// #define SOC_MPI_OPERATIONS_NUM (3)
|
||||
|
||||
/*--------------------------- RSA CAPS ---------------------------------------*/
|
||||
// #define SOC_RSA_MAX_BIT_LEN (3072)
|
||||
|
||||
/*--------------------------- SHA CAPS ---------------------------------------*/
|
||||
|
||||
/* Max amount of bytes in a single DMA operation is 4095,
|
||||
for SHA this means that the biggest safe amount of bytes is
|
||||
31 blocks of 128 bytes = 3968
|
||||
*/
|
||||
// #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
|
||||
// #define SOC_SHA_SUPPORT_DMA (1)
|
||||
|
||||
/* The SHA engine is able to resume hashing from a user */
|
||||
// #define SOC_SHA_SUPPORT_RESUME (1)
|
||||
|
||||
/* Has a centralized DMA, which is shared with all peripherals */
|
||||
// #define SOC_SHA_GDMA (1)
|
||||
|
||||
/* Supported HW algorithms */
|
||||
// #define SOC_SHA_SUPPORT_SHA1 (1)
|
||||
// #define SOC_SHA_SUPPORT_SHA224 (1)
|
||||
// #define SOC_SHA_SUPPORT_SHA256 (1)
|
||||
|
||||
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
|
||||
// #define SOC_SDM_GROUPS 1U
|
||||
// #define SOC_SDM_CHANNELS_PER_GROUP 4
|
||||
// #define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
|
||||
// #define SOC_SDM_CLK_SUPPORT_XTAL 1
|
||||
|
||||
/*-------------------------- SPI CAPS ----------------------------------------*/
|
||||
#define SOC_SPI_PERIPH_NUM 3
|
||||
#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3))
|
||||
#define SOC_SPI_MAX_CS_NUM 6
|
||||
|
||||
// #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
|
||||
|
||||
// #define SOC_SPI_SUPPORT_DDRCLK 1
|
||||
// #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
|
||||
// #define SOC_SPI_SUPPORT_CD_SIG 1
|
||||
// #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
|
||||
// #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
|
||||
// #define SOC_SPI_SUPPORT_CLK_XTAL 1
|
||||
// #define SOC_SPI_SUPPORT_CLK_PLL_F80M 1
|
||||
// #define SOC_SPI_SUPPORT_CLK_RC_FAST 1
|
||||
|
||||
// Peripheral supports DIO, DOUT, QIO, or QOUT
|
||||
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
|
||||
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
|
||||
|
||||
#define SOC_MEMSPI_IS_INDEPENDENT 1
|
||||
#define SOC_SPI_MAX_PRE_DIVIDER 16
|
||||
|
||||
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
|
||||
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_WRAP (1)
|
||||
|
||||
#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1
|
||||
#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1
|
||||
#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1
|
||||
|
||||
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
|
||||
#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
|
||||
#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
|
||||
#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part
|
||||
#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part
|
||||
#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5
|
||||
#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source
|
||||
#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
|
||||
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
|
||||
#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
|
||||
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
// #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
// #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
|
||||
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
|
||||
#define SOC_TIMER_GROUPS (2)
|
||||
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
|
||||
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
|
||||
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
|
||||
#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
|
||||
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
|
||||
// #define SOC_TIMER_SUPPORT_ETM (1)
|
||||
|
||||
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
|
||||
#define SOC_MWDT_SUPPORT_XTAL (1)
|
||||
|
||||
/*-------------------------- TWAI CAPS ---------------------------------------*/
|
||||
// #define SOC_TWAI_CONTROLLER_NUM 2
|
||||
// #define SOC_TWAI_CLK_SUPPORT_XTAL 1
|
||||
// #define SOC_TWAI_BRP_MIN 2
|
||||
// #define SOC_TWAI_BRP_MAX 32768
|
||||
// #define SOC_TWAI_SUPPORTS_RX_STATUS 1
|
||||
|
||||
/*-------------------------- eFuse CAPS----------------------------*/
|
||||
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 0
|
||||
#define SOC_EFUSE_DIS_PAD_JTAG 1
|
||||
#define SOC_EFUSE_DIS_USB_JTAG 1
|
||||
#define SOC_EFUSE_DIS_DIRECT_BOOT 1
|
||||
#define SOC_EFUSE_SOFT_DIS_JTAG 0
|
||||
#define SOC_EFUSE_DIS_ICACHE 0
|
||||
#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
|
||||
|
||||
/*-------------------------- Secure Boot CAPS----------------------------*/
|
||||
#define SOC_SECURE_BOOT_V2_RSA 1
|
||||
#define SOC_SECURE_BOOT_V2_ECC 1
|
||||
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
|
||||
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
|
||||
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
|
||||
|
||||
/*-------------------------- Flash Encryption CAPS----------------------------*/
|
||||
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
|
||||
|
||||
/*------------------------ Anti DPA (Security) CAPS --------------------------*/
|
||||
// #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
|
||||
|
||||
/*-------------------------- UART CAPS ---------------------------------------*/
|
||||
// ESP32-H4 has 3 UARTs (2 HP UART, and 1 LP UART) TODO: IDF-12445 [ESP32H4] inherit from verify code, need remove LP*/
|
||||
#define SOC_UART_NUM (3)
|
||||
#define SOC_UART_HP_NUM (2)
|
||||
#define SOC_UART_LP_NUM (1U)
|
||||
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
|
||||
#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */
|
||||
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
|
||||
#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */
|
||||
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
|
||||
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
|
||||
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
|
||||
|
||||
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
|
||||
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
|
||||
|
||||
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
|
||||
#define SOC_COEX_HW_PTI (1)
|
||||
|
||||
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
|
||||
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
|
||||
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
|
||||
|
||||
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
|
||||
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
|
||||
|
||||
// TODO: IDF-12286 (inherit from verify code, need check)
|
||||
/*-------------------------- Power Management CAPS ----------------------------*/
|
||||
#define SOC_PM_SUPPORT_BEACON_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
|
||||
#define SOC_PM_SUPPORT_TOUCH_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_CPU_PD (1)
|
||||
#define SOC_PM_SUPPORT_MODEM_PD (1)
|
||||
#define SOC_PM_SUPPORT_XTAL32K_PD (1)
|
||||
#define SOC_PM_SUPPORT_RC32K_PD (1)
|
||||
#define SOC_PM_SUPPORT_RC_FAST_PD (1)
|
||||
#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
|
||||
#define SOC_PM_SUPPORT_TOP_PD (1)
|
||||
#define SOC_PM_SUPPORT_HP_AON_PD (1)
|
||||
#define SOC_PM_SUPPORT_MAC_BB_PD (1)
|
||||
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
|
||||
|
||||
// #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1)
|
||||
// /* macro redefine for pass esp_wifi headers md5sum check */
|
||||
// #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
|
||||
|
||||
// #define SOC_PM_CPU_RETENTION_BY_SW (1)
|
||||
// #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
|
||||
// #define SOC_PM_RETENTION_HAS_CLOCK_BUG (1)
|
||||
|
||||
#define SOC_PM_PAU_LINK_NUM (4)
|
||||
|
||||
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
|
||||
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
|
||||
#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
|
||||
|
||||
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
|
||||
#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
|
||||
#define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */
|
||||
|
||||
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */
|
||||
|
||||
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
|
||||
// #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
|
||||
// #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)
|
||||
// #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1)
|
||||
|
||||
/*---------------------------------- Bluetooth CAPS ----------------------------------*/
|
||||
// #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */
|
||||
// #define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */
|
||||
// #define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */
|
||||
// #define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */
|
||||
// #define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */
|
||||
// #define SOC_BLE_POWER_CONTROL_SUPPORTED (1) /*!< Support Bluetooth Power Control */
|
||||
// #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED (1) /*!< Support For BLE Periodic Adv Enhancements */
|
||||
// #define SOC_BLUFI_SUPPORTED (1) /*!< Support BLUFI */
|
||||
// #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1) /*!< Support multiple connections optimization */
|
||||
16
components/soc/esp32h4/include/soc/soc_pins.h
Normal file
16
components/soc/esp32h4/include/soc/soc_pins.h
Normal file
@ -0,0 +1,16 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* Pin definition header file. The long term plan is to have a single soc_pins.h for all
|
||||
* peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
|
||||
* peripheral and include them here to avoid developing conflicts in those header files.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/gpio_pins.h"
|
||||
#include "soc/spi_pins.h"
|
||||
25
components/soc/esp32h4/include/soc/spi_pins.h
Normal file
25
components/soc/esp32h4/include/soc/spi_pins.h
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
// TODO: [ESP32H4] IDF-12388
|
||||
#define MSPI_FUNC_NUM 0
|
||||
#define MSPI_IOMUX_PIN_NUM_CS0 7
|
||||
#define MSPI_IOMUX_PIN_NUM_CS1 6
|
||||
#define MSPI_IOMUX_PIN_NUM_CLK 11
|
||||
#define MSPI_IOMUX_PIN_NUM_MOSI 12
|
||||
#define MSPI_IOMUX_PIN_NUM_MISO 8
|
||||
#define MSPI_IOMUX_PIN_NUM_WP 9
|
||||
#define MSPI_IOMUX_PIN_NUM_HD 10
|
||||
|
||||
#define SPI2_FUNC_NUM 2
|
||||
#define SPI2_IOMUX_PIN_NUM_MISO 15
|
||||
#define SPI2_IOMUX_PIN_NUM_HD 19
|
||||
#define SPI2_IOMUX_PIN_NUM_WP 18
|
||||
#define SPI2_IOMUX_PIN_NUM_CLK 16
|
||||
#define SPI2_IOMUX_PIN_NUM_MOSI 17
|
||||
#define SPI2_IOMUX_PIN_NUM_CS 20
|
||||
18
components/soc/esp32h4/include/soc/uart_channel.h
Normal file
18
components/soc/esp32h4/include/soc/uart_channel.h
Normal file
@ -0,0 +1,18 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C6.
|
||||
|
||||
#pragma once
|
||||
|
||||
//UART channels
|
||||
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 16
|
||||
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 17
|
||||
|
||||
#define UART_TXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
|
||||
#define UART_RXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
|
||||
46
components/soc/esp32h4/include/soc/uart_pins.h
Normal file
46
components/soc/esp32h4/include/soc/uart_pins.h
Normal file
@ -0,0 +1,46 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/io_mux_reg.h"
|
||||
|
||||
/* Specify the number of pins for UART */
|
||||
#define SOC_UART_PINS_COUNT (4)
|
||||
|
||||
/* Specify the GPIO pin number for each UART signal in the IOMUX */
|
||||
#define U0RXD_GPIO_NUM 23
|
||||
#define U0TXD_GPIO_NUM 24
|
||||
#define U0RTS_GPIO_NUM (-1)
|
||||
#define U0CTS_GPIO_NUM (-1)
|
||||
|
||||
#define U1RXD_GPIO_NUM (-1)
|
||||
#define U1TXD_GPIO_NUM (-1)
|
||||
#define U1RTS_GPIO_NUM (-1)
|
||||
#define U1CTS_GPIO_NUM (-1)
|
||||
|
||||
#define LP_U0RXD_GPIO_NUM 4
|
||||
#define LP_U0TXD_GPIO_NUM 5
|
||||
#define LP_U0RTS_GPIO_NUM 2
|
||||
#define LP_U0CTS_GPIO_NUM 3
|
||||
|
||||
/* The following defines are necessary for reconfiguring the UART
|
||||
* to use IOMUX, at runtime. */
|
||||
#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD)
|
||||
#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD)
|
||||
/* No func for the following pins, they shall not be used */
|
||||
#define U0RTS_MUX_FUNC (-1)
|
||||
#define U0CTS_MUX_FUNC (-1)
|
||||
/* Same goes for UART1 */
|
||||
#define U1TXD_MUX_FUNC (-1)
|
||||
#define U1RXD_MUX_FUNC (-1)
|
||||
#define U1RTS_MUX_FUNC (-1)
|
||||
#define U1CTS_MUX_FUNC (-1)
|
||||
|
||||
#define LP_U0TXD_MUX_FUNC (1)
|
||||
#define LP_U0RXD_MUX_FUNC (1)
|
||||
#define LP_U0RTS_MUX_FUNC (1)
|
||||
#define LP_U0CTS_MUX_FUNC (1)
|
||||
15
components/soc/esp32h4/include/soc/wdev_reg.h
Normal file
15
components/soc/esp32h4/include/soc/wdev_reg.h
Normal file
@ -0,0 +1,15 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
#include "soc/lpperi_reg.h"
|
||||
|
||||
// TODO: [ESP32H4] IDF-12265 inherit from verify code, need check
|
||||
|
||||
/* Hardware random number generator register */
|
||||
#define WDEV_RND_REG 0x600B0800
|
||||
130
components/soc/esp32h4/include/soc/xts_aes_reg.h
Normal file
130
components/soc/esp32h4/include/soc/xts_aes_reg.h
Normal file
@ -0,0 +1,130 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/spi1_mem_reg.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//TODO: [ESP32H4] IDF-12506 inherit from verify code, need check
|
||||
|
||||
#define XTS_AES_PLAIN_MEM(i) (REG_SPI_MEM_BASE(i) + 0x300)
|
||||
/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: This field is only used to generate include file in c case. This field is useles
|
||||
s. Please do not use this field..*/
|
||||
#define XTS_AES_PLAIN 0xFFFFFFFF
|
||||
#define XTS_AES_PLAIN_M ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S))
|
||||
#define XTS_AES_PLAIN_V 0xFFFFFFFF
|
||||
#define XTS_AES_PLAIN_S 0
|
||||
|
||||
#define XTS_AES_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340)
|
||||
/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: This bits stores the line-size parameter which will be used in manual encryption
|
||||
calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
|
||||
1: 32-bytes, 2: 64-bytes, 3:reserved..*/
|
||||
#define XTS_AES_LINESIZE 0x00000003
|
||||
#define XTS_AES_LINESIZE_M ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S))
|
||||
#define XTS_AES_LINESIZE_V 0x3
|
||||
#define XTS_AES_LINESIZE_S 0
|
||||
|
||||
#define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344)
|
||||
/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: This bit stores the destination parameter which will be used in manual encryption
|
||||
n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
|
||||
used..*/
|
||||
#define XTS_AES_DESTINATION (BIT(0))
|
||||
#define XTS_AES_DESTINATION_M (BIT(0))
|
||||
#define XTS_AES_DESTINATION_V 0x1
|
||||
#define XTS_AES_DESTINATION_S 0
|
||||
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348)
|
||||
/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
|
||||
/*description: This bits stores the physical-address parameter which will be used in manual enc
|
||||
ryption calculation. This value should aligned with byte number decided by line-
|
||||
size parameter..*/
|
||||
#define XTS_AES_PHYSICAL_ADDRESS 0x03FFFFFF
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_M ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S))
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_V 0x3FFFFFF
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_S 0
|
||||
|
||||
#define XTS_AES_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C)
|
||||
/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to trigger the process of manual encryption calculation. This actio
|
||||
n should only be asserted when manual encryption status is 0. After this action,
|
||||
manual encryption status becomes 1. After calculation is done, manual encryption
|
||||
n status becomes 2..*/
|
||||
#define XTS_AES_TRIGGER (BIT(0))
|
||||
#define XTS_AES_TRIGGER_M (BIT(0))
|
||||
#define XTS_AES_TRIGGER_V 0x1
|
||||
#define XTS_AES_TRIGGER_S 0
|
||||
|
||||
#define XTS_AES_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350)
|
||||
/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to release encrypted result to mspi. This action should only be ass
|
||||
erted when manual encryption status is 2. After this action, manual encryption s
|
||||
tatus will become 3..*/
|
||||
#define XTS_AES_RELEASE (BIT(0))
|
||||
#define XTS_AES_RELEASE_M (BIT(0))
|
||||
#define XTS_AES_RELEASE_V 0x1
|
||||
#define XTS_AES_RELEASE_S 0
|
||||
|
||||
#define XTS_AES_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354)
|
||||
/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
|
||||
en manual encryption status is 3. After this action, manual encryption status wi
|
||||
ll become 0..*/
|
||||
#define XTS_AES_DESTROY (BIT(0))
|
||||
#define XTS_AES_DESTROY_M (BIT(0))
|
||||
#define XTS_AES_DESTROY_V 0x1
|
||||
#define XTS_AES_DESTROY_S 0
|
||||
|
||||
#define XTS_AES_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358)
|
||||
/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
|
||||
calculation, 2: encryption calculation is done but the encrypted result is invi
|
||||
sible to mspi, 3: the encrypted result is visible to mspi..*/
|
||||
#define XTS_AES_STATE 0x00000003
|
||||
#define XTS_AES_STATE_M ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S))
|
||||
#define XTS_AES_STATE_V 0x3
|
||||
#define XTS_AES_STATE_S 0
|
||||
|
||||
#define XTS_AES_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C)
|
||||
/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
|
||||
/*description: This bits stores the last modified-time of manual encryption feature..*/
|
||||
#define XTS_AES_DATE 0x3FFFFFFF
|
||||
#define XTS_AES_DATE_M ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S))
|
||||
#define XTS_AES_DATE_V 0x3FFFFFFF
|
||||
|
||||
#define XTS_AES_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388)
|
||||
/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
|
||||
T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER (BIT(4))
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M (BIT(4))
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V 0x1
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S 4
|
||||
/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
|
||||
ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
|
||||
ing key 1..*/
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN (BIT(3))
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN_M (BIT(3))
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN_V 0x1
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN_S 3
|
||||
/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
|
||||
/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-
|
||||
7: The bigger the number is, the more secure the cryption is. (Note that the per
|
||||
formance of cryption will decrease together with this number increasing).*/
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL 0x00000007
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL_M ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S))
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL_V 0x7
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -14,7 +14,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_MONTR_ENA_REG register
|
||||
* core0 monitor enable configuration register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_MONTR_ENA_REG (DR_REG_BUS_BASE + 0x0)
|
||||
#define BUS_MONITOR_CORE_0_MONTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x0)
|
||||
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether to monitor read operations in region 0 by the Data bus.
|
||||
* 0: Not monitor
|
||||
@ -118,7 +118,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_INTR_RAW_REG register
|
||||
* core0 monitor interrupt status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_INTR_RAW_REG (DR_REG_BUS_BASE + 0x4)
|
||||
#define BUS_MONITOR_CORE_0_INTR_RAW_REG (DR_REG_BUS_MONITOR_BASE + 0x4)
|
||||
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status of read operations in region 0 by Data bus.
|
||||
*/
|
||||
@ -195,7 +195,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_INTR_ENA_REG register
|
||||
* core0 monitor interrupt enable register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_INTR_ENA_REG (DR_REG_BUS_BASE + 0x8)
|
||||
#define BUS_MONITOR_CORE_0_INTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x8)
|
||||
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Core0 dram0 area0 read monitor interrupt enable
|
||||
*/
|
||||
@ -270,7 +270,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_INTR_CLR_REG register
|
||||
* core0 monitor interrupt clear register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_INTR_CLR_REG (DR_REG_BUS_BASE + 0xc)
|
||||
#define BUS_MONITOR_CORE_0_INTR_CLR_REG (DR_REG_BUS_MONITOR_BASE + 0xc)
|
||||
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to clear the interrupt for read operations in region 0 by Data bus.
|
||||
*/
|
||||
@ -347,7 +347,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG register
|
||||
* Configures lower boundary address of region 0 monitored on Data bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_BUS_BASE + 0x10)
|
||||
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x10)
|
||||
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Configures the lower bound address of Data bus region 0.
|
||||
*/
|
||||
@ -359,7 +359,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG register
|
||||
* Configures upper boundary address of region 0 monitored on Data bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_BUS_BASE + 0x14)
|
||||
#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x14)
|
||||
/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the upper bound address of Data bus region 0.
|
||||
*/
|
||||
@ -371,7 +371,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG register
|
||||
* Configures lower boundary address of region 1 monitored on Data bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_BUS_BASE + 0x18)
|
||||
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x18)
|
||||
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Configures the lower bound address of Data bus region 1.
|
||||
*/
|
||||
@ -383,7 +383,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG register
|
||||
* Configures upper boundary address of region 1 monitored on Data bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_BUS_BASE + 0x1c)
|
||||
#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x1c)
|
||||
/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the upper bound address of Data bus region 1.
|
||||
*/
|
||||
@ -395,7 +395,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG register
|
||||
* Configures lower boundary address of region 0 monitored on Peripheral bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_BUS_BASE + 0x20)
|
||||
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x20)
|
||||
/** BUS_MONITOR_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Configures the lower bound address of Peripheral bus region 0.
|
||||
*/
|
||||
@ -407,7 +407,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG register
|
||||
* Configures upper boundary address of region 0 monitored on Peripheral bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_BUS_BASE + 0x24)
|
||||
#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x24)
|
||||
/** BUS_MONITOR_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the upper bound address of Peripheral bus region 0.
|
||||
*/
|
||||
@ -419,7 +419,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG register
|
||||
* Configures lower boundary address of region 1 monitored on Peripheral bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_BUS_BASE + 0x28)
|
||||
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x28)
|
||||
/** BUS_MONITOR_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Configures the lower bound address of Peripheral bus region 1.
|
||||
*/
|
||||
@ -431,7 +431,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG register
|
||||
* Configures upper boundary address of region 1 monitored on Peripheral bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_BUS_BASE + 0x2c)
|
||||
#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x2c)
|
||||
/** BUS_MONITOR_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the upper bound address of Peripheral bus region 1.
|
||||
*/
|
||||
@ -443,7 +443,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_AREA_PC_REG register
|
||||
* Region monitoring HP CPU PC status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_AREA_PC_REG (DR_REG_BUS_BASE + 0x30)
|
||||
#define BUS_MONITOR_CORE_0_AREA_PC_REG (DR_REG_BUS_MONITOR_BASE + 0x30)
|
||||
/** BUS_MONITOR_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the PC value when an interrupt is triggered during region monitoring.
|
||||
*/
|
||||
@ -455,7 +455,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_AREA_SP_REG register
|
||||
* Region monitoring HP CPU SP status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_AREA_SP_REG (DR_REG_BUS_BASE + 0x34)
|
||||
#define BUS_MONITOR_CORE_0_AREA_SP_REG (DR_REG_BUS_MONITOR_BASE + 0x34)
|
||||
/** BUS_MONITOR_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the SP value when an interrupt is triggered during region monitoring.
|
||||
*/
|
||||
@ -467,7 +467,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_SP_MIN_REG register
|
||||
* Configures stack monitoring lower boundary address
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_SP_MIN_REG (DR_REG_BUS_BASE + 0x38)
|
||||
#define BUS_MONITOR_CORE_0_SP_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x38)
|
||||
/** BUS_MONITOR_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the lower bound address of SP.
|
||||
*/
|
||||
@ -479,7 +479,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_SP_MAX_REG register
|
||||
* Configures stack monitoring upper boundary address
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_SP_MAX_REG (DR_REG_BUS_BASE + 0x3c)
|
||||
#define BUS_MONITOR_CORE_0_SP_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x3c)
|
||||
/** BUS_MONITOR_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Configures the upper bound address of SP.
|
||||
*/
|
||||
@ -491,7 +491,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_SP_PC_REG register
|
||||
* Stack monitoring HP CPU PC status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_SP_PC_REG (DR_REG_BUS_BASE + 0x40)
|
||||
#define BUS_MONITOR_CORE_0_SP_PC_REG (DR_REG_BUS_MONITOR_BASE + 0x40)
|
||||
/** BUS_MONITOR_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the PC value during stack monitoring.
|
||||
*/
|
||||
@ -503,7 +503,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_RCD_EN_REG register
|
||||
* HP CPU PC logging enable register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_RCD_EN_REG (DR_REG_BUS_BASE + 0x44)
|
||||
#define BUS_MONITOR_CORE_0_RCD_EN_REG (DR_REG_BUS_MONITOR_BASE + 0x44)
|
||||
/** BUS_MONITOR_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether to enable PC logging.
|
||||
* 0: Disable
|
||||
@ -526,7 +526,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG register
|
||||
* PC logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG (DR_REG_BUS_BASE + 0x48)
|
||||
#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG (DR_REG_BUS_MONITOR_BASE + 0x48)
|
||||
/** BUS_MONITOR_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the PC value at HP CPU reset.
|
||||
*/
|
||||
@ -538,7 +538,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG register
|
||||
* PC logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG (DR_REG_BUS_BASE + 0x4c)
|
||||
#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG (DR_REG_BUS_MONITOR_BASE + 0x4c)
|
||||
/** BUS_MONITOR_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents SP.
|
||||
*/
|
||||
@ -550,7 +550,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
|
||||
* cpu status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_BUS_BASE + 0x60)
|
||||
#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_BUS_MONITOR_BASE + 0x60)
|
||||
/** BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the PC of the last command before the HP CPU enters exception.
|
||||
*/
|
||||
@ -562,7 +562,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_DEBUG_MODE_REG register
|
||||
* cpu status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_DEBUG_MODE_REG (DR_REG_BUS_BASE + 0x64)
|
||||
#define BUS_MONITOR_CORE_0_DEBUG_MODE_REG (DR_REG_BUS_MONITOR_BASE + 0x64)
|
||||
/** BUS_MONITOR_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
|
||||
* Represents whether RISC-V CPU (HP CPU) is in debugging mode.
|
||||
* 1: In debugging mode
|
||||
@ -585,7 +585,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_CAUSE_0_REG register
|
||||
* TRACE lockup cause logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_CAUSE_0_REG (DR_REG_BUS_BASE + 0x68)
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_CAUSE_0_REG (DR_REG_BUS_MONITOR_BASE + 0x68)
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_0 : RO; bitpos: [5:0]; default: 0;
|
||||
* Represents the latest lockup cause
|
||||
*/
|
||||
@ -597,7 +597,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_TVAL_0_REG register
|
||||
* TRACE lockup tval logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_TVAL_0_REG (DR_REG_BUS_BASE + 0x6c)
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_TVAL_0_REG (DR_REG_BUS_MONITOR_BASE + 0x6c)
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the latest lockup tval
|
||||
*/
|
||||
@ -609,7 +609,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_IADDR_0_REG register
|
||||
* TRACE lockup iaddr logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_IADDR_0_REG (DR_REG_BUS_BASE + 0x70)
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_IADDR_0_REG (DR_REG_BUS_MONITOR_BASE + 0x70)
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the latest lockup iaddr
|
||||
*/
|
||||
@ -621,7 +621,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_PRIV_0_REG register
|
||||
* TRACE lockup priv logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_PRIV_0_REG (DR_REG_BUS_BASE + 0x74)
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_PRIV_0_REG (DR_REG_BUS_MONITOR_BASE + 0x74)
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_0 : RO; bitpos: [1:0]; default: 0;
|
||||
* Represents the latest lockup priv
|
||||
*/
|
||||
@ -633,7 +633,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_CAUSE_1_REG register
|
||||
* TRACE lockup cause logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_CAUSE_1_REG (DR_REG_BUS_BASE + 0x78)
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_CAUSE_1_REG (DR_REG_BUS_MONITOR_BASE + 0x78)
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_1 : RO; bitpos: [5:0]; default: 0;
|
||||
* Represents the last lockup cause
|
||||
*/
|
||||
@ -645,7 +645,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_TVAL_1_REG register
|
||||
* TRACE lockup tval logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_TVAL_1_REG (DR_REG_BUS_BASE + 0x7c)
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_TVAL_1_REG (DR_REG_BUS_MONITOR_BASE + 0x7c)
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the last lockup tval
|
||||
*/
|
||||
@ -657,7 +657,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_IADDR_1_REG register
|
||||
* TRACE lockup iaddr logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_IADDR_1_REG (DR_REG_BUS_BASE + 0x80)
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_IADDR_1_REG (DR_REG_BUS_MONITOR_BASE + 0x80)
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the last lockup iaddr
|
||||
*/
|
||||
@ -669,7 +669,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_PRIV_1_REG register
|
||||
* TRACE lockup priv logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_PRIV_1_REG (DR_REG_BUS_BASE + 0x84)
|
||||
#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_PRIV_1_REG (DR_REG_BUS_MONITOR_BASE + 0x84)
|
||||
/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_1 : RO; bitpos: [1:0]; default: 0;
|
||||
* Represents the last lockup priv
|
||||
*/
|
||||
@ -681,7 +681,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_MONTR_ENA_REG register
|
||||
* core1 monitor enable configuration register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_MONTR_ENA_REG (DR_REG_BUS_BASE + 0x88)
|
||||
#define BUS_MONITOR_CORE_1_MONTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x88)
|
||||
/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether to monitor read operations in region 0 by the Data bus.
|
||||
* 0: Not monitor
|
||||
@ -785,7 +785,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_INTR_RAW_REG register
|
||||
* core1 monitor interrupt status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_INTR_RAW_REG (DR_REG_BUS_BASE + 0x8c)
|
||||
#define BUS_MONITOR_CORE_1_INTR_RAW_REG (DR_REG_BUS_MONITOR_BASE + 0x8c)
|
||||
/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status of read operations in region 0 by Data bus.
|
||||
*/
|
||||
@ -862,7 +862,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_INTR_ENA_REG register
|
||||
* core1 monitor interrupt enable register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_INTR_ENA_REG (DR_REG_BUS_BASE + 0x90)
|
||||
#define BUS_MONITOR_CORE_1_INTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x90)
|
||||
/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Core1 dram0 area0 read monitor interrupt enable
|
||||
*/
|
||||
@ -937,7 +937,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_INTR_CLR_REG register
|
||||
* core1 monitor interrupt clear register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_INTR_CLR_REG (DR_REG_BUS_BASE + 0x94)
|
||||
#define BUS_MONITOR_CORE_1_INTR_CLR_REG (DR_REG_BUS_MONITOR_BASE + 0x94)
|
||||
/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to clear the interrupt for read operations in region 0 by Data bus.
|
||||
*/
|
||||
@ -1014,7 +1014,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN_REG register
|
||||
* Configures lower boundary address of region 0 monitored on Data bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN_REG (DR_REG_BUS_BASE + 0x98)
|
||||
#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x98)
|
||||
/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Configures the lower bound address of Data bus region 0.
|
||||
*/
|
||||
@ -1026,7 +1026,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX_REG register
|
||||
* Configures upper boundary address of region 0 monitored on Data bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX_REG (DR_REG_BUS_BASE + 0x9c)
|
||||
#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x9c)
|
||||
/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the upper bound address of Data bus region 0.
|
||||
*/
|
||||
@ -1038,7 +1038,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN_REG register
|
||||
* Configures lower boundary address of region 1 monitored on Data bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN_REG (DR_REG_BUS_BASE + 0xa0)
|
||||
#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0xa0)
|
||||
/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Configures the lower bound address of Data bus region 1.
|
||||
*/
|
||||
@ -1050,7 +1050,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX_REG register
|
||||
* Configures upper boundary address of region 1 monitored on Data bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX_REG (DR_REG_BUS_BASE + 0xa4)
|
||||
#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0xa4)
|
||||
/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the upper bound address of Data bus region 1.
|
||||
*/
|
||||
@ -1062,7 +1062,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_AREA_PIF_0_MIN_REG register
|
||||
* Configures lower boundary address of region 0 monitored on Peripheral bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_AREA_PIF_0_MIN_REG (DR_REG_BUS_BASE + 0xa8)
|
||||
#define BUS_MONITOR_CORE_1_AREA_PIF_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0xa8)
|
||||
/** BUS_MONITOR_CORE_1_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Configures the lower bound address of Peripheral bus region 0.
|
||||
*/
|
||||
@ -1074,7 +1074,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_AREA_PIF_0_MAX_REG register
|
||||
* Configures upper boundary address of region 0 monitored on Peripheral bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_AREA_PIF_0_MAX_REG (DR_REG_BUS_BASE + 0xac)
|
||||
#define BUS_MONITOR_CORE_1_AREA_PIF_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0xac)
|
||||
/** BUS_MONITOR_CORE_1_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the upper bound address of Peripheral bus region 0.
|
||||
*/
|
||||
@ -1086,7 +1086,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_AREA_PIF_1_MIN_REG register
|
||||
* Configures lower boundary address of region 1 monitored on Peripheral bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_AREA_PIF_1_MIN_REG (DR_REG_BUS_BASE + 0xb0)
|
||||
#define BUS_MONITOR_CORE_1_AREA_PIF_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0xb0)
|
||||
/** BUS_MONITOR_CORE_1_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Configures the lower bound address of Peripheral bus region 1.
|
||||
*/
|
||||
@ -1098,7 +1098,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_AREA_PIF_1_MAX_REG register
|
||||
* Configures upper boundary address of region 1 monitored on Peripheral bus
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_AREA_PIF_1_MAX_REG (DR_REG_BUS_BASE + 0xb4)
|
||||
#define BUS_MONITOR_CORE_1_AREA_PIF_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0xb4)
|
||||
/** BUS_MONITOR_CORE_1_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the upper bound address of Peripheral bus region 1.
|
||||
*/
|
||||
@ -1110,7 +1110,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_AREA_PC_REG register
|
||||
* Region monitoring HP CPU PC status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_AREA_PC_REG (DR_REG_BUS_BASE + 0xb8)
|
||||
#define BUS_MONITOR_CORE_1_AREA_PC_REG (DR_REG_BUS_MONITOR_BASE + 0xb8)
|
||||
/** BUS_MONITOR_CORE_1_AREA_PC : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the PC value when an interrupt is triggered during region monitoring.
|
||||
*/
|
||||
@ -1122,7 +1122,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_AREA_SP_REG register
|
||||
* Region monitoring HP CPU SP status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_AREA_SP_REG (DR_REG_BUS_BASE + 0xbc)
|
||||
#define BUS_MONITOR_CORE_1_AREA_SP_REG (DR_REG_BUS_MONITOR_BASE + 0xbc)
|
||||
/** BUS_MONITOR_CORE_1_AREA_SP : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the SP value when an interrupt is triggered during region monitoring.
|
||||
*/
|
||||
@ -1134,7 +1134,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_SP_MIN_REG register
|
||||
* Configures stack monitoring lower boundary address
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_SP_MIN_REG (DR_REG_BUS_BASE + 0xc0)
|
||||
#define BUS_MONITOR_CORE_1_SP_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0xc0)
|
||||
/** BUS_MONITOR_CORE_1_SP_MIN : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the lower bound address of SP.
|
||||
*/
|
||||
@ -1146,7 +1146,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_SP_MAX_REG register
|
||||
* Configures stack monitoring upper boundary address
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_SP_MAX_REG (DR_REG_BUS_BASE + 0xc4)
|
||||
#define BUS_MONITOR_CORE_1_SP_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0xc4)
|
||||
/** BUS_MONITOR_CORE_1_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* Configures the upper bound address of SP.
|
||||
*/
|
||||
@ -1158,7 +1158,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_SP_PC_REG register
|
||||
* Stack monitoring HP CPU PC status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_SP_PC_REG (DR_REG_BUS_BASE + 0xc8)
|
||||
#define BUS_MONITOR_CORE_1_SP_PC_REG (DR_REG_BUS_MONITOR_BASE + 0xc8)
|
||||
/** BUS_MONITOR_CORE_1_SP_PC : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the PC value during stack monitoring.
|
||||
*/
|
||||
@ -1170,7 +1170,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_RCD_EN_REG register
|
||||
* HP CPU PC logging enable register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_RCD_EN_REG (DR_REG_BUS_BASE + 0xcc)
|
||||
#define BUS_MONITOR_CORE_1_RCD_EN_REG (DR_REG_BUS_MONITOR_BASE + 0xcc)
|
||||
/** BUS_MONITOR_CORE_1_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether to enable PC logging.
|
||||
* 0: Disable
|
||||
@ -1193,7 +1193,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_RCD_PDEBUGPC_REG register
|
||||
* PC logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_RCD_PDEBUGPC_REG (DR_REG_BUS_BASE + 0xd0)
|
||||
#define BUS_MONITOR_CORE_1_RCD_PDEBUGPC_REG (DR_REG_BUS_MONITOR_BASE + 0xd0)
|
||||
/** BUS_MONITOR_CORE_1_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the PC value at HP CPU reset.
|
||||
*/
|
||||
@ -1205,7 +1205,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_RCD_PDEBUGSP_REG register
|
||||
* PC logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_RCD_PDEBUGSP_REG (DR_REG_BUS_BASE + 0xd4)
|
||||
#define BUS_MONITOR_CORE_1_RCD_PDEBUGSP_REG (DR_REG_BUS_MONITOR_BASE + 0xd4)
|
||||
/** BUS_MONITOR_CORE_1_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents SP.
|
||||
*/
|
||||
@ -1217,7 +1217,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXCEPTION_REG register
|
||||
* cpu status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_BUS_BASE + 0xe8)
|
||||
#define BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_BUS_MONITOR_BASE + 0xe8)
|
||||
/** BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the PC of the last command before the HP CPU enters exception.
|
||||
*/
|
||||
@ -1229,7 +1229,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_DEBUG_MODE_REG register
|
||||
* cpu status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_DEBUG_MODE_REG (DR_REG_BUS_BASE + 0xec)
|
||||
#define BUS_MONITOR_CORE_1_DEBUG_MODE_REG (DR_REG_BUS_MONITOR_BASE + 0xec)
|
||||
/** BUS_MONITOR_CORE_1_DEBUG_MODE : RO; bitpos: [0]; default: 0;
|
||||
* Represents whether RISC-V CPU (HP CPU) is in debugging mode.
|
||||
* 1: In debugging mode
|
||||
@ -1252,7 +1252,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_CAUSE_0_REG register
|
||||
* TRACE lockup cause logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_CAUSE_0_REG (DR_REG_BUS_BASE + 0xf0)
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_CAUSE_0_REG (DR_REG_BUS_MONITOR_BASE + 0xf0)
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_0 : RO; bitpos: [5:0]; default: 0;
|
||||
* Represents the latest lockup cause
|
||||
*/
|
||||
@ -1264,7 +1264,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_TVAL_0_REG register
|
||||
* TRACE lockup tval logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_TVAL_0_REG (DR_REG_BUS_BASE + 0xf4)
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_TVAL_0_REG (DR_REG_BUS_MONITOR_BASE + 0xf4)
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the latest lockup tval
|
||||
*/
|
||||
@ -1276,7 +1276,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_IADDR_0_REG register
|
||||
* TRACE lockup iaddr logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_IADDR_0_REG (DR_REG_BUS_BASE + 0xf8)
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_IADDR_0_REG (DR_REG_BUS_MONITOR_BASE + 0xf8)
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the latest lockup iaddr
|
||||
*/
|
||||
@ -1288,7 +1288,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_PRIV_0_REG register
|
||||
* TRACE lockup priv logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_PRIV_0_REG (DR_REG_BUS_BASE + 0xfc)
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_PRIV_0_REG (DR_REG_BUS_MONITOR_BASE + 0xfc)
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_0 : RO; bitpos: [1:0]; default: 0;
|
||||
* Represents the latest lockup priv
|
||||
*/
|
||||
@ -1300,7 +1300,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_CAUSE_1_REG register
|
||||
* TRACE lockup cause logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_CAUSE_1_REG (DR_REG_BUS_BASE + 0x100)
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_CAUSE_1_REG (DR_REG_BUS_MONITOR_BASE + 0x100)
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_1 : RO; bitpos: [5:0]; default: 0;
|
||||
* Represents the last lockup cause
|
||||
*/
|
||||
@ -1312,7 +1312,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_TVAL_1_REG register
|
||||
* TRACE lockup tval logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_TVAL_1_REG (DR_REG_BUS_BASE + 0x104)
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_TVAL_1_REG (DR_REG_BUS_MONITOR_BASE + 0x104)
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the last lockup tval
|
||||
*/
|
||||
@ -1324,7 +1324,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_IADDR_1_REG register
|
||||
* TRACE lockup iaddr logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_IADDR_1_REG (DR_REG_BUS_BASE + 0x108)
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_IADDR_1_REG (DR_REG_BUS_MONITOR_BASE + 0x108)
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the last lockup iaddr
|
||||
*/
|
||||
@ -1336,7 +1336,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_PRIV_1_REG register
|
||||
* TRACE lockup priv logging register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_PRIV_1_REG (DR_REG_BUS_BASE + 0x10c)
|
||||
#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_PRIV_1_REG (DR_REG_BUS_MONITOR_BASE + 0x10c)
|
||||
/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_1 : RO; bitpos: [1:0]; default: 0;
|
||||
* Represents the last lockup priv
|
||||
*/
|
||||
@ -1348,7 +1348,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
|
||||
* exception monitor status register
|
||||
*/
|
||||
#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_BUS_BASE + 0x110)
|
||||
#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_BUS_MONITOR_BASE + 0x110)
|
||||
/** BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
|
||||
* reg_core_x_iram0_dram0_limit_cycle_0
|
||||
*/
|
||||
@ -1360,7 +1360,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_CLOCK_GATE_REG register
|
||||
* Register clock control
|
||||
*/
|
||||
#define BUS_MONITOR_CLOCK_GATE_REG (DR_REG_BUS_BASE + 0x114)
|
||||
#define BUS_MONITOR_CLOCK_GATE_REG (DR_REG_BUS_MONITOR_BASE + 0x114)
|
||||
/** BUS_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
|
||||
* Configures whether to enable the register clock gating.
|
||||
* 0: Disable
|
||||
@ -1374,7 +1374,7 @@ extern "C" {
|
||||
/** BUS_MONITOR_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define BUS_MONITOR_DATE_REG (DR_REG_BUS_BASE + 0x3fc)
|
||||
#define BUS_MONITOR_DATE_REG (DR_REG_BUS_MONITOR_BASE + 0x3fc)
|
||||
/** BUS_MONITOR_DATE : R/W; bitpos: [27:0]; default: 34640176;
|
||||
* version register
|
||||
*/
|
||||
@ -1319,12 +1319,12 @@ typedef struct {
|
||||
volatile bus_monitor_clock_gate_reg_t monitor_clock_gate;
|
||||
uint32_t reserved_118[185];
|
||||
volatile bus_monitor_date_reg_t monitor_date;
|
||||
} bus_dev_t;
|
||||
} bus_monitor_dev_t;
|
||||
|
||||
extern bus_dev_t ASSIST_DEBUG;
|
||||
extern bus_monitor_dev_t BUS_MONITOR;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(bus_dev_t) == 0x400, "Invalid size of bus_dev_t structure");
|
||||
_Static_assert(sizeof(bus_monitor_dev_t) == 0x400, "Invalid size of bus_monitor_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
@ -14,7 +14,7 @@ extern "C" {
|
||||
/** MEM_MONITOR_LOG_SETTING_REG register
|
||||
* Bus access logging configuration register
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_BASE + 0x0)
|
||||
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
|
||||
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
|
||||
* Configures monitoring modes.bit[0]: Configures write monitoring.
|
||||
* 0: Disable
|
||||
@ -78,7 +78,7 @@ extern "C" {
|
||||
/** MEM_MONITOR_LOG_SETTING1_REG register
|
||||
* Bus access logging configuration register
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_BASE + 0x4)
|
||||
#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
|
||||
/** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0;
|
||||
* Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_2 bus access logging.
|
||||
@ -105,7 +105,7 @@ extern "C" {
|
||||
/** MEM_MONITOR_LOG_CHECK_DATA_REG register
|
||||
* Configures monitored data in Bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_BASE + 0x8)
|
||||
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
|
||||
/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the data to be monitored during bus accessing.
|
||||
*/
|
||||
@ -117,7 +117,7 @@ extern "C" {
|
||||
/** MEM_MONITOR_LOG_DATA_MASK_REG register
|
||||
* Configures masked data in Bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_BASE + 0xc)
|
||||
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
|
||||
/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
|
||||
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]:
|
||||
* Configures whether to mask the least significant byte of
|
||||
@ -145,7 +145,7 @@ extern "C" {
|
||||
/** MEM_MONITOR_LOG_MIN_REG register
|
||||
* Configures monitored address space in Bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_BASE + 0x10)
|
||||
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
|
||||
/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the lower bound address of the monitored address space.
|
||||
*/
|
||||
@ -157,7 +157,7 @@ extern "C" {
|
||||
/** MEM_MONITOR_LOG_MAX_REG register
|
||||
* Configures monitored address space in Bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_BASE + 0x14)
|
||||
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
|
||||
/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the upper bound address of the monitored address space.
|
||||
*/
|
||||
@ -170,7 +170,7 @@ extern "C" {
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG (DR_REG_MEM_BASE + 0x18)
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
@ -196,7 +196,7 @@ extern "C" {
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG (DR_REG_MEM_BASE + 0x1c)
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
@ -245,7 +245,7 @@ extern "C" {
|
||||
/** MEM_MONITOR_LOG_MEM_START_REG register
|
||||
* Configures the starting address of the storage memory for recorded data
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_BASE + 0x20)
|
||||
#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
|
||||
/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the starting address of the storage space for recorded data.
|
||||
*/
|
||||
@ -257,7 +257,7 @@ extern "C" {
|
||||
/** MEM_MONITOR_LOG_MEM_END_REG register
|
||||
* Configures the end address of the storage memory for recorded data
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_BASE + 0x24)
|
||||
#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
|
||||
/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the ending address of the storage space for recorded data.
|
||||
*/
|
||||
@ -269,7 +269,7 @@ extern "C" {
|
||||
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
|
||||
* Represents the address for the next write
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_BASE + 0x28)
|
||||
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
|
||||
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the address of the next write.
|
||||
*/
|
||||
@ -282,7 +282,7 @@ extern "C" {
|
||||
* Updates the address for the next write with the starting address for the recorded
|
||||
* data
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_BASE + 0x2c)
|
||||
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c)
|
||||
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to
|
||||
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update
|
||||
@ -296,7 +296,7 @@ extern "C" {
|
||||
/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
|
||||
* Logging overflow status register
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_BASE + 0x30)
|
||||
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x30)
|
||||
/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
|
||||
* Represents whether data overflows the storage space.0: Not Overflow
|
||||
* 1: Overflow
|
||||
@ -317,7 +317,7 @@ extern "C" {
|
||||
/** MEM_MONITOR_CLOCK_GATE_REG register
|
||||
* Register clock control
|
||||
*/
|
||||
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_BASE + 0x34)
|
||||
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x34)
|
||||
/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether to enable the register clock gating.0: Disable
|
||||
* 1: Enable
|
||||
@ -330,7 +330,7 @@ extern "C" {
|
||||
/** MEM_MONITOR_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define MEM_MONITOR_DATE_REG (DR_REG_MEM_BASE + 0x3fc)
|
||||
#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
|
||||
/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 36733248;
|
||||
* Version control register.
|
||||
*/
|
||||
|
||||
@ -354,12 +354,12 @@ typedef struct {
|
||||
volatile mem_monitor_clock_gate_reg_t monitor_clock_gate;
|
||||
uint32_t reserved_038[241];
|
||||
volatile mem_monitor_date_reg_t monitor_date;
|
||||
} mem_dev_t;
|
||||
} mem_monitor_dev_t;
|
||||
|
||||
extern mem_dev_t MEM_MONITOR;
|
||||
extern mem_monitor_dev_t MEM_MONITOR;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(mem_dev_t) == 0x400, "Invalid size of mem_dev_t structure");
|
||||
_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -11,6 +11,8 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DR_REG_RNG_BASE DR_REG_TRNG_BASE
|
||||
|
||||
/** RNG_DATA_REG register
|
||||
* RNG result register
|
||||
*/
|
||||
|
||||
@ -11,6 +11,8 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000)
|
||||
|
||||
/** SPI_MEM_CMD_REG register
|
||||
* SPI1 memory command register
|
||||
*/
|
||||
|
||||
@ -104,3 +104,7 @@ tools/test_apps/system/unicore_bootloader:
|
||||
enable:
|
||||
- if: SOC_CPU_CORES_NUM > 1
|
||||
reason: the test should be run on multicore chips
|
||||
disable:
|
||||
- if: IDF_TARGET in ["esp32h4"]
|
||||
temporary: true
|
||||
reason: not supported yet # TODO: [ESP32H4] IDF-12300
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user