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feat(gpio): fix the fspics0 in io mux reg
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@ -205,7 +205,6 @@ extern "C" {
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#define FUNC_GPIO7_GPIO7_0 0
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#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x20)
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#define FUNC_GPIO8_FSPICS0 2
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#define FUNC_GPIO8_GPIO8 1
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#define FUNC_GPIO8_GPIO8_0 0
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@ -214,6 +213,7 @@ extern "C" {
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#define FUNC_GPIO9_GPIO9_0 0
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#define PERIPHS_IO_MUX_U_PAD_GPIO10 (REG_IO_MUX_BASE + 0x28)
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#define FUNC_GPIO10_FSPICS0 2
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#define FUNC_GPIO10_GPIO10 1
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#define FUNC_GPIO10_GPIO10_0 0
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