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fix(rtc): fixed bbpll not calibrated from bootloader issue

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This commit is contained in:
Xiao Xufeng 2023-11-07 16:16:23 +08:00
parent d91c6d0da8
commit 376be14e1c
4 changed files with 55 additions and 1 deletions
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18
components/esp_hw_support/port/esp32c2/rtc_clk.c
View File

@ -351,6 +351,24 @@ bool rtc_dig_8m_enabled(void)
return clk_ll_rc_fast_digi_is_enabled();
}
// Workaround for bootloader not calibrated well issue.
// Placed in IRAM because disabling BBPLL may influence the cache
void rtc_clk_recalib_bbpll(void)
{
rtc_cpu_freq_config_t old_config;
rtc_clk_cpu_freq_get_config(&old_config);
// There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
// - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
// Turn off the BBPLL and do calibration again to fix the issue.
// - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
// requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
if (old_config.source == SOC_CPU_CLK_SRC_PLL) {
rtc_clk_cpu_freq_set_xtal();
rtc_clk_cpu_freq_set_config(&old_config);
}
}
/* Name used in libphy.a:phy_chip_v7.o
* TODO: update the library to use rtc_clk_xtal_freq_get
*/

19
components/esp_hw_support/port/esp32s3/rtc_clk.c
View File

@ -459,6 +459,25 @@ static bool rtc_clk_set_bbpll_always_on(void)
return is_bbpll_on;
}
// Workaround for bootloader not calibrated well issue.
// Placed in IRAM because disabling BBPLL may influence the cache
void rtc_clk_recalib_bbpll(void)
{
rtc_cpu_freq_config_t old_config;
rtc_clk_cpu_freq_get_config(&old_config);
// There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
// - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
// Turn off the BBPLL and do calibration again to fix the issue.
// - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
// requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
if (old_config.source == SOC_CPU_CLK_SRC_PLL) {
rtc_clk_cpu_freq_set_xtal();
rtc_clk_cpu_freq_set_config(&old_config);
}
}
/* Name used in libphy.a:phy_chip_v7.o
* TODO: update the library to use rtc_clk_xtal_freq_get
*/

9
components/esp_system/Kconfig
View File

@ -543,6 +543,15 @@ menu "ESP System Settings"
(2). For special workflow, the chip needs do more things instead of restarting directly. This part
needs to be done in callback function of interrupt.
config ESP_SYSTEM_BBPLL_RECALIB
bool "Re-calibration BBPLL at startup"
depends on IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3
default y
help
This configuration helps to address an BBPLL inaccurate issue when boot from certain bootloader version,
which may increase about the boot-up time by about 200 us. Disable this when your bootloader is built with
ESP-IDF version v5.2 and above.
endmenu # ESP System Settings
menu "IPC (Inter-Processor Call)"

10
components/esp_system/port/cpu_start.c
View File

@ -428,8 +428,16 @@ void IRAM_ATTR call_start_cpu0(void)
* In this stage, we re-configure the Flash (and MSPI) to required configuration
*/
spi_flash_init_chip_state();
// In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough.
// Do calibration again here so that we can use better clock for the timing tuning.
#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB
extern void rtc_clk_recalib_bbpll(void);
rtc_clk_recalib_bbpll();
#endif
#if CONFIG_IDF_TARGET_ESP32S3
//On other chips, this feature is not provided by HW, or hasn't been tested yet.
// This function needs to be called when PLL is enabled
// On other chips, this feature is not provided by HW, or hasn't been tested yet.
spi_timing_flash_tuning();
#endif