diff --git a/components/efuse/esp32c61/esp_efuse_table.c b/components/efuse/esp32c61/esp_efuse_table.c index 07784d930e..4ff8c7c62f 100644 --- a/components/efuse/esp32c61/esp_efuse_table.c +++ b/components/efuse/esp32c61/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 52aee23d9256003919a3d01945678355 +// md5_digest_table af9aaa79feb0970d90f35360a5113f03 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -235,6 +235,62 @@ static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, }; +static const esp_efuse_desc_t WR_DIS_TEMPERATURE_SENSOR[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMPERATURE_SENSOR, +}; + +static const esp_efuse_desc_t WR_DIS_OCODE[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF, +}; + static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA, }; @@ -528,6 +584,62 @@ static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, }; +static const esp_efuse_desc_t TEMPERATURE_SENSOR[] = { + {EFUSE_BLK2, 128, 9}, // [] Temperature calibration data, +}; + +static const esp_efuse_desc_t OCODE[] = { + {EFUSE_BLK2, 137, 8}, // [] ADC OCode calibration, +}; + +static const esp_efuse_desc_t ADC1_AVE_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK2, 145, 10}, // [] Average initcode of ADC1 atten0, +}; + +static const esp_efuse_desc_t ADC1_AVE_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK2, 155, 10}, // [] Average initcode of ADC1 atten1, +}; + +static const esp_efuse_desc_t ADC1_AVE_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK2, 165, 10}, // [] Average initcode of ADC1 atten2, +}; + +static const esp_efuse_desc_t ADC1_AVE_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK2, 175, 10}, // [] Average initcode of ADC1 atten3, +}; + +static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = { + {EFUSE_BLK2, 185, 10}, // [] HI_DOUT of ADC1 atten0, +}; + +static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = { + {EFUSE_BLK2, 195, 10}, // [] HI_DOUT of ADC1 atten1, +}; + +static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = { + {EFUSE_BLK2, 205, 10}, // [] HI_DOUT of ADC1 atten2, +}; + +static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = { + {EFUSE_BLK2, 215, 10}, // [] HI_DOUT of ADC1 atten3, +}; + +static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK2, 225, 4}, // [] Gap between ADC1 CH0 and average initcode, +}; + +static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK2, 229, 4}, // [] Gap between ADC1 CH1 and average initcode, +}; + +static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK2, 233, 4}, // [] Gap between ADC1 CH2 and average initcode, +}; + +static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK2, 237, 4}, // [] Gap between ADC1 CH3 and average initcode, +}; + static const esp_efuse_desc_t USER_DATA[] = { {EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data, }; @@ -843,6 +955,76 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[] = { + &WR_DIS_TEMPERATURE_SENSOR[0], // [] wr_dis of TEMPERATURE_SENSOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = { + &WR_DIS_OCODE[0], // [] wr_dis of OCODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN0[] = { + &WR_DIS_ADC1_AVE_INIT_CODE_ATTEN0[0], // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN1[] = { + &WR_DIS_ADC1_AVE_INIT_CODE_ATTEN1[0], // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN2[] = { + &WR_DIS_ADC1_AVE_INIT_CODE_ATTEN2[0], // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN3[] = { + &WR_DIS_ADC1_AVE_INIT_CODE_ATTEN3[0], // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = { + &WR_DIS_ADC1_HI_DOUT_ATTEN0[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = { + &WR_DIS_ADC1_HI_DOUT_ATTEN1[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = { + &WR_DIS_ADC1_HI_DOUT_ATTEN2[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = { + &WR_DIS_ADC1_HI_DOUT_ATTEN3[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { + &WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { + &WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { + &WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { + &WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = { &WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA NULL @@ -1208,6 +1390,76 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[] = { + &TEMPERATURE_SENSOR[0], // [] Temperature calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { + &OCODE[0], // [] ADC OCode calibration + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN0[] = { + &ADC1_AVE_INIT_CODE_ATTEN0[0], // [] Average initcode of ADC1 atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN1[] = { + &ADC1_AVE_INIT_CODE_ATTEN1[0], // [] Average initcode of ADC1 atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN2[] = { + &ADC1_AVE_INIT_CODE_ATTEN2[0], // [] Average initcode of ADC1 atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN3[] = { + &ADC1_AVE_INIT_CODE_ATTEN3[0], // [] Average initcode of ADC1 atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = { + &ADC1_HI_DOUT_ATTEN0[0], // [] HI_DOUT of ADC1 atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = { + &ADC1_HI_DOUT_ATTEN1[0], // [] HI_DOUT of ADC1 atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = { + &ADC1_HI_DOUT_ATTEN2[0], // [] HI_DOUT of ADC1 atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = { + &ADC1_HI_DOUT_ATTEN3[0], // [] HI_DOUT of ADC1 atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { + &ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH0 and average initcode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { + &ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH1 and average initcode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { + &ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH2 and average initcode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { + &ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH3 and average initcode + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { &USER_DATA[0], // [BLOCK_USR_DATA] User data NULL diff --git a/components/efuse/esp32c61/esp_efuse_table.csv b/components/efuse/esp32c61/esp_efuse_table.csv index 271c86df89..2a82ff95b5 100644 --- a/components/efuse/esp32c61/esp_efuse_table.csv +++ b/components/efuse/esp32c61/esp_efuse_table.csv @@ -9,7 +9,7 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# This file was generated by regtools.py based on the efuses.yaml file with the version: e564f8042b56a475a7714bb28ecdadfa +# This file was generated by regtools.py based on the efuses.yaml file with the version: 8f05ff9d292b10d2360200fae1d15e8d WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS @@ -66,6 +66,20 @@ WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID +WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 21, 1, [] wr_dis of TEMPERATURE_SENSOR +WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE +WR_DIS.ADC1_AVE_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN0 +WR_DIS.ADC1_AVE_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN1 +WR_DIS.ADC1_AVE_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN2 +WR_DIS.ADC1_AVE_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN3 +WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0 +WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1 +WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2 +WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3 +WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF +WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF +WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF +WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 @@ -143,6 +157,20 @@ PSRAM_VENDOR, EFUSE_BLK1, 86, 2, [] PSRAM TEMP, EFUSE_BLK1, 88, 2, [] Temperature PKG_VERSION, EFUSE_BLK1, 90, 3, [] Package version OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID +TEMPERATURE_SENSOR, EFUSE_BLK2, 128, 9, [] Temperature calibration data +OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode calibration +ADC1_AVE_INIT_CODE_ATTEN0, EFUSE_BLK2, 145, 10, [] Average initcode of ADC1 atten0 +ADC1_AVE_INIT_CODE_ATTEN1, EFUSE_BLK2, 155, 10, [] Average initcode of ADC1 atten1 +ADC1_AVE_INIT_CODE_ATTEN2, EFUSE_BLK2, 165, 10, [] Average initcode of ADC1 atten2 +ADC1_AVE_INIT_CODE_ATTEN3, EFUSE_BLK2, 175, 10, [] Average initcode of ADC1 atten3 +ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 185, 10, [] HI_DOUT of ADC1 atten0 +ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 195, 10, [] HI_DOUT of ADC1 atten1 +ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 205, 10, [] HI_DOUT of ADC1 atten2 +ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 215, 10, [] HI_DOUT of ADC1 atten3 +ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 225, 4, [] Gap between ADC1 CH0 and average initcode +ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 229, 4, [] Gap between ADC1 CH1 and average initcode +ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 233, 4, [] Gap between ADC1 CH2 and average initcode +ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 237, 4, [] Gap between ADC1 CH3 and average initcode USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data diff --git a/components/efuse/esp32c61/include/esp_efuse_table.h b/components/efuse/esp32c61/include/esp_efuse_table.h index 085c9223e2..40844a0581 100644 --- a/components/efuse/esp32c61/include/esp_efuse_table.h +++ b/components/efuse/esp32c61/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 52aee23d9256003919a3d01945678355 +// md5_digest_table af9aaa79feb0970d90f35360a5113f03 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -79,6 +79,20 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; @@ -175,6 +189,20 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; diff --git a/components/soc/esp32c61/register/soc/efuse_reg.h b/components/soc/esp32c61/register/soc/efuse_reg.h index c1eac845a8..fa1866d023 100644 --- a/components/soc/esp32c61/register/soc/efuse_reg.h +++ b/components/soc/esp32c61/register/soc/efuse_reg.h @@ -557,13 +557,13 @@ extern "C" { #define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) #define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 -/** EFUSE_C61_NO_EXTENTION : R; bitpos: [31:16]; default: 0; - * Reserved +/** EFUSE_RD_RESERVE_1_48 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ -#define EFUSE_C61_NO_EXTENTION 0x0000FFFFU -#define EFUSE_C61_NO_EXTENTION_M (EFUSE_C61_NO_EXTENTION_V << EFUSE_C61_NO_EXTENTION_S) -#define EFUSE_C61_NO_EXTENTION_V 0x0000FFFFU -#define EFUSE_C61_NO_EXTENTION_S 16 +#define EFUSE_RD_RESERVE_1_48 0x0000FFFFU +#define EFUSE_RD_RESERVE_1_48_M (EFUSE_RD_RESERVE_1_48_V << EFUSE_RD_RESERVE_1_48_S) +#define EFUSE_RD_RESERVE_1_48_V 0x0000FFFFU +#define EFUSE_RD_RESERVE_1_48_S 16 /** EFUSE_RD_MAC_SYS2_REG register * Represents rd_mac_sys @@ -756,49 +756,147 @@ extern "C" { * Represents rd_sys_part1_data4 */ #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE0_BASE + 0x6c) -/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0; + * Temperature calibration data */ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_S 0 +#define EFUSE_TEMPERATURE_SENSOR 0x000001FFU +#define EFUSE_TEMPERATURE_SENSOR_M (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S) +#define EFUSE_TEMPERATURE_SENSOR_V 0x000001FFU +#define EFUSE_TEMPERATURE_SENSOR_S 0 +/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0; + * ADC OCode calibration + */ +#define EFUSE_OCODE 0x000000FFU +#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) +#define EFUSE_OCODE_V 0x000000FFU +#define EFUSE_OCODE_S 9 +/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN0 : R; bitpos: [26:17]; default: 0; + * Average initcode of ADC1 atten0 + */ +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0 0x000003FFU +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_S) +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_V 0x000003FFU +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_S 17 +/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN1 : R; bitpos: [31:27]; default: 0; + * Average initcode of ADC1 atten1 + */ +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1 0x0000001FU +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_S) +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_V 0x0000001FU +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_S 27 /** EFUSE_RD_SYS_PART1_DATA5_REG register * Represents rd_sys_part1_data5 */ #define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE0_BASE + 0x70) -/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0; + * Average initcode of ADC1 atten1 */ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_5_S 0 +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1 0x0000001FU +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_S) +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_V 0x0000001FU +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_S 0 +/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN2 : R; bitpos: [14:5]; default: 0; + * Average initcode of ADC1 atten2 + */ +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2 0x000003FFU +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_S) +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_V 0x000003FFU +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_S 5 +/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN3 : R; bitpos: [24:15]; default: 0; + * Average initcode of ADC1 atten3 + */ +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3 0x000003FFU +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_S) +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_V 0x000003FFU +#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_S 15 +/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0; + * HI_DOUT of ADC1 atten0 + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x0000007FU +#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x0000007FU +#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 25 /** EFUSE_RD_SYS_PART1_DATA6_REG register * Represents rd_sys_part1_data6 */ #define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE0_BASE + 0x74) -/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0; + * HI_DOUT of ADC1 atten0 */ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_6_S 0 +#define EFUSE_ADC1_HI_DOUT_ATTEN0_1 0x00000007U +#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V 0x00000007U +#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S 0 +/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0; + * HI_DOUT of ADC1 atten1 + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x000003FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x000003FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 3 +/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0; + * HI_DOUT of ADC1 atten2 + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 13 +/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0; + * HI_DOUT of ADC1 atten3 + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000001FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000001FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 23 /** EFUSE_RD_SYS_PART1_DATA7_REG register * Represents rd_sys_part1_data7 */ #define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE0_BASE + 0x78) -/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0; + * HI_DOUT of ADC1 atten3 */ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_7_S 0 +#define EFUSE_ADC1_HI_DOUT_ATTEN3_1 (BIT(0)) +#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V 0x00000001U +#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S 0 +/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0; + * Gap between ADC1 CH0 and average initcode + */ +#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 1 +/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0; + * Gap between ADC1 CH1 and average initcode + */ +#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 5 +/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0; + * Gap between ADC1 CH2 and average initcode + */ +#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 9 +/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0; + * Gap between ADC1 CH3 and average initcode + */ +#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 13 +/** EFUSE_RESERVED_2_241 : R; bitpos: [31:17]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_241 0x00007FFFU +#define EFUSE_RESERVED_2_241_M (EFUSE_RESERVED_2_241_V << EFUSE_RESERVED_2_241_S) +#define EFUSE_RESERVED_2_241_V 0x00007FFFU +#define EFUSE_RESERVED_2_241_S 17 /** EFUSE_RD_USR_DATA0_REG register * Represents rd_usr_data0 diff --git a/components/soc/esp32c61/register/soc/efuse_struct.h b/components/soc/esp32c61/register/soc/efuse_struct.h index 1ae0eb37c3..291d8b4565 100644 --- a/components/soc/esp32c61/register/soc/efuse_struct.h +++ b/components/soc/esp32c61/register/soc/efuse_struct.h @@ -456,10 +456,10 @@ typedef union { * Represents MAC address. High 16-bit. */ uint32_t mac_1:16; - /** c61_no_extention : R; bitpos: [31:16]; default: 0; - * Reserved + /** rd_reserve_1_48 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ - uint32_t c61_no_extention:16; + uint32_t rd_reserve_1_48:16; }; uint32_t val; } efuse_rd_mac_sys1_reg_t; @@ -627,10 +627,22 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** temperature_sensor : R; bitpos: [8:0]; default: 0; + * Temperature calibration data */ - uint32_t sys_data_part1_4:32; + uint32_t temperature_sensor:9; + /** ocode : R; bitpos: [16:9]; default: 0; + * ADC OCode calibration + */ + uint32_t ocode:8; + /** adc1_ave_init_code_atten0 : R; bitpos: [26:17]; default: 0; + * Average initcode of ADC1 atten0 + */ + uint32_t adc1_ave_init_code_atten0:10; + /** adc1_ave_init_code_atten1 : R; bitpos: [31:27]; default: 0; + * Average initcode of ADC1 atten1 + */ + uint32_t adc1_ave_init_code_atten1:5; }; uint32_t val; } efuse_rd_sys_part1_data4_reg_t; @@ -640,10 +652,22 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** adc1_ave_init_code_atten1_1 : R; bitpos: [4:0]; default: 0; + * Average initcode of ADC1 atten1 */ - uint32_t sys_data_part1_5:32; + uint32_t adc1_ave_init_code_atten1_1:5; + /** adc1_ave_init_code_atten2 : R; bitpos: [14:5]; default: 0; + * Average initcode of ADC1 atten2 + */ + uint32_t adc1_ave_init_code_atten2:10; + /** adc1_ave_init_code_atten3 : R; bitpos: [24:15]; default: 0; + * Average initcode of ADC1 atten3 + */ + uint32_t adc1_ave_init_code_atten3:10; + /** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0; + * HI_DOUT of ADC1 atten0 + */ + uint32_t adc1_hi_dout_atten0:7; }; uint32_t val; } efuse_rd_sys_part1_data5_reg_t; @@ -653,10 +677,22 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0; + * HI_DOUT of ADC1 atten0 */ - uint32_t sys_data_part1_6:32; + uint32_t adc1_hi_dout_atten0_1:3; + /** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0; + * HI_DOUT of ADC1 atten1 + */ + uint32_t adc1_hi_dout_atten1:10; + /** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0; + * HI_DOUT of ADC1 atten2 + */ + uint32_t adc1_hi_dout_atten2:10; + /** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0; + * HI_DOUT of ADC1 atten3 + */ + uint32_t adc1_hi_dout_atten3:9; }; uint32_t val; } efuse_rd_sys_part1_data6_reg_t; @@ -666,10 +702,30 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0; + * HI_DOUT of ADC1 atten3 */ - uint32_t sys_data_part1_7:32; + uint32_t adc1_hi_dout_atten3_1:1; + /** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0; + * Gap between ADC1 CH0 and average initcode + */ + uint32_t adc1_ch0_atten0_initcode_diff:4; + /** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0; + * Gap between ADC1 CH1 and average initcode + */ + uint32_t adc1_ch1_atten0_initcode_diff:4; + /** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0; + * Gap between ADC1 CH2 and average initcode + */ + uint32_t adc1_ch2_atten0_initcode_diff:4; + /** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0; + * Gap between ADC1 CH3 and average initcode + */ + uint32_t adc1_ch3_atten0_initcode_diff:4; + /** reserved_2_241 : R; bitpos: [31:17]; default: 0; + * reserved + */ + uint32_t reserved_2_241:15; }; uint32_t val; } efuse_rd_sys_part1_data7_reg_t;