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Merge branch 'refactor/common_rom_rtc_apis' into 'master'

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soc: define reset reasons in soc component

Closes IDF-1993

See merge request espressif/esp-idf!9829
This commit is contained in:
morris 2021-07-13 07:05:25 +00:00
commit 3e2d98500f
47 changed files with 624 additions and 314 deletions
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2
components/app_update/test/test_switch_ota.c
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@ -14,10 +14,8 @@
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h" #include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h" #include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/rtc.h"
#endif #endif
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"

3
components/bootloader_support/include/bootloader_common.h
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@ -8,7 +8,8 @@
#include "esp_flash_partitions.h" #include "esp_flash_partitions.h"
#include "esp_image_format.h" #include "esp_image_format.h"
#include "esp_app_format.h" #include "esp_app_format.h"
// RESET_REASON is declared in rom/rtc.h // [refactor-todo]: we shouldn't expose ROM header files in a public API header, remove them in v5.0
// Tracked in IDF-1968
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/rtc.h" #include "esp32/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_IDF_TARGET_ESP32S2

19
components/bootloader_support/src/bootloader_clock_init.c
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@ -8,23 +8,10 @@
#include "soc/rtc.h" #include "soc/rtc.h"
#include "soc/efuse_periph.h" #include "soc/efuse_periph.h"
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#if CONFIG_IDF_TARGET_ESP32
#define CPU_RESET_REASON RTC_SW_CPU_RESET
#ifdef CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h" #include "soc/dport_reg.h"
#include "esp32/rom/rtc.h"
#undef CPU_RESET_REASON
#define CPU_RESET_REASON SW_CPU_RESET
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/rtc.h"
#endif #endif
#include "esp_rom_sys.h"
#include "esp_rom_uart.h" #include "esp_rom_uart.h"
__attribute__((weak)) void bootloader_clock_configure(void) __attribute__((weak)) void bootloader_clock_configure(void)
@ -52,7 +39,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
} }
#endif #endif
if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) { if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || esp_rom_get_reset_reason(0) != RESET_REASON_CPU0_SW) {
rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT(); rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ; clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;

2
components/bootloader_support/src/bootloader_common.c
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@ -194,5 +194,5 @@ void bootloader_common_vddsdio_configure(void)
RESET_REASON bootloader_common_get_reset_reason(int cpu_no) RESET_REASON bootloader_common_get_reset_reason(int cpu_no)
{ {
return rtc_get_reset_reason(cpu_no); return (RESET_REASON)esp_rom_get_reset_reason(cpu_no);
} }

9
components/bootloader_support/src/bootloader_utility.c
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@ -13,23 +13,21 @@
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
#include "esp_rom_uart.h" #include "esp_rom_uart.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h" #include "soc/dport_reg.h"
#include "esp32/rom/cache.h" #include "esp32/rom/cache.h"
#include "esp32/rom/spi_flash.h" #include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/secure_boot.h" #include "esp32/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h" #include "esp32s2/rom/cache.h"
#include "esp32s2/rom/spi_flash.h" #include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/secure_boot.h" #include "esp32s2/rom/secure_boot.h"
#include "soc/extmem_reg.h" #include "soc/extmem_reg.h"
#include "soc/cache_memory.h" #include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32S3 #elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/cache.h" #include "esp32s3/rom/cache.h"
#include "esp32s3/rom/spi_flash.h" #include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/rtc.h"
#include "esp32s3/rom/secure_boot.h" #include "esp32s3/rom/secure_boot.h"
#include "soc/extmem_reg.h" #include "soc/extmem_reg.h"
#include "soc/cache_memory.h" #include "soc/cache_memory.h"
@ -39,7 +37,6 @@
#include "esp32c3/rom/ets_sys.h" #include "esp32c3/rom/ets_sys.h"
#include "esp32c3/rom/spi_flash.h" #include "esp32c3/rom/spi_flash.h"
#include "esp32c3/rom/crc.h" #include "esp32c3/rom/crc.h"
#include "esp32c3/rom/rtc.h"
#include "esp32c3/rom/uart.h" #include "esp32c3/rom/uart.h"
#include "esp32c3/rom/gpio.h" #include "esp32c3/rom/gpio.h"
#include "esp32c3/rom/secure_boot.h" #include "esp32c3/rom/secure_boot.h"
@ -51,7 +48,6 @@
#include "esp32h2/rom/ets_sys.h" #include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/spi_flash.h" #include "esp32h2/rom/spi_flash.h"
#include "esp32h2/rom/crc.h" #include "esp32h2/rom/crc.h"
#include "esp32h2/rom/rtc.h"
#include "esp32h2/rom/uart.h" #include "esp32h2/rom/uart.h"
#include "esp32h2/rom/gpio.h" #include "esp32h2/rom/gpio.h"
#include "esp32h2/rom/secure_boot.h" #include "esp32h2/rom/secure_boot.h"
@ -69,7 +65,6 @@
#include "soc/rtc_periph.h" #include "soc/rtc_periph.h"
#include "soc/timer_periph.h" #include "soc/timer_periph.h"
#include "sdkconfig.h"
#include "esp_image_format.h" #include "esp_image_format.h"
#include "esp_secure_boot.h" #include "esp_secure_boot.h"
#include "esp_flash_encrypt.h" #include "esp_flash_encrypt.h"
@ -456,7 +451,7 @@ static void set_actual_ota_seq(const bootloader_state_t *bs, int index)
#ifdef CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP #ifdef CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP
void bootloader_utility_load_boot_image_from_deep_sleep(void) void bootloader_utility_load_boot_image_from_deep_sleep(void)
{ {
if (rtc_get_reset_reason(0) == DEEPSLEEP_RESET) { if (esp_rom_get_reset_reason(0) == RESET_REASON_CORE_DEEP_SLEEP) {
esp_partition_pos_t *partition = bootloader_common_get_rtc_retain_mem_partition(); esp_partition_pos_t *partition = bootloader_common_get_rtc_retain_mem_partition();
if (partition != NULL) { if (partition != NULL) {
esp_image_metadata_t image_data; esp_image_metadata_t image_data;

15
components/bootloader_support/src/esp32/bootloader_esp32.c
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@ -33,7 +33,6 @@
#include "esp_rom_efuse.h" #include "esp_rom_efuse.h"
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
#include "esp32/rom/spi_flash.h" #include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp_efuse.h" #include "esp_efuse.h"
static const char *TAG = "boot.esp32"; static const char *TAG = "boot.esp32";
@ -323,17 +322,17 @@ static void wdt_reset_info_dump(int cpu)
static void bootloader_check_wdt_reset(void) static void bootloader_check_wdt_reset(void)
{ {
int wdt_rst = 0; int wdt_rst = 0;
RESET_REASON rst_reas[2]; soc_reset_reason_t rst_reas[2];
rst_reas[0] = rtc_get_reset_reason(0); rst_reas[0] = esp_rom_get_reset_reason(0);
rst_reas[1] = rtc_get_reset_reason(1); rst_reas[1] = esp_rom_get_reset_reason(1);
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET || if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
rst_reas[0] == TGWDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) { rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT."); ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
wdt_rst = 1; wdt_rst = 1;
} }
if (rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET || rst_reas[1] == TG1WDT_SYS_RESET || if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
rst_reas[1] == TGWDT_CPU_RESET || rst_reas[1] == RTCWDT_CPU_RESET) { rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
ESP_LOGW(TAG, "APP CPU has been reset by WDT."); ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
wdt_rst = 1; wdt_rst = 1;
} }

9
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
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@ -28,7 +28,6 @@
#include "esp32c3/rom/cache.h" #include "esp32c3/rom/cache.h"
#include "esp32c3/rom/ets_sys.h" #include "esp32c3/rom/ets_sys.h"
#include "esp32c3/rom/spi_flash.h" #include "esp32c3/rom/spi_flash.h"
#include "esp32c3/rom/rtc.h"
#include "bootloader_common.h" #include "bootloader_common.h"
#include "bootloader_init.h" #include "bootloader_init.h"
#include "bootloader_clock.h" #include "bootloader_clock.h"
@ -234,11 +233,9 @@ static void wdt_reset_info_dump(int cpu)
static void bootloader_check_wdt_reset(void) static void bootloader_check_wdt_reset(void)
{ {
int wdt_rst = 0; int wdt_rst = 0;
RESET_REASON rst_reas[2]; soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
rst_reas[0] = rtc_get_reset_reason(0); rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT."); ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
wdt_rst = 1; wdt_rst = 1;
} }

9
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
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@ -28,7 +28,6 @@
#include "esp32h2/rom/cache.h" #include "esp32h2/rom/cache.h"
#include "esp32h2/rom/ets_sys.h" #include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/spi_flash.h" #include "esp32h2/rom/spi_flash.h"
#include "esp32h2/rom/rtc.h"
#include "bootloader_common.h" #include "bootloader_common.h"
#include "bootloader_init.h" #include "bootloader_init.h"
#include "bootloader_clock.h" #include "bootloader_clock.h"
@ -233,11 +232,9 @@ static void wdt_reset_info_dump(int cpu)
static void bootloader_check_wdt_reset(void) static void bootloader_check_wdt_reset(void)
{ {
int wdt_rst = 0; int wdt_rst = 0;
RESET_REASON rst_reas[2]; soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
rst_reas[0] = rtc_get_reset_reason(0); rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT."); ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
wdt_rst = 1; wdt_rst = 1;
} }

11
components/bootloader_support/src/esp32s2/bootloader_esp32s2.c
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@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include <stdint.h> #include <stdint.h>
#include <string.h>
#include "sdkconfig.h" #include "sdkconfig.h"
#include "bootloader_common.h" #include "bootloader_common.h"
#include "soc/efuse_reg.h" #include "soc/efuse_reg.h"
@ -23,7 +24,6 @@
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
#include "esp32s2/rom/cache.h" #include "esp32s2/rom/cache.h"
#include "esp32s2/rom/spi_flash.h" #include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/rtc.h"
#include "esp_attr.h" #include "esp_attr.h"
#include "esp_log.h" #include "esp_log.h"
@ -35,7 +35,6 @@
#include "soc/extmem_reg.h" #include "soc/extmem_reg.h"
#include "soc/rtc.h" #include "soc/rtc.h"
#include "soc/spi_periph.h" #include "soc/spi_periph.h"
#include <string.h>
#include "esp_efuse.h" #include "esp_efuse.h"
static const char *TAG = "boot.esp32s2"; static const char *TAG = "boot.esp32s2";
@ -256,11 +255,9 @@ static void wdt_reset_info_dump(int cpu)
static void bootloader_check_wdt_reset(void) static void bootloader_check_wdt_reset(void)
{ {
int wdt_rst = 0; int wdt_rst = 0;
RESET_REASON rst_reas[2]; soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
rst_reas[0] = rtc_get_reset_reason(0); rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT."); ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
wdt_rst = 1; wdt_rst = 1;
} }

14
components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
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@ -265,14 +265,20 @@ static void wdt_reset_info_dump(int cpu)
static void bootloader_check_wdt_reset(void) static void bootloader_check_wdt_reset(void)
{ {
int wdt_rst = 0; int wdt_rst = 0;
RESET_REASON rst_reas[2]; soc_reset_reason_t rst_reas[2];
rst_reas[0] = rtc_get_reset_reason(0); rst_reas[0] = esp_rom_get_reset_reason(0);
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET || rst_reas[1] = esp_rom_get_reset_reason(1);
rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) { if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT."); ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
wdt_rst = 1; wdt_rst = 1;
} }
if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
wdt_rst = 1;
}
if (wdt_rst) { if (wdt_rst) {
// if reset by WDT dump info from trace port // if reset by WDT dump info from trace port
wdt_reset_info_dump(0); wdt_reset_info_dump(0);

10
components/bootloader_support/src/esp_image_format.c
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@ -17,21 +17,17 @@
#include <bootloader_sha.h> #include <bootloader_sha.h>
#include "bootloader_util.h" #include "bootloader_util.h"
#include "bootloader_common.h" #include "bootloader_common.h"
#include "esp_rom_sys.h"
#include "soc/soc_memory_layout.h" #include "soc/soc_memory_layout.h"
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/rtc.h"
#include "esp32/rom/secure_boot.h" #include "esp32/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/secure_boot.h" #include "esp32s2/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S3 #elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/rtc.h"
#include "esp32s3/rom/secure_boot.h" #include "esp32s3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C3 #elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#include "esp32c3/rom/secure_boot.h" #include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H2 #elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/rtc.h"
#include "esp32h2/rom/secure_boot.h" #include "esp32h2/rom/secure_boot.h"
#endif #endif
@ -254,7 +250,7 @@ esp_err_t bootloader_load_image(const esp_partition_pos_t *part, esp_image_metad
#if CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS #if CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS
mode = ESP_IMAGE_LOAD_NO_VALIDATE; mode = ESP_IMAGE_LOAD_NO_VALIDATE;
#elif CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON #elif CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON
if (rtc_get_reset_reason(0) == POWERON_RESET) { if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) {
mode = ESP_IMAGE_LOAD_NO_VALIDATE; mode = ESP_IMAGE_LOAD_NO_VALIDATE;
} }
#endif // CONFIG_BOOTLOADER_SKIP_... #endif // CONFIG_BOOTLOADER_SKIP_...
@ -685,7 +681,7 @@ static bool should_load(uint32_t load_addr)
{ {
/* Reload the RTC memory segments whenever a non-deepsleep reset /* Reload the RTC memory segments whenever a non-deepsleep reset
is occurring */ is occurring */
bool load_rtc_memory = rtc_get_reset_reason(0) != DEEPSLEEP_RESET; bool load_rtc_memory = esp_rom_get_reset_reason(0) != RESET_REASON_CORE_DEEP_SLEEP;
if (should_map(load_addr)) { if (should_map(load_addr)) {
return false; return false;

5
components/esp_hw_support/sleep_modes.c
View File

@ -48,12 +48,13 @@
#include "sdkconfig.h" #include "sdkconfig.h"
#include "esp_rom_uart.h" #include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "brownout.h" #include "brownout.h"
#ifdef CONFIG_IDF_TARGET_ESP32 #ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/cache.h" #include "esp32/rom/cache.h"
#include "esp32/clk.h"
#include "esp32/rom/rtc.h" #include "esp32/rom/rtc.h"
#include "esp32/clk.h"
#include "esp_private/gpio.h" #include "esp_private/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/clk.h" #include "esp32s2/clk.h"
@ -1199,7 +1200,7 @@ esp_err_t esp_sleep_disable_wifi_wakeup(void)
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void) esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
{ {
if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET && !s_light_sleep_wakeup) { if (esp_rom_get_reset_reason(0) != RESET_REASON_CORE_DEEP_SLEEP && !s_light_sleep_wakeup) {
return ESP_SLEEP_WAKEUP_UNDEFINED; return ESP_SLEEP_WAKEUP_UNDEFINED;
} }

8
components/esp_hw_support/test/test_rtc_clk.c
View File

@ -365,8 +365,8 @@ static void trigger_deepsleep(void)
static void check_time_deepsleep_1(void) static void check_time_deepsleep_1(void)
{ {
RESET_REASON reason = rtc_get_reset_reason(0); soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET); TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
int64_t end = esp_rtc_get_time_us(); int64_t end = esp_rtc_get_time_us();
TEST_ASSERT_GREATER_THAN(start, end); TEST_ASSERT_GREATER_THAN(start, end);
@ -385,8 +385,8 @@ static void check_time_deepsleep_1(void)
static void check_time_deepsleep_2(void) static void check_time_deepsleep_2(void)
{ {
RESET_REASON reason = rtc_get_reset_reason(0); soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET); TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
int64_t end = esp_rtc_get_time_us(); int64_t end = esp_rtc_get_time_us();
TEST_ASSERT_GREATER_THAN(start, end); TEST_ASSERT_GREATER_THAN(start, end);
} }

14
components/esp_phy/src/phy_init.c
View File

@ -34,17 +34,12 @@
#include "driver/periph_ctrl.h" #include "driver/periph_ctrl.h"
#include "esp_private/wifi.h" #include "esp_private/wifi.h"
#include "esp_rom_crc.h" #include "esp_rom_crc.h"
#include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32C3
#include "esp32/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "soc/syscon_reg.h" #include "soc/syscon_reg.h"
#elif CONFIG_IDF_TARGET_ESP32S3 #elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/rtc.h"
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "soc/syscon_reg.h" #include "soc/syscon_reg.h"
#endif #endif
@ -605,12 +600,9 @@ void esp_phy_load_cal_and_init(void)
} }
memcpy(init_data, phy_init_data, sizeof(esp_phy_init_data_t)); memcpy(init_data, phy_init_data, sizeof(esp_phy_init_data_t));
#if CONFIG_IDF_TARGET_ESP32
// ToDo: remove once esp_reset_reason is supported on esp32s2
if (esp_reset_reason() == ESP_RST_BROWNOUT) { if (esp_reset_reason() == ESP_RST_BROWNOUT) {
esp_phy_reduce_tx_power(init_data); esp_phy_reduce_tx_power(init_data);
} }
#endif
#else #else
const esp_phy_init_data_t* init_data = esp_phy_get_init_data(); const esp_phy_init_data_t* init_data = esp_phy_get_init_data();
if (init_data == NULL) { if (init_data == NULL) {
@ -622,7 +614,7 @@ void esp_phy_load_cal_and_init(void)
#ifdef CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE #ifdef CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE
esp_phy_calibration_mode_t calibration_mode = PHY_RF_CAL_PARTIAL; esp_phy_calibration_mode_t calibration_mode = PHY_RF_CAL_PARTIAL;
uint8_t sta_mac[6]; uint8_t sta_mac[6];
if (rtc_get_reset_reason(0) == DEEPSLEEP_RESET) { if (esp_rom_get_reset_reason(0) == RESET_REASON_CORE_DEEP_SLEEP) {
calibration_mode = PHY_RF_CAL_NONE; calibration_mode = PHY_RF_CAL_NONE;
} }
esp_err_t err = esp_phy_load_cal_data_from_nvs(cal_data); esp_err_t err = esp_phy_load_cal_data_from_nvs(cal_data);

1
components/esp_rom/esp32/ld/esp32.rom.api.ld
View File

@ -37,3 +37,4 @@ PROVIDE ( esp_rom_md5_final = 0x4005db1c );
PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

1
components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld
View File

@ -33,3 +33,4 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

1
components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld
View File

@ -33,3 +33,4 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

1
components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
View File

@ -36,3 +36,4 @@ PROVIDE ( esp_rom_md5_final = 0x4000530c );
PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

1
components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
View File

@ -37,5 +37,6 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE( esp_rom_spiflash_attach = spi_flash_attach ); PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );

14
components/esp_rom/include/esp32/rom/rtc.h
View File

@ -22,6 +22,7 @@
#include "soc/soc.h" #include "soc/soc.h"
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -98,6 +99,19 @@ typedef enum {
RTCWDT_RTC_RESET = 16 /**<16, RTC Watch dog reset digital core and rtc module*/ RTCWDT_RTC_RESET = 16 /**<16, RTC Watch dog reset digital core and rtc module*/
} RESET_REASON; } RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
_Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
_Static_assert((soc_reset_reason_t)SW_RESET == RESET_REASON_CORE_SW, "SW_RESET != RESET_REASON_CORE_SW");
_Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
_Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
_Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
_Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
_Static_assert((soc_reset_reason_t)TGWDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TGWDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
_Static_assert((soc_reset_reason_t)SW_CPU_RESET == RESET_REASON_CPU0_SW, "SW_CPU_RESET != RESET_REASON_CPU0_SW");
_Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
_Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
typedef enum { typedef enum {
NO_SLEEP = 0, NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0, EXT_EVENT0_TRIG = BIT0,

15
components/esp_rom/include/esp32c3/rom/rtc.h
View File

@ -22,6 +22,7 @@
#include "soc/soc.h" #include "soc/soc.h"
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -99,6 +100,20 @@ typedef enum {
SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/ SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/
} RESET_REASON; } RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
_Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
_Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
_Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
_Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
_Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
_Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
_Static_assert((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
_Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
_Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
_Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
_Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
typedef enum { typedef enum {
NO_SLEEP = 0, NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0, EXT_EVENT0_TRIG = BIT0,

15
components/esp_rom/include/esp32h2/rom/rtc.h
View File

@ -22,6 +22,7 @@
#include "soc/soc.h" #include "soc/soc.h"
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -99,6 +100,20 @@ typedef enum {
SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/ SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/
} RESET_REASON; } RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
_Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
_Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
_Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
_Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
_Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
_Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
_Static_assert((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
_Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
_Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
_Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
_Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
typedef enum { typedef enum {
NO_SLEEP = 0, NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0, EXT_EVENT0_TRIG = BIT0,

16
components/esp_rom/include/esp32s2/rom/rtc.h
View File

@ -22,6 +22,7 @@
#include "soc/soc.h" #include "soc/soc.h"
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -98,6 +99,21 @@ typedef enum {
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/ GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
} RESET_REASON; } RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
_Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
_Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
_Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
_Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
_Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
_Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
_Static_assert((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
_Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
_Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
_Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
_Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
_Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
typedef enum { typedef enum {
NO_SLEEP = 0, NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0, EXT_EVENT0_TRIG = BIT0,

17
components/esp_rom/include/esp32s3/rom/rtc.h
View File

@ -17,6 +17,7 @@
#include <stdbool.h> #include <stdbool.h>
#include <stdint.h> #include <stdint.h>
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -93,6 +94,22 @@ typedef enum {
EFUSE_RESET = 20, /**<20, efuse reset digital core*/ EFUSE_RESET = 20, /**<20, efuse reset digital core*/
} RESET_REASON; } RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
_Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
_Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
_Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
_Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
_Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
_Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
_Static_assert((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
_Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
_Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
_Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
_Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
_Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
_Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
typedef enum { typedef enum {
NO_SLEEP = 0, NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0, EXT_EVENT0_TRIG = BIT0,

13
components/esp_rom/include/esp_rom_sys.h
View File

@ -14,12 +14,13 @@
#pragma once #pragma once
#include <stdint.h>
#include "soc/reset_reasons.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include <stdint.h>
/** /**
* @brief Print formated string to console device * @brief Print formated string to console device
* @note float and long long data are not supported! * @note float and long long data are not supported!
@ -51,6 +52,14 @@ void esp_rom_install_channel_putc(int channel, void (*putc)(char c));
*/ */
void esp_rom_install_uart_printf(void); void esp_rom_install_uart_printf(void);
/**
* @brief Get reset reason of CPU
*
* @param cpu_no CPU number
* @return Reset reason code (see in soc/reset_reasons.h)
*/
soc_reset_reason_t esp_rom_get_reset_reason(int cpu_no);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

19
components/esp_system/port/cpu_start.c
View File

@ -35,19 +35,16 @@
#include "soc/dport_reg.h" #include "soc/dport_reg.h"
#include "esp32/rtc.h" #include "esp32/rtc.h"
#include "esp32/rom/cache.h" #include "esp32/rom/cache.h"
#include "esp32/rom/rtc.h"
#include "esp32/spiram.h" #include "esp32/spiram.h"
#elif CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rtc.h" #include "esp32s2/rtc.h"
#include "esp32s2/rom/cache.h" #include "esp32s2/rom/cache.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/spiram.h" #include "esp32s2/spiram.h"
#include "esp32s2/dport_access.h" #include "esp32s2/dport_access.h"
#include "esp32s2/memprot.h" #include "esp32s2/memprot.h"
#elif CONFIG_IDF_TARGET_ESP32S3 #elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rtc.h" #include "esp32s3/rtc.h"
#include "esp32s3/rom/cache.h" #include "esp32s3/rom/cache.h"
#include "esp32s3/rom/rtc.h"
#include "esp32s3/spiram.h" #include "esp32s3/spiram.h"
#include "esp32s3/dport_access.h" #include "esp32s3/dport_access.h"
#include "esp32s3/memprot.h" #include "esp32s3/memprot.h"
@ -58,13 +55,11 @@
#elif CONFIG_IDF_TARGET_ESP32C3 #elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rtc.h" #include "esp32c3/rtc.h"
#include "esp32c3/rom/cache.h" #include "esp32c3/rom/cache.h"
#include "esp32c3/rom/rtc.h"
#include "soc/cache_memory.h" #include "soc/cache_memory.h"
#include "esp32c3/memprot.h" #include "esp32c3/memprot.h"
#elif CONFIG_IDF_TARGET_ESP32H2 #elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rtc.h" #include "esp32h2/rtc.h"
#include "esp32h2/rom/cache.h" #include "esp32h2/rom/cache.h"
#include "esp32h2/rom/rtc.h"
#include "soc/cache_memory.h" #include "soc/cache_memory.h"
#include "esp32h2/memprot.h" #include "esp32h2/memprot.h"
#endif #endif
@ -274,9 +269,9 @@ static void intr_matrix_clear(void)
void IRAM_ATTR call_start_cpu0(void) void IRAM_ATTR call_start_cpu0(void)
{ {
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
RESET_REASON rst_reas[SOC_CPU_CORES_NUM]; soc_reset_reason_t rst_reas[SOC_CPU_CORES_NUM];
#else #else
RESET_REASON rst_reas[1]; soc_reset_reason_t rst_reas[1];
#endif #endif
#ifdef __riscv #ifdef __riscv
@ -301,16 +296,16 @@ void IRAM_ATTR call_start_cpu0(void)
// Move exception vectors to IRAM // Move exception vectors to IRAM
cpu_hal_set_vecbase(&_vector_table); cpu_hal_set_vecbase(&_vector_table);
rst_reas[0] = rtc_get_reset_reason(0); rst_reas[0] = esp_rom_get_reset_reason(0);
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
rst_reas[1] = rtc_get_reset_reason(1); rst_reas[1] = esp_rom_get_reset_reason(1);
#endif #endif
#ifndef CONFIG_BOOTLOADER_WDT_ENABLE #ifndef CONFIG_BOOTLOADER_WDT_ENABLE
// from panic handler we can be reset by RWDT or TG0WDT // from panic handler we can be reset by RWDT or TG0WDT
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|| rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET || rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0
#endif #endif
) { ) {
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
@ -329,7 +324,7 @@ void IRAM_ATTR call_start_cpu0(void)
#endif #endif
/* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */ /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
if (rst_reas[0] != DEEPSLEEP_RESET) { if (rst_reas[0] != RESET_REASON_CORE_DEEP_SLEEP) {
memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start)); memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
} }

15
components/esp_system/port/soc/esp32/clk.c
View File

@ -27,8 +27,8 @@
#include "esp_log.h" #include "esp_log.h"
#include "esp32/clk.h" #include "esp32/clk.h"
#include "esp32/rom/rtc.h"
#include "esp_rom_uart.h" #include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "sdkconfig.h" #include "sdkconfig.h"
@ -213,23 +213,22 @@ __attribute__((weak)) void esp_perip_clk_init(void)
uint32_t wifi_bt_sdio_clk; uint32_t wifi_bt_sdio_clk;
#if CONFIG_FREERTOS_UNICORE #if CONFIG_FREERTOS_UNICORE
RESET_REASON rst_reas[1]; soc_reset_reason_t rst_reas[1];
#else #else
RESET_REASON rst_reas[2]; soc_reset_reason_t rst_reas[2];
#endif #endif
rst_reas[0] = rtc_get_reset_reason(0); rst_reas[0] = esp_rom_get_reset_reason(0);
#if !CONFIG_FREERTOS_UNICORE #if !CONFIG_FREERTOS_UNICORE
rst_reas[1] = rtc_get_reset_reason(1); rst_reas[1] = esp_rom_get_reset_reason(1);
#endif #endif
/* For reason that only reset CPU, do not disable the clocks /* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset. * that have been enabled before reset.
*/ */
if ((rst_reas[0] >= TGWDT_CPU_RESET && rst_reas[0] <= RTCWDT_CPU_RESET) if ((rst_reas[0] >= RESET_REASON_CPU0_MWDT0 && rst_reas[0] <= RESET_REASON_CPU0_RTC_WDT)
#if !CONFIG_FREERTOS_UNICORE #if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= TGWDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET) || (rst_reas[1] >= RESET_REASON_CPU1_MWDT1 && rst_reas[1] <= RESET_REASON_CPU1_RTC_WDT)
#endif #endif
) { ) {
common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG); common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);

40
components/esp_system/port/soc/esp32/reset_reason.c
View File

@ -13,26 +13,23 @@
// limitations under the License. // limitations under the License.
#include "esp_system.h" #include "esp_system.h"
#include "esp32/rom/rtc.h" #include "esp_rom_sys.h"
#include "esp_private/system_internal.h" #include "esp_private/system_internal.h"
#include "soc/rtc_periph.h" #include "soc/rtc_periph.h"
#include "esp32/rom/rtc.h"
static void esp_reset_reason_clear_hint(void); static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason; static esp_reset_reason_t s_reset_reason;
static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint) static esp_reset_reason_t get_reset_reason(uint32_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{ {
switch (rtc_reset_reason) { switch (rtc_reset_reason) {
case POWERON_RESET: case RESET_REASON_CHIP_POWER_ON:
return ESP_RST_POWERON; return ESP_RST_POWERON;
/* For ESP32, ESP_RST_EXT is never returned */ case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
case SW_CPU_RESET:
case SW_RESET:
case EXT_CPU_RESET: /* unused */
if (reset_reason_hint == ESP_RST_PANIC || if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT || reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT || reset_reason_hint == ESP_RST_TASK_WDT ||
@ -41,29 +38,27 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
} }
return ESP_RST_SW; return ESP_RST_SW;
case DEEPSLEEP_RESET: case RESET_REASON_CORE_DEEP_SLEEP:
return ESP_RST_DEEPSLEEP; return ESP_RST_DEEPSLEEP;
case TG0WDT_SYS_RESET: case RESET_REASON_CORE_MWDT0:
return ESP_RST_TASK_WDT; return ESP_RST_TASK_WDT;
case TG1WDT_SYS_RESET: case RESET_REASON_CORE_MWDT1:
return ESP_RST_INT_WDT; return ESP_RST_INT_WDT;
case OWDT_RESET: case RESET_REASON_CORE_RTC_WDT:
case RTCWDT_SYS_RESET: case RESET_REASON_SYS_RTC_WDT:
case RTCWDT_RTC_RESET: case RESET_REASON_CPU0_RTC_WDT:
case RTCWDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_MWDT0:
case TGWDT_CPU_RESET: /* unused */
return ESP_RST_WDT; return ESP_RST_WDT;
case RTCWDT_BROWN_OUT_RESET: /* unused */ case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT; return ESP_RST_BROWNOUT;
case SDIO_RESET: case RESET_REASON_CORE_SDIO:
return ESP_RST_SDIO; return ESP_RST_SDIO;
case INTRUSION_RESET: /* unused */
default: default:
return ESP_RST_UNKNOWN; return ESP_RST_UNKNOWN;
} }
@ -72,8 +67,7 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
static void __attribute__((constructor)) esp_reset_reason_init(void) static void __attribute__((constructor)) esp_reset_reason_init(void)
{ {
esp_reset_reason_t hint = esp_reset_reason_get_hint(); esp_reset_reason_t hint = esp_reset_reason_get_hint();
s_reset_reason = get_reset_reason(rtc_get_reset_reason(PRO_CPU_NUM), s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
hint);
if (hint != ESP_RST_UNKNOWN) { if (hint != ESP_RST_UNKNOWN) {
esp_reset_reason_clear_hint(); esp_reset_reason_clear_hint();
} }
@ -88,7 +82,7 @@ esp_reset_reason_t esp_reset_reason(void)
* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the * a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
* deep sleep wake stub entry address and for reset reason hint, since wake stub * deep sleep wake stub entry address and for reset reason hint, since wake stub
* is only used for deep sleep reset, and in this case the reason provided by * is only used for deep sleep reset, and in this case the reason provided by
* rtc_get_reset_reason is unambiguous. * esp_rom_get_reset_reason is unambiguous.
* *
* Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG): * Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
* the value is replicated in low and high half-words. In addition to that, * the value is replicated in low and high half-words. In addition to that,

25
components/esp_system/port/soc/esp32c3/clk.c
View File

@ -23,7 +23,6 @@
#include "esp_clk_internal.h" #include "esp_clk_internal.h"
#include "esp32c3/rom/ets_sys.h" #include "esp32c3/rom/ets_sys.h"
#include "esp32c3/rom/uart.h" #include "esp32c3/rom/uart.h"
#include "esp32c3/rom/rtc.h"
#include "soc/system_reg.h" #include "soc/system_reg.h"
#include "soc/dport_access.h" #include "soc/dport_access.h"
#include "soc/soc.h" #include "soc/soc.h"
@ -36,6 +35,7 @@
#include "bootloader_clock.h" #include "bootloader_clock.h"
#include "soc/syscon_reg.h" #include "soc/syscon_reg.h"
#include "esp_rom_uart.h" #include "esp_rom_uart.h"
#include "esp_rom_sys.h"
/* Number of cycles to wait from the 32k XTAL oscillator to consider it running. /* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
* Larger values increase startup delay. Smaller values may cause false positive * Larger values increase startup delay. Smaller values may cause false positive
@ -75,9 +75,9 @@ static const char *TAG = "clk";
{ {
#if !CONFIG_IDF_ENV_FPGA #if !CONFIG_IDF_ENV_FPGA
rtc_config_t cfg = RTC_CONFIG_DEFAULT(); rtc_config_t cfg = RTC_CONFIG_DEFAULT();
RESET_REASON rst_reas; soc_reset_reason_t rst_reas;
rst_reas = rtc_get_reset_reason(0); rst_reas = esp_rom_get_reset_reason(0);
if (rst_reas == POWERON_RESET) { if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
cfg.cali_ocode = 1; cfg.cali_ocode = 1;
} }
rtc_init(cfg); rtc_init(cfg);
@ -211,16 +211,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
uint32_t common_perip_clk1 = 0; uint32_t common_perip_clk1 = 0;
#if CONFIG_FREERTOS_UNICORE soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
RESET_REASON rst_reas[1];
#else
RESET_REASON rst_reas[2];
#endif
rst_reas[0] = rtc_get_reset_reason(0);
#if !CONFIG_FREERTOS_UNICORE
rst_reas[1] = rtc_get_reset_reason(1);
#endif
/* For reason that only reset CPU, do not disable the clocks /* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset. * that have been enabled before reset.
@ -228,11 +219,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* For reason that only reset CPU, do not disable the clocks /* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset. * that have been enabled before reset.
*/ */
if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET) if (rst_reason >= RESET_REASON_CPU0_MWDT0 && rst_reason <= RESET_REASON_CPU0_RTC_WDT && rst_reason != RESET_REASON_SYS_BROWN_OUT) {
#if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= TG0WDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
#endif
) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG); wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);

37
components/esp_system/port/soc/esp32c3/reset_reason.c
View File

@ -13,22 +13,23 @@
// limitations under the License. // limitations under the License.
#include "esp_system.h" #include "esp_system.h"
#include "esp32c3/rom/rtc.h" #include "esp_rom_sys.h"
#include "esp_private/system_internal.h" #include "esp_private/system_internal.h"
#include "soc/rtc_periph.h" #include "soc/rtc_periph.h"
#include "esp32c3/rom/rtc.h"
static void esp_reset_reason_clear_hint(void); static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason; static esp_reset_reason_t s_reset_reason;
static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint) static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{ {
switch (rtc_reset_reason) { switch (rtc_reset_reason) {
case POWERON_RESET: case RESET_REASON_CHIP_POWER_ON:
return ESP_RST_POWERON; return ESP_RST_POWERON;
case RTC_SW_CPU_RESET: case RESET_REASON_CPU0_SW:
case RTC_SW_SYS_RESET: case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC || if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT || reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT || reset_reason_hint == ESP_RST_TASK_WDT ||
@ -37,27 +38,26 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
} }
return ESP_RST_SW; return ESP_RST_SW;
case DEEPSLEEP_RESET: case RESET_REASON_CORE_DEEP_SLEEP:
return ESP_RST_DEEPSLEEP; return ESP_RST_DEEPSLEEP;
case TG0WDT_SYS_RESET: case RESET_REASON_CORE_MWDT0:
return ESP_RST_TASK_WDT; return ESP_RST_TASK_WDT;
case TG1WDT_SYS_RESET: case RESET_REASON_CORE_MWDT1:
return ESP_RST_INT_WDT; return ESP_RST_INT_WDT;
case RTCWDT_SYS_RESET: case RESET_REASON_CORE_RTC_WDT:
case RTCWDT_RTC_RESET: case RESET_REASON_SYS_RTC_WDT:
case SUPER_WDT_RESET: case RESET_REASON_SYS_SUPER_WDT:
case RTCWDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_RTC_WDT:
case TG0WDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_MWDT0:
case TG1WDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_MWDT1:
return ESP_RST_WDT; return ESP_RST_WDT;
case RTCWDT_BROWN_OUT_RESET: case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT; return ESP_RST_BROWNOUT;
case INTRUSION_RESET: /* unused */
default: default:
return ESP_RST_UNKNOWN; return ESP_RST_UNKNOWN;
} }
@ -66,8 +66,7 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
static void __attribute__((constructor)) esp_reset_reason_init(void) static void __attribute__((constructor)) esp_reset_reason_init(void)
{ {
esp_reset_reason_t hint = esp_reset_reason_get_hint(); esp_reset_reason_t hint = esp_reset_reason_get_hint();
s_reset_reason = get_reset_reason(rtc_get_reset_reason(PRO_CPU_NUM), s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
hint);
if (hint != ESP_RST_UNKNOWN) { if (hint != ESP_RST_UNKNOWN) {
esp_reset_reason_clear_hint(); esp_reset_reason_clear_hint();
} }
@ -82,7 +81,7 @@ esp_reset_reason_t esp_reset_reason(void)
* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the * a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
* deep sleep wake stub entry address and for reset reason hint, since wake stub * deep sleep wake stub entry address and for reset reason hint, since wake stub
* is only used for deep sleep reset, and in this case the reason provided by * is only used for deep sleep reset, and in this case the reason provided by
* rtc_get_reset_reason is unambiguous. * esp_rom_get_reset_reason is unambiguous.
* *
* Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG): * Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
* the value is replicated in low and high half-words. In addition to that, * the value is replicated in low and high half-words. In addition to that,

25
components/esp_system/port/soc/esp32h2/clk.c
View File

@ -23,7 +23,6 @@
#include "esp_clk_internal.h" #include "esp_clk_internal.h"
#include "esp32h2/rom/ets_sys.h" #include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/uart.h" #include "esp32h2/rom/uart.h"
#include "esp32h2/rom/rtc.h"
#include "soc/system_reg.h" #include "soc/system_reg.h"
#include "soc/dport_access.h" #include "soc/dport_access.h"
#include "soc/soc.h" #include "soc/soc.h"
@ -36,6 +35,7 @@
#include "bootloader_clock.h" #include "bootloader_clock.h"
#include "soc/syscon_reg.h" #include "soc/syscon_reg.h"
#include "esp_rom_uart.h" #include "esp_rom_uart.h"
#include "esp_rom_sys.h"
/* Number of cycles to wait from the 32k XTAL oscillator to consider it running. /* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
* Larger values increase startup delay. Smaller values may cause false positive * Larger values increase startup delay. Smaller values may cause false positive
@ -75,9 +75,9 @@ static const char *TAG = "clk";
{ {
#if !CONFIG_IDF_ENV_FPGA #if !CONFIG_IDF_ENV_FPGA
rtc_config_t cfg = RTC_CONFIG_DEFAULT(); rtc_config_t cfg = RTC_CONFIG_DEFAULT();
RESET_REASON rst_reas; soc_reset_reason_t rst_reas;
rst_reas = rtc_get_reset_reason(0); rst_reas = esp_rom_get_reset_reason(0);
if (rst_reas == POWERON_RESET) { if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
cfg.cali_ocode = 1; cfg.cali_ocode = 1;
} }
rtc_init(cfg); rtc_init(cfg);
@ -211,16 +211,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
uint32_t common_perip_clk, hwcrypto_perip_clk = 0; uint32_t common_perip_clk, hwcrypto_perip_clk = 0;
uint32_t common_perip_clk1 = 0; uint32_t common_perip_clk1 = 0;
#if CONFIG_FREERTOS_UNICORE soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
RESET_REASON rst_reas[1];
#else
RESET_REASON rst_reas[2];
#endif
rst_reas[0] = rtc_get_reset_reason(0);
#if !CONFIG_FREERTOS_UNICORE
rst_reas[1] = rtc_get_reset_reason(1);
#endif
/* For reason that only reset CPU, do not disable the clocks /* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset. * that have been enabled before reset.
@ -228,11 +219,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* For reason that only reset CPU, do not disable the clocks /* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset. * that have been enabled before reset.
*/ */
if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET) if (rst_reason >= RESET_REASON_CPU0_MWDT0 && rst_reason <= RESET_REASON_CPU0_RTC_WDT && rst_reason != RESET_REASON_SYS_BROWN_OUT) {
#if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= TG0WDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
#endif
) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
} else { } else {

37
components/esp_system/port/soc/esp32h2/reset_reason.c
View File

@ -13,22 +13,23 @@
// limitations under the License. // limitations under the License.
#include "esp_system.h" #include "esp_system.h"
#include "esp32h2/rom/rtc.h" #include "esp_rom_sys.h"
#include "esp_private/system_internal.h" #include "esp_private/system_internal.h"
#include "soc/rtc_periph.h" #include "soc/rtc_periph.h"
#include "esp32h2/rom/rtc.h"
static void esp_reset_reason_clear_hint(void); static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason; static esp_reset_reason_t s_reset_reason;
static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint) static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{ {
switch (rtc_reset_reason) { switch (rtc_reset_reason) {
case POWERON_RESET: case RESET_REASON_CHIP_POWER_ON:
return ESP_RST_POWERON; return ESP_RST_POWERON;
case RTC_SW_CPU_RESET: case RESET_REASON_CPU0_SW:
case RTC_SW_SYS_RESET: case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC || if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT || reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT || reset_reason_hint == ESP_RST_TASK_WDT ||
@ -37,27 +38,26 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
} }
return ESP_RST_SW; return ESP_RST_SW;
case DEEPSLEEP_RESET: case RESET_REASON_CORE_DEEP_SLEEP:
return ESP_RST_DEEPSLEEP; return ESP_RST_DEEPSLEEP;
case TG0WDT_SYS_RESET: case RESET_REASON_CORE_MWDT0:
return ESP_RST_TASK_WDT; return ESP_RST_TASK_WDT;
case TG1WDT_SYS_RESET: case RESET_REASON_CORE_MWDT1:
return ESP_RST_INT_WDT; return ESP_RST_INT_WDT;
case RTCWDT_SYS_RESET: case RESET_REASON_CORE_RTC_WDT:
case RTCWDT_RTC_RESET: case RESET_REASON_SYS_RTC_WDT:
case SUPER_WDT_RESET: case RESET_REASON_SYS_SUPER_WDT:
case RTCWDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_RTC_WDT:
case TG0WDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_MWDT0:
case TG1WDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_MWDT1:
return ESP_RST_WDT; return ESP_RST_WDT;
case RTCWDT_BROWN_OUT_RESET: case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT; return ESP_RST_BROWNOUT;
case INTRUSION_RESET: /* unused */
default: default:
return ESP_RST_UNKNOWN; return ESP_RST_UNKNOWN;
} }
@ -66,8 +66,7 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
static void __attribute__((constructor)) esp_reset_reason_init(void) static void __attribute__((constructor)) esp_reset_reason_init(void)
{ {
esp_reset_reason_t hint = esp_reset_reason_get_hint(); esp_reset_reason_t hint = esp_reset_reason_get_hint();
s_reset_reason = get_reset_reason(rtc_get_reset_reason(PRO_CPU_NUM), s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
hint);
if (hint != ESP_RST_UNKNOWN) { if (hint != ESP_RST_UNKNOWN) {
esp_reset_reason_clear_hint(); esp_reset_reason_clear_hint();
} }
@ -82,7 +81,7 @@ esp_reset_reason_t esp_reset_reason(void)
* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the * a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
* deep sleep wake stub entry address and for reset reason hint, since wake stub * deep sleep wake stub entry address and for reset reason hint, since wake stub
* is only used for deep sleep reset, and in this case the reason provided by * is only used for deep sleep reset, and in this case the reason provided by
* rtc_get_reset_reason is unambiguous. * esp_rom_get_reset_reason is unambiguous.
* *
* Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG): * Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
* the value is replicated in low and high half-words. In addition to that, * the value is replicated in low and high half-words. In addition to that,

15
components/esp_system/port/soc/esp32s2/clk.c
View File

@ -22,8 +22,8 @@
#include "esp_log.h" #include "esp_log.h"
#include "esp32s2/clk.h" #include "esp32s2/clk.h"
#include "esp_clk_internal.h" #include "esp_clk_internal.h"
#include "esp32s2/rom/rtc.h"
#include "esp_rom_uart.h" #include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "soc/system_reg.h" #include "soc/system_reg.h"
#include "soc/dport_access.h" #include "soc/dport_access.h"
#include "soc/soc.h" #include "soc/soc.h"
@ -77,9 +77,8 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
__attribute__((weak)) void esp_clk_init(void) __attribute__((weak)) void esp_clk_init(void)
{ {
rtc_config_t cfg = RTC_CONFIG_DEFAULT(); rtc_config_t cfg = RTC_CONFIG_DEFAULT();
RESET_REASON rst_reas; soc_reset_reason_t rst_reas = esp_rom_get_reset_reason(0);
rst_reas = rtc_get_reset_reason(0); if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
if (rst_reas == POWERON_RESET) {
cfg.cali_ocode = 1; cfg.cali_ocode = 1;
} }
rtc_init(cfg); rtc_init(cfg);
@ -214,16 +213,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
uint32_t common_perip_clk1 = 0; uint32_t common_perip_clk1 = 0;
RESET_REASON rst_reas[1]; soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
rst_reas[0] = rtc_get_reset_reason(0);
/* For reason that only reset CPU, do not disable the clocks /* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset. * that have been enabled before reset.
*/ */
if (rst_reas[0] >= TG0WDT_CPU_RESET && if (rst_reason >= RESET_REASON_CPU0_MWDT0 && rst_reason <= RESET_REASON_CPU0_RTC_WDT && rst_reason != RESET_REASON_SYS_BROWN_OUT) {
rst_reas[0] <= TG0WDT_CPU_RESET &&
rst_reas[0] != RTCWDT_BROWN_OUT_RESET) {
common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG); common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG); hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG);
wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG); wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);

37
components/esp_system/port/soc/esp32s2/reset_reason.c
View File

@ -13,22 +13,23 @@
// limitations under the License. // limitations under the License.
#include "esp_system.h" #include "esp_system.h"
#include "esp32s2/rom/rtc.h" #include "esp_rom_sys.h"
#include "esp_private/system_internal.h" #include "esp_private/system_internal.h"
#include "soc/rtc_periph.h" #include "soc/rtc_periph.h"
#include "esp32s2/rom/rtc.h"
static void esp_reset_reason_clear_hint(void); static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason; static esp_reset_reason_t s_reset_reason;
static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint) static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{ {
switch (rtc_reset_reason) { switch (rtc_reset_reason) {
case POWERON_RESET: case RESET_REASON_CHIP_POWER_ON:
return ESP_RST_POWERON; return ESP_RST_POWERON;
case RTC_SW_CPU_RESET: case RESET_REASON_CPU0_SW:
case RTC_SW_SYS_RESET: case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC || if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT || reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT || reset_reason_hint == ESP_RST_TASK_WDT ||
@ -37,27 +38,26 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
} }
return ESP_RST_SW; return ESP_RST_SW;
case DEEPSLEEP_RESET: case RESET_REASON_CORE_DEEP_SLEEP:
return ESP_RST_DEEPSLEEP; return ESP_RST_DEEPSLEEP;
case TG0WDT_SYS_RESET: case RESET_REASON_CORE_MWDT0:
return ESP_RST_TASK_WDT; return ESP_RST_TASK_WDT;
case TG1WDT_SYS_RESET: case RESET_REASON_CORE_MWDT1:
return ESP_RST_INT_WDT; return ESP_RST_INT_WDT;
case RTCWDT_SYS_RESET: case RESET_REASON_CORE_RTC_WDT:
case RTCWDT_RTC_RESET: case RESET_REASON_SYS_RTC_WDT:
case SUPER_WDT_RESET: case RESET_REASON_SYS_SUPER_WDT:
case RTCWDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_RTC_WDT:
case TG0WDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_MWDT0:
case TG1WDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_MWDT1:
return ESP_RST_WDT; return ESP_RST_WDT;
case RTCWDT_BROWN_OUT_RESET: case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT; return ESP_RST_BROWNOUT;
case INTRUSION_RESET: /* unused */
default: default:
return ESP_RST_UNKNOWN; return ESP_RST_UNKNOWN;
} }
@ -66,8 +66,7 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
static void __attribute__((constructor)) esp_reset_reason_init(void) static void __attribute__((constructor)) esp_reset_reason_init(void)
{ {
esp_reset_reason_t hint = esp_reset_reason_get_hint(); esp_reset_reason_t hint = esp_reset_reason_get_hint();
s_reset_reason = get_reset_reason(rtc_get_reset_reason(PRO_CPU_NUM), s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
hint);
if (hint != ESP_RST_UNKNOWN) { if (hint != ESP_RST_UNKNOWN) {
esp_reset_reason_clear_hint(); esp_reset_reason_clear_hint();
} }
@ -82,7 +81,7 @@ esp_reset_reason_t esp_reset_reason(void)
* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the * a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
* deep sleep wake stub entry address and for reset reason hint, since wake stub * deep sleep wake stub entry address and for reset reason hint, since wake stub
* is only used for deep sleep reset, and in this case the reason provided by * is only used for deep sleep reset, and in this case the reason provided by
* rtc_get_reset_reason is unambiguous. * esp_rom_get_reset_reason is unambiguous.
* *
* Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG): * Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
* the value is replicated in low and high half-words. In addition to that, * the value is replicated in low and high half-words. In addition to that,

15
components/esp_system/port/soc/esp32s3/clk.c
View File

@ -22,9 +22,8 @@
#include "esp_log.h" #include "esp_log.h"
#include "esp32s3/clk.h" #include "esp32s3/clk.h"
#include "esp_clk_internal.h" #include "esp_clk_internal.h"
#include "esp32s3/rom/ets_sys.h"
#include "esp32s3/rom/rtc.h"
#include "esp_rom_uart.h" #include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "soc/system_reg.h" #include "soc/system_reg.h"
#include "soc/dport_access.h" #include "soc/dport_access.h"
#include "soc/soc.h" #include "soc/soc.h"
@ -210,22 +209,22 @@ __attribute__((weak)) void esp_perip_clk_init(void)
uint32_t common_perip_clk1 = 0; uint32_t common_perip_clk1 = 0;
#if CONFIG_FREERTOS_UNICORE #if CONFIG_FREERTOS_UNICORE
RESET_REASON rst_reas[1]; soc_reset_reason_t rst_reas[1];
#else #else
RESET_REASON rst_reas[2]; soc_reset_reason_t rst_reas[2];
#endif #endif
rst_reas[0] = rtc_get_reset_reason(0); rst_reas[0] = esp_rom_get_reset_reason(0);
#if !CONFIG_FREERTOS_UNICORE #if !CONFIG_FREERTOS_UNICORE
rst_reas[1] = rtc_get_reset_reason(1); rst_reas[1] = esp_rom_get_reset_reason(1);
#endif #endif
/* For reason that only reset CPU, do not disable the clocks /* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset. * that have been enabled before reset.
*/ */
if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET) if ((rst_reas[0] >= RESET_REASON_CPU0_MWDT0 && rst_reas[0] <= RESET_REASON_CPU0_RTC_WDT && rst_reas[0] != RESET_REASON_SYS_BROWN_OUT)
#if !CONFIG_FREERTOS_UNICORE #if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= TG0WDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET) || (rst_reas[1] >= RESET_REASON_CPU1_MWDT1 && rst_reas[1] <= RESET_REASON_CPU1_RTC_WDT && rst_reas[1] != RESET_REASON_SYS_BROWN_OUT)
#endif #endif
) { ) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);

37
components/esp_system/port/soc/esp32s3/reset_reason.c
View File

@ -13,22 +13,23 @@
// limitations under the License. // limitations under the License.
#include "esp_system.h" #include "esp_system.h"
#include "esp32s3/rom/rtc.h" #include "esp_rom_sys.h"
#include "esp_private/system_internal.h" #include "esp_private/system_internal.h"
#include "soc/rtc_periph.h" #include "soc/rtc_periph.h"
#include "esp32s3/rom/rtc.h"
static void esp_reset_reason_clear_hint(void); static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason; static esp_reset_reason_t s_reset_reason;
static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint) static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{ {
switch (rtc_reset_reason) { switch (rtc_reset_reason) {
case POWERON_RESET: case RESET_REASON_CHIP_POWER_ON:
return ESP_RST_POWERON; return ESP_RST_POWERON;
case RTC_SW_CPU_RESET: case RESET_REASON_CPU0_SW:
case RTC_SW_SYS_RESET: case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC || if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT || reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT || reset_reason_hint == ESP_RST_TASK_WDT ||
@ -37,27 +38,26 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
} }
return ESP_RST_SW; return ESP_RST_SW;
case DEEPSLEEP_RESET: case RESET_REASON_CORE_DEEP_SLEEP:
return ESP_RST_DEEPSLEEP; return ESP_RST_DEEPSLEEP;
case TG0WDT_SYS_RESET: case RESET_REASON_CORE_MWDT0:
return ESP_RST_TASK_WDT; return ESP_RST_TASK_WDT;
case TG1WDT_SYS_RESET: case RESET_REASON_CORE_MWDT1:
return ESP_RST_INT_WDT; return ESP_RST_INT_WDT;
case RTCWDT_SYS_RESET: case RESET_REASON_CORE_RTC_WDT:
case RTCWDT_RTC_RESET: case RESET_REASON_SYS_RTC_WDT:
case SUPER_WDT_RESET: case RESET_REASON_SYS_SUPER_WDT:
case RTCWDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_RTC_WDT:
case TG0WDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_MWDT0:
case TG1WDT_CPU_RESET: /* unused */ case RESET_REASON_CPU0_MWDT1:
return ESP_RST_WDT; return ESP_RST_WDT;
case RTCWDT_BROWN_OUT_RESET: case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT; return ESP_RST_BROWNOUT;
case INTRUSION_RESET: /* unused */
default: default:
return ESP_RST_UNKNOWN; return ESP_RST_UNKNOWN;
} }
@ -66,8 +66,7 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
static void __attribute__((constructor)) esp_reset_reason_init(void) static void __attribute__((constructor)) esp_reset_reason_init(void)
{ {
esp_reset_reason_t hint = esp_reset_reason_get_hint(); esp_reset_reason_t hint = esp_reset_reason_get_hint();
s_reset_reason = get_reset_reason(rtc_get_reset_reason(PRO_CPU_NUM), s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
hint);
if (hint != ESP_RST_UNKNOWN) { if (hint != ESP_RST_UNKNOWN) {
esp_reset_reason_clear_hint(); esp_reset_reason_clear_hint();
} }
@ -82,7 +81,7 @@ esp_reset_reason_t esp_reset_reason(void)
* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the * a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
* deep sleep wake stub entry address and for reset reason hint, since wake stub * deep sleep wake stub entry address and for reset reason hint, since wake stub
* is only used for deep sleep reset, and in this case the reason provided by * is only used for deep sleep reset, and in this case the reason provided by
* rtc_get_reset_reason is unambiguous. * esp_rom_get_reset_reason is unambiguous.
* *
* In addition to that, MSB is set to 1, which doesn't happen when * In addition to that, MSB is set to 1, which doesn't happen when
* RTC_CNTL_STORE6_REG contains deep sleep wake stub address. * RTC_CNTL_STORE6_REG contains deep sleep wake stub address.

11
components/esp_system/test/test_sleep.c
View File

@ -3,7 +3,6 @@
#include <sys/param.h> #include <sys/param.h>
#include "esp_sleep.h" #include "esp_sleep.h"
#include "driver/rtc_io.h" #include "driver/rtc_io.h"
#include "esp_rom_uart.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/task.h" #include "freertos/task.h"
#include "freertos/semphr.h" #include "freertos/semphr.h"
@ -17,6 +16,7 @@
#include "esp_newlib.h" #include "esp_newlib.h"
#include "test_utils.h" #include "test_utils.h"
#include "sdkconfig.h" #include "sdkconfig.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
#include "esp_timer.h" #include "esp_timer.h"
@ -24,19 +24,14 @@
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
#include "esp32/clk.h" #include "esp32/clk.h"
#include "esp32/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/clk.h" #include "esp32s2/clk.h"
#include "esp32s2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S3 #elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/clk.h" #include "esp32s3/clk.h"
#include "esp32s3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C3 #elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/clk.h" #include "esp32c3/clk.h"
#include "esp32c3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32H2 #elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/clk.h" #include "esp32h2/clk.h"
#include "esp32h2/rom/rtc.h"
#endif #endif
#define ESP_EXT0_WAKEUP_LEVEL_LOW 0 #define ESP_EXT0_WAKEUP_LEVEL_LOW 0
@ -531,8 +526,8 @@ static void trigger_deepsleep(void)
static void check_time_deepsleep(void) static void check_time_deepsleep(void)
{ {
struct timeval stop; struct timeval stop;
RESET_REASON reason = rtc_get_reset_reason(0); soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET); TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
gettimeofday(&stop, NULL); gettimeofday(&stop, NULL);
// Time dt_ms must in any case be positive. // Time dt_ms must in any case be positive.
int dt_ms = (stop.tv_sec - start.tv_sec) * 1000 + (stop.tv_usec - start.tv_usec) / 1000; int dt_ms = (stop.tv_sec - start.tv_sec) * 1000 + (stop.tv_usec - start.tv_usec) / 1000;

58
components/soc/esp32/include/soc/reset_reasons.h Normal file
View File

@ -0,0 +1,58 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_SDIO = 0x06, // SDIO module resets the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU1_MWDT1 = 0x0B, // Main watch dog 1 resets CPU 1
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0
RESET_REASON_CPU1_SW = 0x0C, // Software resets CPU 1
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_CPU1_RTC_WDT = 0x0D, // RTC watch dog resets CPU 1
RESET_REASON_CPU1_CPU0 = 0x0E, // CPU0 resets CPU1 by DPORT_APPCPU_RESETTING
RESET_REASON_SYS_BROWN_OUT = 0x0F, // Reset when the VDD voltage is not stable
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

61
components/soc/esp32c3/include/soc/reset_reasons.h Normal file
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@ -0,0 +1,61 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

61
components/soc/esp32h2/include/soc/reset_reasons.h Normal file
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@ -0,0 +1,61 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

58
components/soc/esp32s2/include/soc/reset_reasons.h Normal file
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@ -0,0 +1,58 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

64
components/soc/esp32s3/include/soc/reset_reasons.h Normal file
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@ -0,0 +1,64 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU1_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 1
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU1_SW = 0x0C, // Software resets CPU 1 by RTC_CNTL_SW_APPCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_CPU1_RTC_WDT = 0x0D, // RTC watch dog resets CPU 1
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_CPU1_MWDT1 = 0x11, // Main watch dog 1 resets CPU 1
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

4
docs/en/api-guides/unit-tests-legacy.rst
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@ -120,8 +120,8 @@ To support this, we can define multi-stage test cases, to group a set of test fu
void check_deepsleep_reset_reason() void check_deepsleep_reset_reason()
{ {
RESET_REASON reason = rtc_get_reset_reason(0); soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET); TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
} }
TEST_CASE_MULTIPLE_STAGES("reset reason check for deepsleep", "[esp32]", trigger_deepsleep, check_deepsleep_reset_reason); TEST_CASE_MULTIPLE_STAGES("reset reason check for deepsleep", "[esp32]", trigger_deepsleep, check_deepsleep_reset_reason);

4
docs/en/api-guides/unit-tests.rst
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@ -108,8 +108,8 @@ The normal test cases are expected to finish without reset (or only need to chec
void check_deepsleep_reset_reason() void check_deepsleep_reset_reason()
{ {
RESET_REASON reason = rtc_get_reset_reason(0); soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET); TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
} }
TEST_CASE_MULTIPLE_STAGES("reset reason check for deepsleep", "[{IDF_TARGET_PATH_NAME}]", trigger_deepsleep, check_deepsleep_reset_reason); TEST_CASE_MULTIPLE_STAGES("reset reason check for deepsleep", "[{IDF_TARGET_PATH_NAME}]", trigger_deepsleep, check_deepsleep_reset_reason);

4
docs/zh_CN/api-guides/unit-tests-legacy.rst
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@ -137,8 +137,8 @@ DUT2 终端::
void check_deepsleep_reset_reason() void check_deepsleep_reset_reason()
{ {
RESET_REASON reason = rtc_get_reset_reason(0); soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET); TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
} }
TEST_CASE_MULTIPLE_STAGES("reset reason check for deepsleep", "[esp32]", trigger_deepsleep, check_deepsleep_reset_reason); TEST_CASE_MULTIPLE_STAGES("reset reason check for deepsleep", "[esp32]", trigger_deepsleep, check_deepsleep_reset_reason);

4
docs/zh_CN/api-guides/unit-tests.rst
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@ -105,8 +105,8 @@ DUT2（slave）终端::
void check_deepsleep_reset_reason() void check_deepsleep_reset_reason()
{ {
RESET_REASON reason = rtc_get_reset_reason(0); soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET); TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
} }
TEST_CASE_MULTIPLE_STAGES("reset reason check for deepsleep", "[{IDF_TARGET_PATH_NAME}]", trigger_deepsleep, check_deepsleep_reset_reason); TEST_CASE_MULTIPLE_STAGES("reset reason check for deepsleep", "[{IDF_TARGET_PATH_NAME}]", trigger_deepsleep, check_deepsleep_reset_reason);

4
tools/ci/check_public_headers_exceptions.txt
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@ -111,11 +111,15 @@ components/esp_hw_support/port/esp32/regi2c_ctrl.h
components/esp_rom/include/esp32/rom/sha.h components/esp_rom/include/esp32/rom/sha.h
components/esp_rom/include/esp32/rom/secure_boot.h components/esp_rom/include/esp32/rom/secure_boot.h
components/esp_rom/include/esp32c3/rom/spi_flash.h components/esp_rom/include/esp32c3/rom/spi_flash.h
components/esp_rom/include/esp32c3/rom/rtc.h
components/esp_rom/include/esp32s2/rom/spi_flash.h components/esp_rom/include/esp32s2/rom/spi_flash.h
components/esp_rom/include/esp32s2/rom/cache.h components/esp_rom/include/esp32s2/rom/cache.h
components/esp_rom/include/esp32s2/rom/secure_boot.h components/esp_rom/include/esp32s2/rom/secure_boot.h
components/esp_rom/include/esp32s2/rom/opi_flash.h components/esp_rom/include/esp32s2/rom/opi_flash.h
components/esp_rom/include/esp32s2/rom/rtc.h
components/esp_rom/include/esp32s2/rom/efuse.h components/esp_rom/include/esp32s2/rom/efuse.h
components/esp_rom/include/esp32s3/rom/rtc.h
components/esp_rom/include/esp32h2/rom/rtc.h
components/esp32/include/esp32/dport_access.h components/esp32/include/esp32/dport_access.h
components/esp32/include/rom/sha.h components/esp32/include/rom/sha.h
components/esp32/include/rom/secure_boot.h components/esp32/include/rom/secure_boot.h