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feat(esp32h21): ci enable public header check (stage7)

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This commit is contained in:
gaoxu 2024-12-24 16:44:08 +08:00
parent 8905189743
commit 3e30d2e928
25 changed files with 148 additions and 103 deletions
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1
.gitlab/ci/host-test.yml
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@ -33,6 +33,7 @@ check_public_headers:
- IDF_TARGET=esp32h2 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
- IDF_TARGET=esp32p4 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
- IDF_TARGET=esp32c61 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
- IDF_TARGET=esp32h21 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
test_nvs_coverage:
extends:

2
components/driver/deprecated/driver/adc_types_legacy.h
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@ -70,7 +70,7 @@ typedef enum {
ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO4 */
ADC1_CHANNEL_MAX,
} adc1_channel_t;
#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5
#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32H21
typedef enum {
ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */
ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */

16
components/esp_adc/esp32h21/include/adc_cali_schemes.h Normal file
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@ -0,0 +1,16 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file adc_cali_schemes.h
*
* @brief Supported calibration schemes
*/
//TODO: [ESP32H21] IDF-11590
// #define ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED 1

0
components/esp_adc/esp32h21/include/.gitkeep → components/esp_hw_support/include/soc/esp32h21/rtc.h
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0
components/esp_hw_support/include/soc/esp32h21/.gitkeep → components/esp_hw_support/lowpower/port/esp32h21/sleep_cpu.c
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1
components/esp_hw_support/port/esp32h21/CMakeLists.txt
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@ -0,0 +1 @@
target_include_directories(${COMPONENT_LIB} PUBLIC . include)

0
components/esp_hw_support/port/esp32h21/include/soc/rtc.h Normal file
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0
components/esp_hw_support/port/esp32h21/systimer.c Normal file
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0
components/esp_rom/patches/esp_rom_regi2c_esp32h21.c Normal file
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4
components/esp_system/port/soc/esp32h21/cache_err_int.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -18,7 +18,7 @@
#include "riscv/interrupt.h"
#include "hal/cache_ll.h"
// TODO: [ESP32H21] IDF-11900, IDF-11909
// TODO: [ESP32H21] IDF-11524
static const char *TAG = "CACHE_ERR";

2
components/hal/esp32h21/include/hal/cache_ll.h
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@ -9,7 +9,7 @@
#pragma once
#include <stdbool.h>
#include "soc/extmem_reg.h"
#include "soc/cache_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"

2
components/hal/esp32h21/include/hal/mwdt_ll.h
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@ -23,7 +23,7 @@ extern "C" {
#include "esp_attr.h"
#include "hal/misc.h"
//TODO: [ESP32H21] IDF-11874, inherit from h2
//TODO: [ESP32H21] IDF-11528, inherit from h2
/* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
#define MWDT_LL_DEFAULT_CLK_PRESCALER 16000

7
components/hal/include/hal/clk_tree_hal.h
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@ -8,9 +8,12 @@
#include <stdint.h>
#include "soc/clk_tree_defs.h"
#include "soc/clkout_channel.h"
#include "soc/soc_caps.h"
#if SOC_GPIO_CLOCKOUT_CHANNEL_NUM > 0 //TODO: [ESP32H21] IDF-11582
#include "soc/clkout_channel.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
@ -61,6 +64,7 @@ uint32_t clk_hal_xtal_get_freq_mhz(void);
uint32_t clk_hal_apll_get_freq_hz(void);
#endif //SOC_CLK_APLL_SUPPORTED
#if SOC_GPIO_CLOCKOUT_CHANNEL_NUM > 0 //TODO: [ESP32H21] IDF-11582
/**
* @brief Set up clock output channel
* @param clk_sig The clock signal source to be mapped to GPIOs
@ -82,6 +86,7 @@ void clk_hal_clock_output_set_divider(clock_out_channel_t channel_id, uint32_t d
* @param channel_id The clock output channel to teardown
*/
void clk_hal_clock_output_teardown(clock_out_channel_t channel_id);
#endif
#ifdef __cplusplus
}

5
components/hal/include/hal/ledc_types.h
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@ -35,6 +35,7 @@ typedef enum {
LEDC_DUTY_DIR_MAX,
} ledc_duty_direction_t;
#if SOC_LEDC_SUPPORTED
/**
* @brief LEDC global clock sources
*/
@ -81,6 +82,10 @@ typedef enum {
LEDC_SCLK = LEDC_USE_PLL_DIV_CLK, /*!< Selecting this value for LEDC_TICK_SEL_TIMER let the hardware take its source clock from LEDC_CLK_SEL */
#endif
} ledc_clk_src_t;
#else
typedef int ledc_clk_cfg_t;
typedef int ledc_clk_src_t;
#endif
typedef enum {
LEDC_TIMER_0 = 0, /*!< LEDC timer 0 */

2
components/hal/include/hal/sha_types.h
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@ -27,6 +27,8 @@
#include "esp32c5/rom/sha.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/sha.h"
#elif CONFIG_IDF_TARGET_ESP32H21
#include "esp32h21/rom/sha.h"
#elif CONFIG_IDF_TARGET_ESP32P4
#include "esp32p4/rom/sha.h"
#endif

12
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
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@ -243,18 +243,6 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x000000000FFF807F
config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
bool
default y
config SOC_CLOCKOUT_HAS_SOURCE_GATE
bool
default y
config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8

5
components/soc/esp32h21/include/soc/gdma_channel.h Normal file
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@ -0,0 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

6
components/soc/esp32h21/include/soc/soc.h
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@ -12,18 +12,18 @@
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#include "soc/reg_base.h"
#define PRO_CPU_NUM (0)
// TODO: IDF-11856
#define DR_REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define DR_REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000)
#define DR_REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000)
#define DR_REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define DR_UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define DR_REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H21
#define DR_REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define DR_REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000)
#define DR_REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000)
#define DR_REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
#define DR_REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000)

6
components/soc/esp32h21/include/soc/soc_caps.h
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@ -221,9 +221,9 @@
// #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
// The Clock Out signal is route to the pin by GPIO matrix
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
// #define SOC_CLOCKOUT_HAS_SOURCE_GATE (1)
// #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated LP_IOMUX subsystem on ESP32-H2. LP functions are still supported

5
components/soc/esp32h21/ld/esp32h21.peripherals.ld
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@ -52,6 +52,9 @@ PROVIDE ( LP_AON = 0x600B1000 );
PROVIDE ( LP_WDT = 0x600B1C00 );
PROVIDE ( LPPERI = 0x600B2800 );
PROVIDE ( LP_ANA_PERI = 0x600B2C00 );
PROVIDE ( LP_TIMER = 0x600B3000 );
PROVIDE ( LP_APM = 0x600B3800 );
PROVIDE ( EFUSE = 0x600B4000 );
PROVIDE ( TRACE = 0x600C0000 );
PROVIDE ( ASSIST_DEBUG = 0x600C2000 );
PROVIDE ( INTPRI = 0x600C5000 );
PROVIDE ( CACHE = 0x600C8000 );

140
components/soc/esp32h21/register/soc/interrupt_matrix_reg.h
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@ -13,7 +13,7 @@ extern "C" {
/** INTMTX_CORE0_PMU_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x0)
#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0)
/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PMU_INTR mapping register
*/
@ -25,7 +25,7 @@ extern "C" {
/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x4)
#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4)
/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_EFUSE_INTR mapping register
*/
@ -37,7 +37,7 @@ extern "C" {
/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8)
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8)
/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_RTC_TIMER_INTR mapping register
*/
@ -49,7 +49,7 @@ extern "C" {
/** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc)
#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc)
/** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_BLE_TIMER_INTR mapping register
*/
@ -61,7 +61,7 @@ extern "C" {
/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x10)
#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10)
/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_WDT_INTR mapping register
*/
@ -73,7 +73,7 @@ extern "C" {
/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x14)
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14)
/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_PERI_TIMEOUT_INTR mapping register
*/
@ -85,7 +85,7 @@ extern "C" {
/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x18)
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18)
/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_APM_M0_INTR mapping register
*/
@ -97,7 +97,7 @@ extern "C" {
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTMTX_BASE + 0x1c)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_INTR_FROM_CPU_0 mapping register
*/
@ -109,7 +109,7 @@ extern "C" {
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTMTX_BASE + 0x20)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_INTR_FROM_CPU_1 mapping register
*/
@ -121,7 +121,7 @@ extern "C" {
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTMTX_BASE + 0x24)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_INTR_FROM_CPU_2 mapping register
*/
@ -133,7 +133,7 @@ extern "C" {
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTMTX_BASE + 0x28)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_INTR_FROM_CPU_3 mapping register
*/
@ -145,7 +145,7 @@ extern "C" {
/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x2c)
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c)
/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_ASSIST_DEBUG_INTR mapping register
*/
@ -157,7 +157,7 @@ extern "C" {
/** INTMTX_CORE0_TRACE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x30)
#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30)
/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TRACE_INTR mapping register
*/
@ -169,7 +169,7 @@ extern "C" {
/** INTMTX_CORE0_CACHE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x34)
#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34)
/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CACHE_INTR mapping register
*/
@ -181,7 +181,7 @@ extern "C" {
/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x38)
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38)
/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_PERI_TIMEOUT_INTR mapping register
*/
@ -193,7 +193,7 @@ extern "C" {
/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x3c)
#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c)
/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BT_MAC_INTR mapping register
*/
@ -205,7 +205,7 @@ extern "C" {
/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x40)
#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40)
/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BT_BB_INTR mapping register
*/
@ -217,7 +217,7 @@ extern "C" {
/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x44)
#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44)
/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BT_BB_NMI mapping register
*/
@ -229,7 +229,7 @@ extern "C" {
/** INTMTX_CORE0_COEX_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x48)
#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48)
/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_COEX_INTR mapping register
*/
@ -241,7 +241,7 @@ extern "C" {
/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x4c)
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c)
/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BLE_TIMER_INTR mapping register
*/
@ -253,7 +253,7 @@ extern "C" {
/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x50)
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50)
/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BLE_SEC_INTR mapping register
*/
@ -265,7 +265,7 @@ extern "C" {
/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x54)
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54)
/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_ZB_MAC_INTR mapping register
*/
@ -277,7 +277,7 @@ extern "C" {
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTMTX_BASE + 0x58)
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58)
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_GPIO_INTERRUPT_PRO mapping register
*/
@ -289,7 +289,7 @@ extern "C" {
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x5c)
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c)
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_GPIO_INTERRUPT_PRO_NMI mapping register
*/
@ -301,7 +301,7 @@ extern "C" {
/** INTMTX_CORE0_PAU_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x60)
#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60)
/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PAU_INTR mapping register
*/
@ -313,7 +313,7 @@ extern "C" {
/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x64)
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64)
/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_PERI_TIMEOUT_INTR mapping register
*/
@ -325,7 +325,7 @@ extern "C" {
/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x68)
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68)
/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_APM_M0_INTR mapping register
*/
@ -337,7 +337,7 @@ extern "C" {
/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x6c)
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c)
/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_APM_M1_INTR mapping register
*/
@ -349,7 +349,7 @@ extern "C" {
/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x70)
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70)
/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_APM_M2_INTR mapping register
*/
@ -361,7 +361,7 @@ extern "C" {
/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x74)
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74)
/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_APM_M3_INTR mapping register
*/
@ -373,7 +373,7 @@ extern "C" {
/** INTMTX_CORE0_MSPI_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x78)
#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78)
/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_MSPI_INTR mapping register
*/
@ -385,7 +385,7 @@ extern "C" {
/** INTMTX_CORE0_I2S1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x7c)
#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c)
/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_I2S1_INTR mapping register
*/
@ -397,7 +397,7 @@ extern "C" {
/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x80)
#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80)
/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_UHCI0_INTR mapping register
*/
@ -409,7 +409,7 @@ extern "C" {
/** INTMTX_CORE0_UART0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x84)
#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84)
/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_UART0_INTR mapping register
*/
@ -421,7 +421,7 @@ extern "C" {
/** INTMTX_CORE0_UART1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x88)
#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88)
/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_UART1_INTR mapping register
*/
@ -433,7 +433,7 @@ extern "C" {
/** INTMTX_CORE0_LEDC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8c)
#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c)
/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LEDC_INTR mapping register
*/
@ -445,7 +445,7 @@ extern "C" {
/** INTMTX_CORE0_CAN0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x90)
#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90)
/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CAN0_INTR mapping register
*/
@ -457,7 +457,7 @@ extern "C" {
/** INTMTX_CORE0_USB_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x94)
#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94)
/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_USB_INTR mapping register
*/
@ -469,7 +469,7 @@ extern "C" {
/** INTMTX_CORE0_RMT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x98)
#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98)
/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_RMT_INTR mapping register
*/
@ -481,7 +481,7 @@ extern "C" {
/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x9c)
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c)
/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_I2C_EXT0_INTR mapping register
*/
@ -493,7 +493,7 @@ extern "C" {
/** INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa0)
#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0)
/** INTMTX_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_I2C_EXT1_INTR mapping register
*/
@ -505,7 +505,7 @@ extern "C" {
/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa4)
#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4)
/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TG0_T0_INTR mapping register
*/
@ -517,7 +517,7 @@ extern "C" {
/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa8)
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8)
/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TG0_WDT_INTR mapping register
*/
@ -529,7 +529,7 @@ extern "C" {
/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xac)
#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac)
/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TG1_T0_INTR mapping register
*/
@ -541,7 +541,7 @@ extern "C" {
/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb0)
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0)
/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TG1_WDT_INTR mapping register
*/
@ -553,7 +553,7 @@ extern "C" {
/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb4)
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4)
/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_SYSTIMER_TARGET0_INTR mapping register
*/
@ -565,7 +565,7 @@ extern "C" {
/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb8)
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8)
/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_SYSTIMER_TARGET1_INTR mapping register
*/
@ -577,7 +577,7 @@ extern "C" {
/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xbc)
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc)
/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_SYSTIMER_TARGET2_INTR mapping register
*/
@ -589,7 +589,7 @@ extern "C" {
/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc0)
#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0)
/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_APB_ADC_INTR mapping register
*/
@ -601,7 +601,7 @@ extern "C" {
/** INTMTX_CORE0_PWM_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc4)
#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4)
/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PWM_INTR mapping register
*/
@ -613,7 +613,7 @@ extern "C" {
/** INTMTX_CORE0_PCNT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc8)
#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8)
/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PCNT_INTR mapping register
*/
@ -625,7 +625,7 @@ extern "C" {
/** INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xcc)
#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc)
/** INTMTX_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PARL_IO_TX_INTR mapping register
*/
@ -637,7 +637,7 @@ extern "C" {
/** INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd0)
#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0)
/** INTMTX_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PARL_IO_RX_INTR mapping register
*/
@ -649,7 +649,7 @@ extern "C" {
/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd4)
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4)
/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_IN_CH0_INTR mapping register
*/
@ -661,7 +661,7 @@ extern "C" {
/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd8)
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8)
/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_IN_CH1_INTR mapping register
*/
@ -673,7 +673,7 @@ extern "C" {
/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xdc)
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc)
/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_IN_CH2_INTR mapping register
*/
@ -685,7 +685,7 @@ extern "C" {
/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe0)
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0)
/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_OUT_CH0_INTR mapping register
*/
@ -697,7 +697,7 @@ extern "C" {
/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe4)
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4)
/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_OUT_CH1_INTR mapping register
*/
@ -709,7 +709,7 @@ extern "C" {
/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe8)
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8)
/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_OUT_CH2_INTR mapping register
*/
@ -721,7 +721,7 @@ extern "C" {
/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xec)
#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec)
/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_GPSPI2_INTR mapping register
*/
@ -733,7 +733,7 @@ extern "C" {
/** INTMTX_CORE0_AES_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf0)
#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0)
/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_AES_INTR mapping register
*/
@ -745,7 +745,7 @@ extern "C" {
/** INTMTX_CORE0_SHA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf4)
#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4)
/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_SHA_INTR mapping register
*/
@ -757,7 +757,7 @@ extern "C" {
/** INTMTX_CORE0_RSA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf8)
#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8)
/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_RSA_INTR mapping register
*/
@ -769,7 +769,7 @@ extern "C" {
/** INTMTX_CORE0_ECC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xfc)
#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc)
/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_ECC_INTR mapping register
*/
@ -781,7 +781,7 @@ extern "C" {
/** INTMTX_CORE0_ECDSA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x100)
#define INTMTX_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100)
/** INTMTX_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_ECDSA_INTR mapping register
*/
@ -793,7 +793,7 @@ extern "C" {
/** INTMTX_CORE0_INT_STATUS_REG_0_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTMTX_BASE + 0x104)
#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104)
/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
* Status register for interrupt sources 0~31 mapping register
*/
@ -805,7 +805,7 @@ extern "C" {
/** INTMTX_CORE0_INT_STATUS_REG_1_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTMTX_BASE + 0x108)
#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108)
/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
* Status register for interrupt sources 32~63 mapping register
*/
@ -817,7 +817,7 @@ extern "C" {
/** INTMTX_CORE0_INT_STATUS_REG_2_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTMTX_BASE + 0x10c)
#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c)
/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
* Status register for interrupt sources 64~95 mapping register
*/
@ -829,7 +829,7 @@ extern "C" {
/** INTMTX_CORE0_CLOCK_GATE_REG register
* register description
*/
#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTMTX_BASE + 0x110)
#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110)
/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Clock register
*/
@ -841,7 +841,7 @@ extern "C" {
/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register
* register description
*/
#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTMTX_BASE + 0x7fc)
#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc)
/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35688784;
* Version control register
*/

5
components/soc/esp32h21/register/soc/pmu_struct.h
View File

@ -6,15 +6,12 @@
#pragma once
#include <stdint.h>
#include <stddef.h>
#include "soc/pmu_reg.h"
#ifdef __cplusplus
extern "C"
{
#endif
#include "soc.h"
#include "soc/pmu_reg.h"
typedef union
{
struct

10
components/soc/esp32h21/register/soc/reg_base.h
View File

@ -22,7 +22,7 @@
#define DR_REG_I2S0_BASE 0x6000D000
#define DR_REG_APB_SARADC_BASE 0x6000E000
#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000
#define DR_REG_INTMTX_BASE 0x60010000
#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000
#define DR_REG_PCNT_BASE 0x60012000
#define DR_REG_SOC_ETM_BASE 0x60013000
#define DR_REG_MCPWM0_BASE 0x60014000
@ -54,6 +54,12 @@
#define DR_REG_LP_WDT_BASE 0x600B1C00
#define DR_REG_LPPERI_BASE 0x600B2800
#define DR_REG_LP_ANA_PERI_BASE 0x600B2C00
#define DR_REG_LP_TIMER_BASE 0x600B3000
#define DR_REG_LP_APM_BASE 0x600B3800
#define DR_REG_EFUSE_BASE 0x600B4000
#define DR_REG_TRACE_BASE 0x600C0000
#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000
#define DR_REG_INTPRI_BASE 0x600C5000
#define DR_REG_CACHE_BASE 0x600C8000
#define DR_REG_I2C_ANA_MST_BASE 0x600AD800 //TODO: [ESP32H21] IDF-11550, need check
#define PWDET_CONF_REG 0x600A0810 //TODO: [ESP32H21] IDF-11589, IDF-11592, need check

4
components/soc/esp32h21/register/soc/sha_struct.h
View File

@ -62,7 +62,7 @@ typedef union {
/** continue : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
uint32_t continue:31;
uint32_t conti:31;
};
uint32_t val;
} sha_continue_reg_t;
@ -165,7 +165,7 @@ typedef struct {
uint32_t reserved_004[2];
volatile sha_dma_block_num_reg_t dma_block_num;
volatile sha_start_reg_t start;
volatile sha_continue_reg_t continue;
volatile sha_continue_reg_t conti;
volatile sha_busy_reg_t busy;
volatile sha_dma_start_reg_t dma_start;
volatile sha_dma_continue_reg_t dma_continue;

16
examples/common_components/env_caps/esp32h21/Kconfig.env_caps Normal file
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@ -0,0 +1,16 @@
config ENV_GPIO_RANGE_MIN
int
default 0
config ENV_GPIO_RANGE_MAX
int
default 27
# GPIOs 15/16 are always used by UART in examples
config ENV_GPIO_IN_RANGE_MAX
int
default ENV_GPIO_RANGE_MAX
config ENV_GPIO_OUT_RANGE_MAX
int
default ENV_GPIO_RANGE_MAX