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refactor(i2c): rename some LL functions according to TRM descriptions

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This commit is contained in:
morris 2024-11-20 18:16:34 +08:00
parent 5c9e7670f2
commit 3fb7461eb0
17 changed files with 162 additions and 144 deletions
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4
components/driver/i2c/i2c.c
View File

@ -810,7 +810,7 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf)
#if SOC_I2C_SUPPORT_SLAVE
if (i2c_conf->mode == I2C_MODE_SLAVE) { //slave mode
i2c_hal_slave_init(&(i2c_context[i2c_num].hal));
i2c_ll_slave_tx_auto_start_en(i2c_context[i2c_num].hal.dev, true);
i2c_ll_slave_enable_auto_start(i2c_context[i2c_num].hal.dev, true);
I2C_CLOCK_SRC_ATOMIC() {
i2c_ll_set_source_clk(i2c_context[i2c_num].hal.dev, src_clk);
}
@ -1504,7 +1504,7 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, BaseType_t
}
}
i2c_ll_update(i2c_context[i2c_num].hal.dev);
i2c_ll_master_trans_start(i2c_context[i2c_num].hal.dev);
i2c_ll_start_trans(i2c_context[i2c_num].hal.dev);
return;
}

1
components/esp_driver_i2c/i2c_master.c
View File

@ -130,6 +130,7 @@ static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master)
}
i2c_hal_master_init(hal);
i2c_ll_enable_fifo_mode(hal->dev, true);
i2c_ll_disable_intr_mask(hal->dev, I2C_LL_INTR_MASK);
i2c_ll_clear_intr_mask(hal->dev, I2C_LL_INTR_MASK);
i2c_hal_set_timing_config(hal, &timing_config);

14
components/esp_driver_i2c/i2c_slave.c
View File

@ -247,11 +247,11 @@ esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave
#if SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
if (i2c_slave->fifo_mode == I2C_SLAVE_NONFIFO) {
i2c_ll_slave_set_fifo_mode(hal->dev, false);
i2c_ll_enable_mem_access_nonfifo(hal->dev, true);
i2c_ll_enable_fifo_mode(hal->dev, false);
i2c_ll_slave_enable_dual_addressing_mode(hal->dev, true);
} else {
i2c_ll_slave_set_fifo_mode(hal->dev, true);
i2c_ll_enable_mem_access_nonfifo(hal->dev, false);
i2c_ll_enable_fifo_mode(hal->dev, true);
i2c_ll_slave_enable_dual_addressing_mode(hal->dev, false);
}
#endif
@ -273,7 +273,7 @@ esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave
#if SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
i2c_ll_slave_enable_scl_stretch(hal->dev, slave_config->flags.stretch_en);
#endif
i2c_ll_slave_tx_auto_start_en(hal->dev, true);
i2c_ll_slave_enable_auto_start(hal->dev, true);
i2c_ll_update(hal->dev);
portEXIT_CRITICAL(&i2c_slave->base->spinlock);
@ -386,7 +386,7 @@ esp_err_t i2c_slave_read_ram(i2c_slave_dev_handle_t i2c_slave, uint8_t ram_offse
portEXIT_CRITICAL(&i2c_slave->base->spinlock);
return ESP_ERR_INVALID_SIZE;
}
i2c_ll_read_by_nonfifo(hal->dev, ram_offset, data, fifo_size);
i2c_ll_read_rx_by_nonfifo(hal->dev, ram_offset, data, fifo_size);
portEXIT_CRITICAL(&i2c_slave->base->spinlock);
return ESP_OK;
@ -407,7 +407,7 @@ esp_err_t i2c_slave_write_ram(i2c_slave_dev_handle_t i2c_slave, uint8_t ram_offs
ESP_EARLY_LOGE(TAG, "No extra fifo to fill your buffer, please split your buffer");
return ESP_ERR_INVALID_SIZE;
}
i2c_ll_write_by_nonfifo(hal->dev, ram_offset, data, size);
i2c_ll_write_tx_by_nonfifo(hal->dev, ram_offset, data, size);
xSemaphoreGive(i2c_slave->slv_tx_mux);
return ESP_OK;
}

2
components/esp_driver_i2c/i2c_slave_v2.c
View File

@ -290,7 +290,7 @@ esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave
portENTER_CRITICAL(&i2c_slave->base->spinlock);
i2c_hal_slave_init(hal);
i2c_ll_slave_set_fifo_mode(hal->dev, true);
i2c_ll_enable_fifo_mode(hal->dev, true);
i2c_ll_set_slave_addr(hal->dev, slave_config->slave_addr, false);
i2c_ll_set_tout(hal->dev, I2C_LL_MAX_TIMEOUT);

11
components/hal/esp32/include/hal/i2c_ll.h
View File

@ -280,7 +280,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
*
* @return None
*/
static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
{
hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
}
@ -299,7 +299,7 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
}
/**
* @brief Configure I2C slave broadcasting mode.
* @brief Enable the I2C slave to respond to broadcast address
*
* @param hw Beginning address of the peripheral registers
* @param broadcast_en Set true to enable broadcast, else, set it false
@ -509,7 +509,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
* @return None
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_start_trans(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
@ -708,7 +708,6 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
ctrl_reg.sda_force_out = 1;
ctrl_reg.scl_force_out = 1;
hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0;
}
/**
@ -770,12 +769,12 @@ static inline void i2c_ll_reset_register(int i2c_port)
#define i2c_ll_reset_register(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; i2c_ll_reset_register(__VA_ARGS__);} while(0)
/**
* @brief Set whether slave should auto start, or only start with start signal from master
* @brief Enable I2C slave to automatically send data when addressed by the master
*
* @param hw Beginning address of the peripheral registers
* @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
*/
static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
static inline void i2c_ll_slave_enable_auto_start(i2c_dev_t *hw, bool slv_ex_auto_en)
{
;// ESP32 do not support
}

17
components/hal/esp32c2/include/hal/i2c_ll.h
View File

@ -76,7 +76,7 @@ typedef enum {
*/
static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2c_hal_clk_config_t *clk_cal)
{
uint32_t clkm_div = source_clk / (bus_freq * 1024) +1;
uint32_t clkm_div = source_clk / (bus_freq * 1024) + 1;
uint32_t sclk_freq = source_clk / clkm_div;
uint32_t half_cycle = sclk_freq / bus_freq / 2;
//SCL
@ -85,7 +85,7 @@ static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_f
// default, scl_wait_high < scl_high
// Make 80KHz as a boundary here, because when working at lower frequency, too much scl_wait_high will faster the frequency
// according to some hardware behaviors.
clk_cal->scl_wait_high = (bus_freq >= 80*1000) ? (half_cycle / 2 - 2) : (half_cycle / 4);
clk_cal->scl_wait_high = (bus_freq >= 80 * 1000) ? (half_cycle / 2 - 2) : (half_cycle / 4);
clk_cal->scl_high = half_cycle - clk_cal->scl_wait_high;
clk_cal->sda_hold = half_cycle / 4;
clk_cal->sda_sample = half_cycle / 2;
@ -326,7 +326,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
*
* @return None
*/
static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
{
hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
}
@ -414,6 +414,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
*/
static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->fifo_conf.txfifo_wm_thrhd = empty_thr;
}
@ -427,6 +428,8 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
*/
static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->ctr.rx_full_ack_level = 0;
hw->fifo_conf.rxfifo_wm_thrhd = full_thr;
}
@ -543,7 +546,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
* @return None
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_start_trans(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
@ -590,8 +593,8 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
__attribute__((always_inline))
static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i< len; i++) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]);
for (int i = 0; i < len; i++) {
hw->data.val = ptr[i];
}
}
@ -607,7 +610,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_
__attribute__((always_inline))
static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
{
for(int i = 0; i < len; i++) {
for (int i = 0; i < len; i++) {
ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->data, fifo_rdata);
}
}

29
components/hal/esp32c3/include/hal/i2c_ll.h
View File

@ -342,7 +342,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
*
* @return None
*/
static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
{
hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
}
@ -361,7 +361,7 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
}
/**
* @brief Configure I2C slave broadcasting mode.
* @brief Enable the I2C slave to respond to broadcast address
*
* @param hw Beginning address of the peripheral registers
* @param broadcast_en Set true to enable broadcast, else, set it false
@ -495,6 +495,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
*/
static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->fifo_conf.tx_fifo_wm_thrhd = empty_thr;
}
@ -509,6 +510,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->ctr.rx_full_ack_level = 0;
hw->fifo_conf.rx_fifo_wm_thrhd = full_thr;
}
@ -625,7 +627,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
* @return None
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_start_trans(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
@ -673,7 +675,7 @@ __attribute__((always_inline))
static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo_data, data, ptr[i]);
hw->fifo_data.val = ptr[i];
}
}
@ -695,14 +697,14 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
}
/**
* @brief Write the I2C hardware txFIFO
* @brief Write to the TX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
static inline void i2c_ll_write_tx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
hw->txfifo_mem[i + ram_offset] = ptr[i];
@ -710,14 +712,14 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
}
/**
* @brief Read the I2C hardware ram
* @brief Read from the RX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs read
*/
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
static inline void i2c_ll_read_rx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
ptr[i] = hw->rxfifo_mem[i + ram_offset];
@ -725,14 +727,16 @@ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uin
}
/**
* @brief Get access to I2C RAM address directly
* @brief Enable I2C slave dual addressing mode
*
* @note When enable the dual addressing mode, I2C RAM must be accessed in non-FIFO mode
*
* @param hw Beginning address of the peripheral registers
* @param addr_wr_en Enable I2C ram address read and write
*
* @return None
*/
static inline void i2c_ll_enable_mem_access_nonfifo(i2c_dev_t *hw, bool addr_wr_en)
static inline void i2c_ll_slave_enable_dual_addressing_mode(i2c_dev_t *hw, bool addr_wr_en)
{
hw->fifo_conf.fifo_addr_cfg_en = addr_wr_en;
}
@ -874,16 +878,15 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
ctrl_reg.sda_force_out = 1;
ctrl_reg.scl_force_out = 1;
hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0;
}
/**
* @brief Set whether slave should auto start, or only start with start signal from master
* @brief Enable I2C slave to automatically send data when addressed by the master
*
* @param hw Beginning address of the peripheral registers
* @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
*/
static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
static inline void i2c_ll_slave_enable_auto_start(i2c_dev_t *hw, bool slv_ex_auto_en)
{
hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en;
}

29
components/hal/esp32c5/include/hal/i2c_ll.h
View File

@ -299,7 +299,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
*
* @return None
*/
static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
{
hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
}
@ -318,7 +318,7 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
}
/**
* @brief Configure I2C slave broadcasting mode.
* @brief Enable the I2C slave to respond to broadcast address
*
* @param hw Beginning address of the peripheral registers
* @param broadcast_en Set true to enable broadcast, else, set it false
@ -452,6 +452,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
*/
static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->fifo_conf.txfifo_wm_thrhd = empty_thr;
}
@ -466,6 +467,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->ctr.rx_full_ack_level = 0;
hw->fifo_conf.rxfifo_wm_thrhd = full_thr;
}
@ -582,7 +584,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
* @return None
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_start_trans(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
@ -630,7 +632,7 @@ __attribute__((always_inline))
static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]);
hw->data.val = ptr[i];
}
}
@ -652,14 +654,14 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
}
/**
* @brief Write the I2C hardware txFIFO
* @brief Write to the TX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
static inline void i2c_ll_write_tx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
hw->txfifo_mem[i + ram_offset] = ptr[i];
@ -667,14 +669,14 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
}
/**
* @brief Read the I2C hardware ram
* @brief Read from the RX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs read
*/
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
static inline void i2c_ll_read_rx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
ptr[i] = hw->rxfifo_mem[i + ram_offset];
@ -682,14 +684,16 @@ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uin
}
/**
* @brief Get access to I2C RAM address directly
* @brief Enable I2C slave dual addressing mode
*
* @note When enable the dual addressing mode, I2C RAM must be accessed in non-FIFO mode
*
* @param hw Beginning address of the peripheral registers
* @param addr_wr_en Enable I2C ram address read and write
*
* @return None
*/
static inline void i2c_ll_enable_mem_access_nonfifo(i2c_dev_t *hw, bool addr_wr_en)
static inline void i2c_ll_slave_enable_dual_addressing_mode(i2c_dev_t *hw, bool addr_wr_en)
{
hw->fifo_conf.fifo_addr_cfg_en = addr_wr_en;
}
@ -912,16 +916,15 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0;
}
/**
* @brief Set whether slave should auto start, or only start with start signal from master
* @brief Enable I2C slave to automatically send data when addressed by the master
*
* @param hw Beginning address of the peripheral registers
* @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
*/
static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
static inline void i2c_ll_slave_enable_auto_start(i2c_dev_t *hw, bool slv_ex_auto_en)
{
hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en;
}

29
components/hal/esp32c6/include/hal/i2c_ll.h
View File

@ -303,7 +303,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
*
* @return None
*/
static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
{
hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
}
@ -322,7 +322,7 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
}
/**
* @brief Configure I2C slave broadcasting mode.
* @brief Enable the I2C slave to respond to broadcast address
*
* @param hw Beginning address of the peripheral registers
* @param broadcast_en Set true to enable broadcast, else, set it false
@ -456,6 +456,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
*/
static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->fifo_conf.txfifo_wm_thrhd = empty_thr;
}
@ -470,6 +471,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->ctr.rx_full_ack_level = 0;
hw->fifo_conf.rxfifo_wm_thrhd = full_thr;
}
@ -586,7 +588,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
* @return None
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_start_trans(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
@ -634,7 +636,7 @@ __attribute__((always_inline))
static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]);
hw->data.val = ptr[i];
}
}
@ -656,14 +658,14 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
}
/**
* @brief Write the I2C hardware txFIFO
* @brief Write to the TX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
static inline void i2c_ll_write_tx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
hw->txfifo_mem[i + ram_offset] = ptr[i];
@ -671,14 +673,14 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
}
/**
* @brief Read the I2C hardware ram
* @brief Read from the RX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs read
*/
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
static inline void i2c_ll_read_rx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
ptr[i] = hw->rxfifo_mem[i + ram_offset];
@ -686,14 +688,16 @@ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uin
}
/**
* @brief Get access to I2C RAM address directly
* @brief Enable I2C slave dual addressing mode
*
* @note When enable the dual addressing mode, I2C RAM must be accessed in non-FIFO mode
*
* @param hw Beginning address of the peripheral registers
* @param addr_wr_en Enable I2C ram address read and write
*
* @return None
*/
static inline void i2c_ll_enable_mem_access_nonfifo(i2c_dev_t *hw, bool addr_wr_en)
static inline void i2c_ll_slave_enable_dual_addressing_mode(i2c_dev_t *hw, bool addr_wr_en)
{
hw->fifo_conf.fifo_addr_cfg_en = addr_wr_en;
}
@ -914,16 +918,15 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0;
}
/**
* @brief Set whether slave should auto start, or only start with start signal from master
* @brief Enable I2C slave to automatically send data when addressed by the master
*
* @param hw Beginning address of the peripheral registers
* @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
*/
static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
static inline void i2c_ll_slave_enable_auto_start(i2c_dev_t *hw, bool slv_ex_auto_en)
{
hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en;
}

29
components/hal/esp32c61/include/hal/i2c_ll.h
View File

@ -293,7 +293,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
*
* @return None
*/
static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
{
hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
}
@ -312,7 +312,7 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
}
/**
* @brief Configure I2C slave broadcasting mode.
* @brief Enable the I2C slave to respond to broadcast address
*
* @param hw Beginning address of the peripheral registers
* @param broadcast_en Set true to enable broadcast, else, set it false
@ -446,6 +446,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
*/
static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->fifo_conf.txfifo_wm_thrhd = empty_thr;
}
@ -460,6 +461,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->ctr.rx_full_ack_level = 0;
hw->fifo_conf.rxfifo_wm_thrhd = full_thr;
}
@ -576,7 +578,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
* @return None
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_start_trans(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
@ -624,7 +626,7 @@ __attribute__((always_inline))
static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]);
hw->data.val = ptr[i];
}
}
@ -646,14 +648,14 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
}
/**
* @brief Write the I2C hardware txFIFO
* @brief Write to the TX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
static inline void i2c_ll_write_tx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
hw->txfifo_mem[i + ram_offset] = ptr[i];
@ -661,14 +663,14 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
}
/**
* @brief Read the I2C hardware ram
* @brief Read from the RX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs read
*/
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
static inline void i2c_ll_read_rx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
ptr[i] = hw->rxfifo_mem[i + ram_offset];
@ -676,14 +678,16 @@ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uin
}
/**
* @brief Get access to I2C RAM address directly
* @brief Enable I2C slave dual addressing mode
*
* @note When enable the dual addressing mode, I2C RAM must be accessed in non-FIFO mode
*
* @param hw Beginning address of the peripheral registers
* @param addr_wr_en Enable I2C ram address read and write
*
* @return None
*/
static inline void i2c_ll_enable_mem_access_nonfifo(i2c_dev_t *hw, bool addr_wr_en)
static inline void i2c_ll_slave_enable_dual_addressing_mode(i2c_dev_t *hw, bool addr_wr_en)
{
hw->fifo_conf.fifo_addr_cfg_en = addr_wr_en;
}
@ -838,16 +842,15 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0;
}
/**
* @brief Set whether slave should auto start, or only start with start signal from master
* @brief Enable I2C slave to automatically send data when addressed by the master
*
* @param hw Beginning address of the peripheral registers
* @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
*/
static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
static inline void i2c_ll_slave_enable_auto_start(i2c_dev_t *hw, bool slv_ex_auto_en)
{
hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en;
}

29
components/hal/esp32h2/include/hal/i2c_ll.h
View File

@ -289,7 +289,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
*
* @return None
*/
static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
{
hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
}
@ -308,7 +308,7 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
}
/**
* @brief Configure I2C slave broadcasting mode.
* @brief Enable the I2C slave to respond to broadcast address
*
* @param hw Beginning address of the peripheral registers
* @param broadcast_en Set true to enable broadcast, else, set it false
@ -442,6 +442,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
*/
static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->fifo_conf.txfifo_wm_thrhd = empty_thr;
}
@ -456,6 +457,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->ctr.rx_full_ack_level = 0;
hw->fifo_conf.rxfifo_wm_thrhd = full_thr;
}
@ -572,7 +574,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
* @return None
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_start_trans(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
@ -620,7 +622,7 @@ __attribute__((always_inline))
static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]);
hw->data.val = ptr[i];
}
}
@ -642,14 +644,14 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
}
/**
* @brief Write the I2C hardware txFIFO
* @brief Write to the TX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
static inline void i2c_ll_write_tx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
hw->txfifo_mem[i + ram_offset] = ptr[i];
@ -657,14 +659,14 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
}
/**
* @brief Read the I2C hardware ram
* @brief Read from the RX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs read
*/
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
static inline void i2c_ll_read_rx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
ptr[i] = hw->rxfifo_mem[i + ram_offset];
@ -672,14 +674,16 @@ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uin
}
/**
* @brief Get access to I2C RAM address directly
* @brief Enable I2C slave dual addressing mode
*
* @note When enable the dual addressing mode, I2C RAM must be accessed in non-FIFO mode
*
* @param hw Beginning address of the peripheral registers
* @param addr_wr_en Enable I2C ram address read and write
*
* @return None
*/
static inline void i2c_ll_enable_mem_access_nonfifo(i2c_dev_t *hw, bool addr_wr_en)
static inline void i2c_ll_slave_enable_dual_addressing_mode(i2c_dev_t *hw, bool addr_wr_en)
{
hw->fifo_conf.fifo_addr_cfg_en = addr_wr_en;
}
@ -821,16 +825,15 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0;
}
/**
* @brief Set whether slave should auto start, or only start with start signal from master
* @brief Enable I2C slave to automatically send data when addressed by the master
*
* @param hw Beginning address of the peripheral registers
* @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
*/
static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
static inline void i2c_ll_slave_enable_auto_start(i2c_dev_t *hw, bool slv_ex_auto_en)
{
hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en;
}

35
components/hal/esp32p4/include/hal/i2c_ll.h
View File

@ -67,12 +67,6 @@ typedef enum {
I2C_INTR_UNMATCH = (1 << 18),
} i2c_ll_slave_intr_t;
typedef enum {
I2C_LL_STRETCH_REASON_MASTER_START = 0,
I2C_LL_STRETCH_REASON_TX_EMPTY = 1,
I2C_LL_STRETCH_REASON_RX_FULL = 2,
} i2c_ll_stretch_cause_t;
// Get the I2C hardware instance
#define I2C_LL_GET_HW(i2c_num) (((i2c_num) == I2C_NUM_0) ? (&I2C0) : (((i2c_num) == I2C_NUM_1) ? (&I2C1) : (&LP_I2C)))
#define I2C_LL_MASTER_EVENT_INTR (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
@ -324,7 +318,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
*
* @return None
*/
static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
{
hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
}
@ -343,7 +337,7 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
}
/**
* @brief Configure I2C slave broadcasting mode.
* @brief Enable the I2C slave to respond to broadcast address
*
* @param hw Beginning address of the peripheral registers
* @param broadcast_en Set true to enable broadcast, else, set it false
@ -477,6 +471,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
*/
static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->fifo_conf.txfifo_wm_thrhd = empty_thr;
}
@ -491,6 +486,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->ctr.rx_full_ack_level = 0;
hw->fifo_conf.rxfifo_wm_thrhd = full_thr;
}
@ -607,7 +603,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
* @return None
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_start_trans(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
@ -655,7 +651,7 @@ __attribute__((always_inline))
static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]);
hw->data.val = ptr[i];
}
}
@ -677,14 +673,14 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
}
/**
* @brief Write the I2C hardware txFIFO
* @brief Write to the TX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
static inline void i2c_ll_write_tx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
hw->txfifo_mem[i + ram_offset] = ptr[i];
@ -692,14 +688,14 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
}
/**
* @brief Read the I2C hardware ram
* @brief Read from the RX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs read
*/
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
static inline void i2c_ll_read_rx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
ptr[i] = hw->rxfifo_mem[i + ram_offset];
@ -707,14 +703,16 @@ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uin
}
/**
* @brief Get access to I2C RAM address directly
* @brief Enable I2C slave dual addressing mode
*
* @note When enable the dual addressing mode, I2C RAM must be accessed in non-FIFO mode
*
* @param hw Beginning address of the peripheral registers
* @param addr_wr_en Enable I2C ram address read and write
*
* @return None
*/
static inline void i2c_ll_enable_mem_access_nonfifo(i2c_dev_t *hw, bool addr_wr_en)
static inline void i2c_ll_slave_enable_dual_addressing_mode(i2c_dev_t *hw, bool addr_wr_en)
{
hw->fifo_conf.fifo_addr_cfg_en = addr_wr_en;
}
@ -951,16 +949,15 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0;
}
/**
* @brief Set whether slave should auto start, or only start with start signal from master
* @brief Enable I2C slave to automatically send data when addressed by the master
*
* @param hw Beginning address of the peripheral registers
* @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
*/
static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
static inline void i2c_ll_slave_enable_auto_start(i2c_dev_t *hw, bool slv_ex_auto_en)
{
hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en;
}

28
components/hal/esp32s2/include/hal/i2c_ll.h
View File

@ -269,7 +269,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
*
* @return None
*/
static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
{
hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
}
@ -289,7 +289,7 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
}
/**
* @brief Configure I2C slave broadcasting mode.
* @brief Enable the I2C slave to respond to broadcast address
*
* @param hw Beginning address of the peripheral registers
* @param broadcast_en Set true to enable broadcast, else, set it false
@ -379,7 +379,7 @@ static inline void i2c_ll_master_write_cmd_reg(i2c_dev_t *hw, i2c_ll_hw_cmd_t cm
static inline void i2c_ll_master_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold)
{
hw->scl_rstart_setup.time = start_setup;
hw->scl_start_hold.time = start_hold-1;
hw->scl_start_hold.time = start_hold - 1;
}
/**
@ -422,6 +422,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
*/
static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->fifo_conf.tx_fifo_wm_thrhd = empty_thr;
}
@ -436,6 +437,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->ctr.rx_full_ack_level = 0;
hw->fifo_conf.rx_fifo_wm_thrhd = full_thr;
}
@ -552,7 +554,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
* @return None
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_start_trans(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
@ -569,7 +571,7 @@ static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int *hold_time)
{
*setup_time = hw->scl_rstart_setup.time;
*hold_time = hw->scl_start_hold.time+1;
*hold_time = hw->scl_start_hold.time + 1;
}
/**
@ -600,7 +602,7 @@ __attribute__((always_inline))
static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
{
uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
for(int i = 0; i < len; i++) {
for (int i = 0; i < len; i++) {
WRITE_PERI_REG(fifo_addr, ptr[i]);
}
}
@ -618,7 +620,7 @@ __attribute__((always_inline))
static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
{
uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
for(int i = 0; i < len; i++) {
for (int i = 0; i < len; i++) {
ptr[i] = READ_PERI_REG(fifo_addr);
}
}
@ -634,7 +636,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
*/
static inline void i2c_ll_master_set_filter(i2c_dev_t *hw, uint8_t filter_num)
{
if(filter_num > 0) {
if (filter_num > 0) {
hw->scl_filter_cfg.thres = filter_num;
hw->sda_filter_cfg.thres = filter_num;
hw->scl_filter_cfg.en = 1;
@ -774,8 +776,6 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
ctrl_reg.sda_force_out = 1;
ctrl_reg.scl_force_out = 1;
hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0;
hw->scl_stretch_conf.slave_scl_stretch_en = 0;
}
/**
@ -837,12 +837,12 @@ static inline void i2c_ll_reset_register(int i2c_port)
#define i2c_ll_reset_register(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; i2c_ll_reset_register(__VA_ARGS__);} while(0)
/**
* @brief Set whether slave should auto start, or only start with start signal from master
* @brief Enable I2C slave to automatically send data when addressed by the master
*
* @param hw Beginning address of the peripheral registers
* @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
*/
static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
static inline void i2c_ll_slave_enable_auto_start(i2c_dev_t *hw, bool slv_ex_auto_en)
{
;// ESP32-S2 do not support
}
@ -1157,8 +1157,8 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
*/
static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int low_period)
{
hw->scl_low_period.period = low_period-1;
hw->scl_high_period.period = hight_period/2+2;
hw->scl_low_period.period = low_period - 1;
hw->scl_high_period.period = hight_period / 2 + 2;
hw->scl_high_period.scl_wait_high_period = hight_period - hw->scl_high_period.period;
}

29
components/hal/esp32s3/include/hal/i2c_ll.h
View File

@ -350,7 +350,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
*
* @return None
*/
static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
{
hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
}
@ -369,7 +369,7 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
}
/**
* @brief Configure I2C slave broadcasting mode.
* @brief Enable the I2C slave to respond to broadcast address
*
* @param hw Beginning address of the peripheral registers
* @param broadcast_en Set true to enable broadcast, else, set it false
@ -503,6 +503,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
*/
static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->fifo_conf.txfifo_wm_thrhd = empty_thr;
}
@ -517,6 +518,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->ctr.rx_full_ack_level = 0;
hw->fifo_conf.rxfifo_wm_thrhd = full_thr;
}
@ -633,7 +635,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
* @return None
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_start_trans(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
@ -681,7 +683,7 @@ __attribute__((always_inline))
static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]);
hw->data.val = ptr[i];
}
}
@ -703,14 +705,14 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
}
/**
* @brief Write the I2C hardware txFIFO
* @brief Write to the TX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
static inline void i2c_ll_write_tx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
hw->txfifo_mem[i + ram_offset] = ptr[i];
@ -718,14 +720,14 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
}
/**
* @brief Read the I2C hardware ram
* @brief Read from the RX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs read
*/
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
static inline void i2c_ll_read_rx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
ptr[i] = hw->rxfifo_mem[i + ram_offset];
@ -733,14 +735,16 @@ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uin
}
/**
* @brief Get access to I2C RAM address directly
* @brief Enable I2C slave dual addressing mode
*
* @note When enable the dual addressing mode, I2C RAM must be accessed in non-FIFO mode
*
* @param hw Beginning address of the peripheral registers
* @param addr_wr_en Enable I2C ram address read and write
*
* @return None
*/
static inline void i2c_ll_enable_mem_access_nonfifo(i2c_dev_t *hw, bool addr_wr_en)
static inline void i2c_ll_slave_enable_dual_addressing_mode(i2c_dev_t *hw, bool addr_wr_en)
{
hw->fifo_conf.fifo_addr_cfg_en = addr_wr_en;
}
@ -878,16 +882,15 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
ctrl_reg.sda_force_out = 1;
ctrl_reg.scl_force_out = 1;
hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0;
}
/**
* @brief Set whether slave should auto start, or only start with start signal from master
* @brief Enable I2C slave to automatically send data when addressed by the master
*
* @param hw Beginning address of the peripheral registers
* @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
*/
static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
static inline void i2c_ll_slave_enable_auto_start(i2c_dev_t *hw, bool slv_ex_auto_en)
{
hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en;
}

2
components/hal/i2c_hal.c
View File

@ -93,5 +93,5 @@ void i2c_hal_set_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t *
void i2c_hal_master_trans_start(i2c_hal_context_t *hal)
{
i2c_ll_update(hal->dev);
i2c_ll_master_trans_start(hal->dev);
i2c_ll_start_trans(hal->dev);
}

10
components/hal/test_apps/hal_i2c/components/hal_i2c/hal_i2c.c
View File

@ -221,7 +221,7 @@ esp_err_t hal_i2c_write(i2c_port_t port_num, uint16_t addr, const uint8_t *txdat
i2c_format_cmd(port_num, cmd_idx++, I2C_LL_CMD_WRITE, ACK_VALUE, 0, NOT_CHECK_ACK_VALUE, tx_len_tmp);
i2c_format_cmd(port_num, cmd_idx++, I2C_LL_CMD_END, ACK_VALUE, 0, NOT_CHECK_ACK_VALUE, 0);
i2c_ll_update(dev);
i2c_ll_master_trans_start(dev);
i2c_ll_start_trans(dev);
ESP_RETURN_ON_ERROR(i2c_wait_done(port_num, cmd_idx - 1, timeout_ms), TAG, "wait done failed");
cmd_idx = 0;
txdata += tx_len_tmp;
@ -230,7 +230,7 @@ esp_err_t hal_i2c_write(i2c_port_t port_num, uint16_t addr, const uint8_t *txdat
i2c_format_cmd(port_num, cmd_idx++, I2C_LL_CMD_STOP, ACK_VALUE, 0, NOT_CHECK_ACK_VALUE, 0);
i2c_ll_update(dev);
i2c_ll_master_trans_start(dev);
i2c_ll_start_trans(dev);
ESP_RETURN_ON_ERROR(i2c_wait_done(port_num, cmd_idx - 1, timeout_ms), TAG, "wait done failed");
return ESP_OK;
}
@ -270,7 +270,7 @@ esp_err_t hal_i2c_read(i2c_port_t port_num, uint16_t addr, uint8_t *rxdata, uint
}
i2c_ll_update(dev);
i2c_ll_master_trans_start(dev);
i2c_ll_start_trans(dev);
ESP_RETURN_ON_ERROR(i2c_wait_done(port_num, cmd_idx - 1, timeout_ms), TAG, "wait done failed");
cmd_idx = 0;
i2c_ll_read_rxfifo(dev, &rxdata[data_idx], 1);
@ -309,7 +309,7 @@ esp_err_t hal_i2c_write_read(i2c_port_t port_num, uint16_t addr, const uint8_t *
i2c_format_cmd(port_num, cmd_idx++, I2C_LL_CMD_END, ACK_VALUE, 0, NOT_CHECK_ACK_VALUE, 0);
/* Initiate I2C transfer */
i2c_ll_update(dev);
i2c_ll_master_trans_start(dev);
i2c_ll_start_trans(dev);
ESP_RETURN_ON_ERROR(i2c_wait_done(port_num, cmd_idx - 1, timeout_ms), TAG, "wait done failed");
cmd_idx = 0;
txdata += tx_len_tmp;
@ -341,7 +341,7 @@ esp_err_t hal_i2c_write_read(i2c_port_t port_num, uint16_t addr, const uint8_t *
}
i2c_ll_update(dev);
i2c_ll_master_trans_start(dev);
i2c_ll_start_trans(dev);
ESP_RETURN_ON_ERROR(i2c_wait_done(port_num, cmd_idx - 1, timeout_ms), TAG, "wait done failed");
i2c_ll_read_rxfifo(dev, &rxdata[data_idx], tmp_rx_length);
cmd_idx = 0;

8
components/ulp/lp_core/lp_core/lp_core_i2c.c
View File

@ -215,7 +215,7 @@ esp_err_t lp_core_i2c_master_read_from_device(i2c_port_t lp_i2c_num, uint16_t de
/* Initiate I2C transfer */
i2c_ll_update(dev);
i2c_ll_master_trans_start(dev);
i2c_ll_start_trans(dev);
/* Wait for the transfer to complete */
ret = lp_core_i2c_wait_for_interrupt(intr_mask, ticks_to_wait);
@ -306,7 +306,7 @@ esp_err_t lp_core_i2c_master_write_to_device(i2c_port_t lp_i2c_num, uint16_t dev
/* Initiate I2C transfer */
i2c_ll_update(dev);
i2c_ll_master_trans_start(dev);
i2c_ll_start_trans(dev);
/* Wait for the transfer to complete */
ret = lp_core_i2c_wait_for_interrupt(intr_mask, ticks_to_wait);
@ -393,7 +393,7 @@ esp_err_t lp_core_i2c_master_write_read_device(i2c_port_t lp_i2c_num, uint16_t d
/* Initiate I2C transfer */
i2c_ll_update(dev);
i2c_ll_master_trans_start(dev);
i2c_ll_start_trans(dev);
/* Wait for the transfer to complete */
ret = lp_core_i2c_wait_for_interrupt(intr_mask, ticks_to_wait);
@ -462,7 +462,7 @@ esp_err_t lp_core_i2c_master_write_read_device(i2c_port_t lp_i2c_num, uint16_t d
/* Initiate I2C transfer */
i2c_ll_update(dev);
i2c_ll_master_trans_start(dev);
i2c_ll_start_trans(dev);
/* Wait for the transfer to complete */
ret = lp_core_i2c_wait_for_interrupt(intr_mask, ticks_to_wait);