mirror of
https://github.com/espressif/esp-idf
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feat(efuse): Adds efuse ADC calib data for ESP32-C5
This commit is contained in:
Konstantin Kondrashov
parent
b4ebb04184
commit
427e8e5fe4
@ -9,7 +9,7 @@
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#include <assert.h>
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#include "esp_efuse_table.h"
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// md5_digest_table 13b0a8106fd483a0fcfa8b2f7388a95f
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// md5_digest_table b26e7466c400977081a142076ef1a5bb
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -287,14 +287,102 @@ static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2,
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};
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static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_HP_DBIAS,
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};
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static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_LP_DBIAS,
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};
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static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBG[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBG,
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};
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static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBIAS[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBIAS,
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};
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static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBG[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBG,
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};
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static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBIAS,
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};
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static const esp_efuse_desc_t WR_DIS_LP_HP_DBIAS_VOL_GAP[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of LP_HP_DBIAS_VOL_GAP,
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};
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static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID,
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};
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static const esp_efuse_desc_t WR_DIS_TEMPERATURE_SENSOR[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMPERATURE_SENSOR,
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};
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static const esp_efuse_desc_t WR_DIS_OCODE[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN0,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN1,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN2,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN3,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF,
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};
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static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
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{EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
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};
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@ -648,14 +736,102 @@ static const esp_efuse_desc_t TRIM_P_BIAS[] = {
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{EFUSE_BLK1, 101, 5}, // [] PADC CAL P bias,
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};
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static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = {
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{EFUSE_BLK1, 106, 4}, // [] Active HP DBIAS of fixed voltage,
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};
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static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = {
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{EFUSE_BLK1, 110, 4}, // [] Active LP DBIAS of fixed voltage,
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};
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static const esp_efuse_desc_t LSLP_HP_DBG[] = {
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{EFUSE_BLK1, 114, 2}, // [] LSLP HP DBG of fixed voltage,
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};
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static const esp_efuse_desc_t LSLP_HP_DBIAS[] = {
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{EFUSE_BLK1, 116, 4}, // [] LSLP HP DBIAS of fixed voltage,
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};
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static const esp_efuse_desc_t DSLP_LP_DBG[] = {
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{EFUSE_BLK1, 120, 4}, // [] DSLP LP DBG of fixed voltage,
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};
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static const esp_efuse_desc_t DSLP_LP_DBIAS[] = {
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{EFUSE_BLK1, 124, 5}, // [] DSLP LP DBIAS of fixed voltage,
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};
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static const esp_efuse_desc_t LP_HP_DBIAS_VOL_GAP[] = {
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{EFUSE_BLK1, 129, 5}, // [] DBIAS gap between LP and HP,
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};
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static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
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{EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID,
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};
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static const esp_efuse_desc_t TEMPERATURE_SENSOR[] = {
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{EFUSE_BLK2, 128, 9}, // [] Temperature calibration data,
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};
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static const esp_efuse_desc_t OCODE[] = {
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{EFUSE_BLK2, 137, 8}, // [] ADC OCode,
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};
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static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = {
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{EFUSE_BLK2, 145, 10}, // [] Average initcode of ADC1 atten0,
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};
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static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = {
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{EFUSE_BLK2, 155, 10}, // [] Average initcode of ADC1 atten0,
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};
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static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = {
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{EFUSE_BLK2, 165, 10}, // [] Average initcode of ADC1 atten0,
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};
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static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = {
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{EFUSE_BLK2, 175, 10}, // [] Average initcode of ADC1 atten0,
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};
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static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = {
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{EFUSE_BLK2, 185, 10}, // [] HI DOUT of ADC1 atten0,
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};
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static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = {
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{EFUSE_BLK2, 195, 10}, // [] HI DOUT of ADC1 atten1,
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};
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static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = {
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{EFUSE_BLK2, 205, 10}, // [] HI DOUT of ADC1 atten2,
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};
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static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = {
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{EFUSE_BLK2, 215, 10}, // [] HI DOUT of ADC1 atten3,
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};
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static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK2, 225, 4}, // [] Gap between ADC1 CH0 and average initcode,
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};
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static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK2, 229, 4}, // [] Gap between ADC1 CH1 and average initcode,
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};
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static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK2, 233, 4}, // [] Gap between ADC1 CH2 and average initcode,
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};
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static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK2, 237, 4}, // [] Gap between ADC1 CH3 and average initcode,
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};
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static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK2, 241, 4}, // [] Gap between ADC1 CH4 and average initcode,
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};
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static const esp_efuse_desc_t ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK2, 245, 4}, // [] Gap between ADC1 CH5 and average initcode,
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};
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static const esp_efuse_desc_t USER_DATA[] = {
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{EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data,
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};
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@ -1036,16 +1212,126 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = {
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&WR_DIS_ACTIVE_HP_DBIAS[0], // [] wr_dis of ACTIVE_HP_DBIAS
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = {
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&WR_DIS_ACTIVE_LP_DBIAS[0], // [] wr_dis of ACTIVE_LP_DBIAS
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[] = {
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&WR_DIS_LSLP_HP_DBG[0], // [] wr_dis of LSLP_HP_DBG
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[] = {
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&WR_DIS_LSLP_HP_DBIAS[0], // [] wr_dis of LSLP_HP_DBIAS
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[] = {
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&WR_DIS_DSLP_LP_DBG[0], // [] wr_dis of DSLP_LP_DBG
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = {
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&WR_DIS_DSLP_LP_DBIAS[0], // [] wr_dis of DSLP_LP_DBIAS
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[] = {
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&WR_DIS_LP_HP_DBIAS_VOL_GAP[0], // [] wr_dis of LP_HP_DBIAS_VOL_GAP
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
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&WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[] = {
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&WR_DIS_TEMPERATURE_SENSOR[0], // [] wr_dis of TEMPERATURE_SENSOR
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = {
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&WR_DIS_OCODE[0], // [] wr_dis of OCODE
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
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&WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
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&WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
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&WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
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&WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
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&WR_DIS_ADC1_HI_DOUT_ATTEN0[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN0
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
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&WR_DIS_ADC1_HI_DOUT_ATTEN1[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
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&WR_DIS_ADC1_HI_DOUT_ATTEN2[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
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&WR_DIS_ADC1_HI_DOUT_ATTEN3[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
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&WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
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&WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
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&WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
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&WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
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&WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
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&WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
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&WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
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NULL
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@ -1486,16 +1772,126 @@ const esp_efuse_desc_t* ESP_EFUSE_TRIM_P_BIAS[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = {
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&ACTIVE_HP_DBIAS[0], // [] Active HP DBIAS of fixed voltage
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = {
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&ACTIVE_LP_DBIAS[0], // [] Active LP DBIAS of fixed voltage
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[] = {
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&LSLP_HP_DBG[0], // [] LSLP HP DBG of fixed voltage
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[] = {
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&LSLP_HP_DBIAS[0], // [] LSLP HP DBIAS of fixed voltage
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NULL
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};
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|
||||
const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[] = {
|
||||
&DSLP_LP_DBG[0], // [] DSLP LP DBG of fixed voltage
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = {
|
||||
&DSLP_LP_DBIAS[0], // [] DSLP LP DBIAS of fixed voltage
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[] = {
|
||||
&LP_HP_DBIAS_VOL_GAP[0], // [] DBIAS gap between LP and HP
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
|
||||
&OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[] = {
|
||||
&TEMPERATURE_SENSOR[0], // [] Temperature calibration data
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
|
||||
&OCODE[0], // [] ADC OCode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = {
|
||||
&ADC1_AVE_INITCODE_ATTEN0[0], // [] Average initcode of ADC1 atten0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = {
|
||||
&ADC1_AVE_INITCODE_ATTEN1[0], // [] Average initcode of ADC1 atten0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = {
|
||||
&ADC1_AVE_INITCODE_ATTEN2[0], // [] Average initcode of ADC1 atten0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = {
|
||||
&ADC1_AVE_INITCODE_ATTEN3[0], // [] Average initcode of ADC1 atten0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = {
|
||||
&ADC1_HI_DOUT_ATTEN0[0], // [] HI DOUT of ADC1 atten0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = {
|
||||
&ADC1_HI_DOUT_ATTEN1[0], // [] HI DOUT of ADC1 atten1
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = {
|
||||
&ADC1_HI_DOUT_ATTEN2[0], // [] HI DOUT of ADC1 atten2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = {
|
||||
&ADC1_HI_DOUT_ATTEN3[0], // [] HI DOUT of ADC1 atten3
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH0 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH1 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH2 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH3 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH4 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH5_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH5 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
|
||||
&USER_DATA[0], // [BLOCK_USR_DATA] User data
|
||||
NULL
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: b09fa417de505238a601eddce188b696
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 287a0ed4951aba84b9571a5f31000275
|
||||
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
@ -79,8 +79,30 @@ WR_DIS.PA_TRIM_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis
|
||||
WR_DIS.TRIM_N_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of TRIM_N_BIAS
|
||||
WR_DIS.TRIM_P_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of TRIM_P_BIAS
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||
WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS
|
||||
WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS
|
||||
WR_DIS.LSLP_HP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBG
|
||||
WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS
|
||||
WR_DIS.DSLP_LP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBG
|
||||
WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS
|
||||
WR_DIS.LP_HP_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_HP_DBIAS_VOL_GAP
|
||||
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 21, 1, [] wr_dis of TEMPERATURE_SENSOR
|
||||
WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
|
||||
WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
@ -173,8 +195,30 @@ PKG_VERSION, EFUSE_BLK1, 90, 3, [] Packag
|
||||
PA_TRIM_VERSION, EFUSE_BLK1, 93, 3, [] PADC CAL PA trim version
|
||||
TRIM_N_BIAS, EFUSE_BLK1, 96, 5, [] PADC CAL N bias
|
||||
TRIM_P_BIAS, EFUSE_BLK1, 101, 5, [] PADC CAL P bias
|
||||
ACTIVE_HP_DBIAS, EFUSE_BLK1, 106, 4, [] Active HP DBIAS of fixed voltage
|
||||
ACTIVE_LP_DBIAS, EFUSE_BLK1, 110, 4, [] Active LP DBIAS of fixed voltage
|
||||
LSLP_HP_DBG, EFUSE_BLK1, 114, 2, [] LSLP HP DBG of fixed voltage
|
||||
LSLP_HP_DBIAS, EFUSE_BLK1, 116, 4, [] LSLP HP DBIAS of fixed voltage
|
||||
DSLP_LP_DBG, EFUSE_BLK1, 120, 4, [] DSLP LP DBG of fixed voltage
|
||||
DSLP_LP_DBIAS, EFUSE_BLK1, 124, 5, [] DSLP LP DBIAS of fixed voltage
|
||||
LP_HP_DBIAS_VOL_GAP, EFUSE_BLK1, 129, 5, [] DBIAS gap between LP and HP
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
TEMPERATURE_SENSOR, EFUSE_BLK2, 128, 9, [] Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode
|
||||
ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 145, 10, [] Average initcode of ADC1 atten0
|
||||
ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 155, 10, [] Average initcode of ADC1 atten0
|
||||
ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 165, 10, [] Average initcode of ADC1 atten0
|
||||
ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 175, 10, [] Average initcode of ADC1 atten0
|
||||
ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 185, 10, [] HI DOUT of ADC1 atten0
|
||||
ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 195, 10, [] HI DOUT of ADC1 atten1
|
||||
ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 205, 10, [] HI DOUT of ADC1 atten2
|
||||
ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 215, 10, [] HI DOUT of ADC1 atten3
|
||||
ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 225, 4, [] Gap between ADC1 CH0 and average initcode
|
||||
ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 229, 4, [] Gap between ADC1 CH1 and average initcode
|
||||
ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 233, 4, [] Gap between ADC1 CH2 and average initcode
|
||||
ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 237, 4, [] Gap between ADC1 CH3 and average initcode
|
||||
ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 241, 4, [] Gap between ADC1 CH4 and average initcode
|
||||
ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 245, 4, [] Gap between ADC1 CH5 and average initcode
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 13b0a8106fd483a0fcfa8b2f7388a95f
|
||||
// md5_digest_table b26e7466c400977081a142076ef1a5bb
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -92,8 +92,30 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PA_TRIM_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_N_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_P_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
@ -205,8 +227,30 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PA_TRIM_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TRIM_N_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TRIM_P_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
|
||||
@ -804,32 +804,74 @@ extern "C" {
|
||||
#define EFUSE_TRIM_P_BIAS_M (EFUSE_TRIM_P_BIAS_V << EFUSE_TRIM_P_BIAS_S)
|
||||
#define EFUSE_TRIM_P_BIAS_V 0x0000001FU
|
||||
#define EFUSE_TRIM_P_BIAS_S 5
|
||||
/** EFUSE_RESERVED_1_106 : R; bitpos: [17:10]; default: 0;
|
||||
* reserved
|
||||
/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [13:10]; default: 0;
|
||||
* Active HP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_RESERVED_1_106 0x000000FFU
|
||||
#define EFUSE_RESERVED_1_106_M (EFUSE_RESERVED_1_106_V << EFUSE_RESERVED_1_106_S)
|
||||
#define EFUSE_RESERVED_1_106_V 0x000000FFU
|
||||
#define EFUSE_RESERVED_1_106_S 10
|
||||
/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
|
||||
* Represents the first 14-bit of zeroth part of system data.
|
||||
#define EFUSE_ACTIVE_HP_DBIAS 0x0000000FU
|
||||
#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
|
||||
#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000000FU
|
||||
#define EFUSE_ACTIVE_HP_DBIAS_S 10
|
||||
/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [17:14]; default: 0;
|
||||
* Active LP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU
|
||||
#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
|
||||
#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU
|
||||
#define EFUSE_SYS_DATA_PART0_0_S 18
|
||||
#define EFUSE_ACTIVE_LP_DBIAS 0x0000000FU
|
||||
#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
|
||||
#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000000FU
|
||||
#define EFUSE_ACTIVE_LP_DBIAS_S 14
|
||||
/** EFUSE_LSLP_HP_DBG : R; bitpos: [19:18]; default: 0;
|
||||
* LSLP HP DBG of fixed voltage
|
||||
*/
|
||||
#define EFUSE_LSLP_HP_DBG 0x00000003U
|
||||
#define EFUSE_LSLP_HP_DBG_M (EFUSE_LSLP_HP_DBG_V << EFUSE_LSLP_HP_DBG_S)
|
||||
#define EFUSE_LSLP_HP_DBG_V 0x00000003U
|
||||
#define EFUSE_LSLP_HP_DBG_S 18
|
||||
/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [23:20]; default: 0;
|
||||
* LSLP HP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_LSLP_HP_DBIAS 0x0000000FU
|
||||
#define EFUSE_LSLP_HP_DBIAS_M (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S)
|
||||
#define EFUSE_LSLP_HP_DBIAS_V 0x0000000FU
|
||||
#define EFUSE_LSLP_HP_DBIAS_S 20
|
||||
/** EFUSE_DSLP_LP_DBG : R; bitpos: [27:24]; default: 0;
|
||||
* DSLP LP DBG of fixed voltage
|
||||
*/
|
||||
#define EFUSE_DSLP_LP_DBG 0x0000000FU
|
||||
#define EFUSE_DSLP_LP_DBG_M (EFUSE_DSLP_LP_DBG_V << EFUSE_DSLP_LP_DBG_S)
|
||||
#define EFUSE_DSLP_LP_DBG_V 0x0000000FU
|
||||
#define EFUSE_DSLP_LP_DBG_S 24
|
||||
/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [31:28]; default: 0;
|
||||
* DSLP LP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_DSLP_LP_DBIAS 0x0000000FU
|
||||
#define EFUSE_DSLP_LP_DBIAS_M (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S)
|
||||
#define EFUSE_DSLP_LP_DBIAS_V 0x0000000FU
|
||||
#define EFUSE_DSLP_LP_DBIAS_S 28
|
||||
|
||||
/** EFUSE_RD_MAC_SYS4_REG register
|
||||
* Represents rd_mac_sys
|
||||
*/
|
||||
#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54)
|
||||
/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the first 14-bit of zeroth part of system data.
|
||||
/** EFUSE_DSLP_LP_DBIAS_1 : R; bitpos: [0]; default: 0;
|
||||
* DSLP LP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
|
||||
#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART0_1_S 0
|
||||
#define EFUSE_DSLP_LP_DBIAS_1 (BIT(0))
|
||||
#define EFUSE_DSLP_LP_DBIAS_1_M (EFUSE_DSLP_LP_DBIAS_1_V << EFUSE_DSLP_LP_DBIAS_1_S)
|
||||
#define EFUSE_DSLP_LP_DBIAS_1_V 0x00000001U
|
||||
#define EFUSE_DSLP_LP_DBIAS_1_S 0
|
||||
/** EFUSE_LP_HP_DBIAS_VOL_GAP : R; bitpos: [5:1]; default: 0;
|
||||
* DBIAS gap between LP and HP
|
||||
*/
|
||||
#define EFUSE_LP_HP_DBIAS_VOL_GAP 0x0000001FU
|
||||
#define EFUSE_LP_HP_DBIAS_VOL_GAP_M (EFUSE_LP_HP_DBIAS_VOL_GAP_V << EFUSE_LP_HP_DBIAS_VOL_GAP_S)
|
||||
#define EFUSE_LP_HP_DBIAS_VOL_GAP_V 0x0000001FU
|
||||
#define EFUSE_LP_HP_DBIAS_VOL_GAP_S 1
|
||||
/** EFUSE_RESERVED_1_134 : R; bitpos: [31:6]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_1_134 0x03FFFFFFU
|
||||
#define EFUSE_RESERVED_1_134_M (EFUSE_RESERVED_1_134_V << EFUSE_RESERVED_1_134_S)
|
||||
#define EFUSE_RESERVED_1_134_V 0x03FFFFFFU
|
||||
#define EFUSE_RESERVED_1_134_S 6
|
||||
|
||||
/** EFUSE_RD_MAC_SYS5_REG register
|
||||
* Represents rd_mac_sys
|
||||
@ -895,13 +937,13 @@ extern "C" {
|
||||
* Represents rd_sys_part1_data4
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
|
||||
/** EFUSE_RESERVED_2_128 : R; bitpos: [8:0]; default: 0;
|
||||
* reserved
|
||||
/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
|
||||
* Temperature calibration data
|
||||
*/
|
||||
#define EFUSE_RESERVED_2_128 0x000001FFU
|
||||
#define EFUSE_RESERVED_2_128_M (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S)
|
||||
#define EFUSE_RESERVED_2_128_V 0x000001FFU
|
||||
#define EFUSE_RESERVED_2_128_S 0
|
||||
#define EFUSE_TEMPERATURE_SENSOR 0x000001FFU
|
||||
#define EFUSE_TEMPERATURE_SENSOR_M (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
|
||||
#define EFUSE_TEMPERATURE_SENSOR_V 0x000001FFU
|
||||
#define EFUSE_TEMPERATURE_SENSOR_S 0
|
||||
/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
|
||||
* ADC OCode
|
||||
*/
|
||||
@ -909,49 +951,147 @@ extern "C" {
|
||||
#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S)
|
||||
#define EFUSE_OCODE_V 0x000000FFU
|
||||
#define EFUSE_OCODE_S 9
|
||||
/** EFUSE_RESERVED_2_145 : R; bitpos: [31:17]; default: 0;
|
||||
* reserved
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_RESERVED_2_145 0x00007FFFU
|
||||
#define EFUSE_RESERVED_2_145_M (EFUSE_RESERVED_2_145_V << EFUSE_RESERVED_2_145_S)
|
||||
#define EFUSE_RESERVED_2_145_V 0x00007FFFU
|
||||
#define EFUSE_RESERVED_2_145_S 17
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 17
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 27
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA5_REG register
|
||||
* Represents rd_sys_part1_data5
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
|
||||
/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
|
||||
#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_5_S 0
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S 0
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S 5
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S 15
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0;
|
||||
* HI DOUT of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x0000007FU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x0000007FU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 25
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA6_REG register
|
||||
* Represents rd_sys_part1_data6
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
|
||||
/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
|
||||
* HI DOUT of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
|
||||
#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_6_S 0
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1 0x00000007U
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V 0x00000007U
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S 0
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0;
|
||||
* HI DOUT of ADC1 atten1
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 3
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0;
|
||||
* HI DOUT of ADC1 atten2
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 13
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0;
|
||||
* HI DOUT of ADC1 atten3
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000001FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000001FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 23
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA7_REG register
|
||||
* Represents rd_sys_part1_data7
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
|
||||
/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0;
|
||||
* HI DOUT of ADC1 atten3
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
|
||||
#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_7_S 0
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1 (BIT(0))
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V 0x00000001U
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S 0
|
||||
/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0;
|
||||
* Gap between ADC1 CH0 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 1
|
||||
/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0;
|
||||
* Gap between ADC1 CH1 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 5
|
||||
/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0;
|
||||
* Gap between ADC1 CH2 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 9
|
||||
/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0;
|
||||
* Gap between ADC1 CH3 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 13
|
||||
/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [20:17]; default: 0;
|
||||
* Gap between ADC1 CH4 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S 17
|
||||
/** EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [24:21]; default: 0;
|
||||
* Gap between ADC1 CH5 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S 21
|
||||
/** EFUSE_RESERVED_2_249 : R; bitpos: [31:25]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_2_249 0x0000007FU
|
||||
#define EFUSE_RESERVED_2_249_M (EFUSE_RESERVED_2_249_V << EFUSE_RESERVED_2_249_S)
|
||||
#define EFUSE_RESERVED_2_249_V 0x0000007FU
|
||||
#define EFUSE_RESERVED_2_249_S 25
|
||||
|
||||
/** EFUSE_RD_USR_DATA0_REG register
|
||||
* Represents rd_usr_data0
|
||||
|
||||
@ -615,14 +615,30 @@ typedef union {
|
||||
* PADC CAL P bias
|
||||
*/
|
||||
uint32_t trim_p_bias:5;
|
||||
/** reserved_1_106 : R; bitpos: [17:10]; default: 0;
|
||||
* reserved
|
||||
/** active_hp_dbias : R; bitpos: [13:10]; default: 0;
|
||||
* Active HP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t reserved_1_106:8;
|
||||
/** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
|
||||
* Represents the first 14-bit of zeroth part of system data.
|
||||
uint32_t active_hp_dbias:4;
|
||||
/** active_lp_dbias : R; bitpos: [17:14]; default: 0;
|
||||
* Active LP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t sys_data_part0_0:14;
|
||||
uint32_t active_lp_dbias:4;
|
||||
/** lslp_hp_dbg : R; bitpos: [19:18]; default: 0;
|
||||
* LSLP HP DBG of fixed voltage
|
||||
*/
|
||||
uint32_t lslp_hp_dbg:2;
|
||||
/** lslp_hp_dbias : R; bitpos: [23:20]; default: 0;
|
||||
* LSLP HP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t lslp_hp_dbias:4;
|
||||
/** dslp_lp_dbg : R; bitpos: [27:24]; default: 0;
|
||||
* DSLP LP DBG of fixed voltage
|
||||
*/
|
||||
uint32_t dslp_lp_dbg:4;
|
||||
/** dslp_lp_dbias : R; bitpos: [31:28]; default: 0;
|
||||
* DSLP LP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t dslp_lp_dbias:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys3_reg_t;
|
||||
@ -632,10 +648,18 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the first 14-bit of zeroth part of system data.
|
||||
/** dslp_lp_dbias_1 : R; bitpos: [0]; default: 0;
|
||||
* DSLP LP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t sys_data_part0_1:32;
|
||||
uint32_t dslp_lp_dbias_1:1;
|
||||
/** lp_hp_dbias_vol_gap : R; bitpos: [5:1]; default: 0;
|
||||
* DBIAS gap between LP and HP
|
||||
*/
|
||||
uint32_t lp_hp_dbias_vol_gap:5;
|
||||
/** reserved_1_134 : R; bitpos: [31:6]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_1_134:26;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys4_reg_t;
|
||||
@ -712,18 +736,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** reserved_2_128 : R; bitpos: [8:0]; default: 0;
|
||||
* reserved
|
||||
/** temperature_sensor : R; bitpos: [8:0]; default: 0;
|
||||
* Temperature calibration data
|
||||
*/
|
||||
uint32_t reserved_2_128:9;
|
||||
uint32_t temperature_sensor:9;
|
||||
/** ocode : R; bitpos: [16:9]; default: 0;
|
||||
* ADC OCode
|
||||
*/
|
||||
uint32_t ocode:8;
|
||||
/** reserved_2_145 : R; bitpos: [31:17]; default: 0;
|
||||
* reserved
|
||||
/** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
uint32_t reserved_2_145:15;
|
||||
uint32_t adc1_ave_initcode_atten0:10;
|
||||
/** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
uint32_t adc1_ave_initcode_atten1:5;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data4_reg_t;
|
||||
@ -733,10 +761,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
uint32_t sys_data_part1_5:32;
|
||||
uint32_t adc1_ave_initcode_atten1_1:5;
|
||||
/** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
uint32_t adc1_ave_initcode_atten2:10;
|
||||
/** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
uint32_t adc1_ave_initcode_atten3:10;
|
||||
/** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0;
|
||||
* HI DOUT of ADC1 atten0
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten0:7;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data5_reg_t;
|
||||
@ -746,10 +786,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0;
|
||||
* HI DOUT of ADC1 atten0
|
||||
*/
|
||||
uint32_t sys_data_part1_6:32;
|
||||
uint32_t adc1_hi_dout_atten0_1:3;
|
||||
/** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0;
|
||||
* HI DOUT of ADC1 atten1
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten1:10;
|
||||
/** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0;
|
||||
* HI DOUT of ADC1 atten2
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten2:10;
|
||||
/** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0;
|
||||
* HI DOUT of ADC1 atten3
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten3:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data6_reg_t;
|
||||
@ -759,10 +811,38 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0;
|
||||
* HI DOUT of ADC1 atten3
|
||||
*/
|
||||
uint32_t sys_data_part1_7:32;
|
||||
uint32_t adc1_hi_dout_atten3_1:1;
|
||||
/** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0;
|
||||
* Gap between ADC1 CH0 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch0_atten0_initcode_diff:4;
|
||||
/** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0;
|
||||
* Gap between ADC1 CH1 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch1_atten0_initcode_diff:4;
|
||||
/** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0;
|
||||
* Gap between ADC1 CH2 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch2_atten0_initcode_diff:4;
|
||||
/** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0;
|
||||
* Gap between ADC1 CH3 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch3_atten0_initcode_diff:4;
|
||||
/** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0;
|
||||
* Gap between ADC1 CH4 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch4_atten0_initcode_diff:4;
|
||||
/** adc1_ch5_atten0_initcode_diff : R; bitpos: [24:21]; default: 0;
|
||||
* Gap between ADC1 CH5 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch5_atten0_initcode_diff:4;
|
||||
/** reserved_2_249 : R; bitpos: [31:25]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_2_249:7;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data7_reg_t;
|
||||
@ -2090,123 +2170,6 @@ typedef union {
|
||||
uint32_t val;
|
||||
} efuse_conf_reg_t;
|
||||
|
||||
/** Group: EFUSE Configure Registers */
|
||||
/** Type of dac_conf register
|
||||
* Controls the eFuse programming voltage.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
|
||||
* Controls the division factor of the rising clock of the programming voltage.
|
||||
*/
|
||||
uint32_t dac_clk_div:8;
|
||||
/** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
|
||||
* Don't care.
|
||||
*/
|
||||
uint32_t dac_clk_pad_sel:1;
|
||||
/** dac_num : R/W; bitpos: [16:9]; default: 255;
|
||||
* Controls the rising period of the programming voltage.
|
||||
*/
|
||||
uint32_t dac_num:8;
|
||||
/** oe_clr : R/W; bitpos: [17]; default: 0;
|
||||
* Reduces the power supply of the programming voltage.
|
||||
*/
|
||||
uint32_t oe_clr:1;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_dac_conf_reg_t;
|
||||
|
||||
/** Type of rd_tim_conf register
|
||||
* Configures read timing parameters.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** thr_a : R/W; bitpos: [7:0]; default: 1;
|
||||
* Configures the read hold time.
|
||||
*/
|
||||
uint32_t thr_a:8;
|
||||
/** trd : R/W; bitpos: [15:8]; default: 2;
|
||||
* Configures the read time.
|
||||
*/
|
||||
uint32_t trd:8;
|
||||
/** tsur_a : R/W; bitpos: [23:16]; default: 1;
|
||||
* Configures the read setup time.
|
||||
*/
|
||||
uint32_t tsur_a:8;
|
||||
/** read_init_num : R/W; bitpos: [31:24]; default: 22;
|
||||
* Configures the waiting time of reading eFuse memory.
|
||||
*/
|
||||
uint32_t read_init_num:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_tim_conf_reg_t;
|
||||
|
||||
/** Type of wr_tim_conf1 register
|
||||
* Configurarion register 1 of eFuse programming timing parameters.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tsup_a : R/W; bitpos: [7:0]; default: 1;
|
||||
* Configures the programming setup time.
|
||||
*/
|
||||
uint32_t tsup_a:8;
|
||||
/** pwr_on_num : R/W; bitpos: [23:8]; default: 12288;
|
||||
* Configures the power up time for VDDQ.
|
||||
*/
|
||||
uint32_t pwr_on_num:16;
|
||||
/** thp_a : R/W; bitpos: [31:24]; default: 1;
|
||||
* Configures the programming hold time.
|
||||
*/
|
||||
uint32_t thp_a:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_wr_tim_conf1_reg_t;
|
||||
|
||||
/** Type of wr_tim_conf2 register
|
||||
* Configurarion register 2 of eFuse programming timing parameters.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
|
||||
* Configures the power outage time for VDDQ.
|
||||
*/
|
||||
uint32_t pwr_off_num:16;
|
||||
/** tpgm : R/W; bitpos: [31:16]; default: 200;
|
||||
* Configures the active programming time.
|
||||
*/
|
||||
uint32_t tpgm:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_wr_tim_conf2_reg_t;
|
||||
|
||||
/** Type of wr_tim_conf0_rs_bypass register
|
||||
* Configurarion register0 of eFuse programming time parameters and rs bypass
|
||||
* operation.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to bypass reed solomon correction step.
|
||||
*/
|
||||
uint32_t bypass_rs_correction:1;
|
||||
/** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
|
||||
* Configures block number of programming twice operation.
|
||||
*/
|
||||
uint32_t bypass_rs_blk_num:11;
|
||||
/** update : WT; bitpos: [12]; default: 0;
|
||||
* Set this bit to update multi-bit register signals.
|
||||
*/
|
||||
uint32_t update:1;
|
||||
/** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
|
||||
* Configures the inactive programming time.
|
||||
*/
|
||||
uint32_t tpgm_inactive:8;
|
||||
uint32_t reserved_21:11;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_wr_tim_conf0_rs_bypass_reg_t;
|
||||
|
||||
|
||||
/** Group: EFUSE Status Registers */
|
||||
/** Type of status register
|
||||
@ -2355,6 +2318,124 @@ typedef union {
|
||||
} efuse_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: EFUSE Configure Registers */
|
||||
/** Type of dac_conf register
|
||||
* Controls the eFuse programming voltage.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
|
||||
* Controls the division factor of the rising clock of the programming voltage.
|
||||
*/
|
||||
uint32_t dac_clk_div:8;
|
||||
/** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
|
||||
* Don't care.
|
||||
*/
|
||||
uint32_t dac_clk_pad_sel:1;
|
||||
/** dac_num : R/W; bitpos: [16:9]; default: 255;
|
||||
* Controls the rising period of the programming voltage.
|
||||
*/
|
||||
uint32_t dac_num:8;
|
||||
/** oe_clr : R/W; bitpos: [17]; default: 0;
|
||||
* Reduces the power supply of the programming voltage.
|
||||
*/
|
||||
uint32_t oe_clr:1;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_dac_conf_reg_t;
|
||||
|
||||
/** Type of rd_tim_conf register
|
||||
* Configures read timing parameters.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** thr_a : R/W; bitpos: [7:0]; default: 1;
|
||||
* Configures the read hold time.
|
||||
*/
|
||||
uint32_t thr_a:8;
|
||||
/** trd : R/W; bitpos: [15:8]; default: 2;
|
||||
* Configures the read time.
|
||||
*/
|
||||
uint32_t trd:8;
|
||||
/** tsur_a : R/W; bitpos: [23:16]; default: 1;
|
||||
* Configures the read setup time.
|
||||
*/
|
||||
uint32_t tsur_a:8;
|
||||
/** read_init_num : R/W; bitpos: [31:24]; default: 22;
|
||||
* Configures the waiting time of reading eFuse memory.
|
||||
*/
|
||||
uint32_t read_init_num:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_tim_conf_reg_t;
|
||||
|
||||
/** Type of wr_tim_conf1 register
|
||||
* Configurarion register 1 of eFuse programming timing parameters.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tsup_a : R/W; bitpos: [7:0]; default: 1;
|
||||
* Configures the programming setup time.
|
||||
*/
|
||||
uint32_t tsup_a:8;
|
||||
/** pwr_on_num : R/W; bitpos: [23:8]; default: 12288;
|
||||
* Configures the power up time for VDDQ.
|
||||
*/
|
||||
uint32_t pwr_on_num:16;
|
||||
/** thp_a : R/W; bitpos: [31:24]; default: 1;
|
||||
* Configures the programming hold time.
|
||||
*/
|
||||
uint32_t thp_a:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_wr_tim_conf1_reg_t;
|
||||
|
||||
/** Type of wr_tim_conf2 register
|
||||
* Configurarion register 2 of eFuse programming timing parameters.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
|
||||
* Configures the power outage time for VDDQ.
|
||||
*/
|
||||
uint32_t pwr_off_num:16;
|
||||
/** tpgm : R/W; bitpos: [31:16]; default: 200;
|
||||
* Configures the active programming time.
|
||||
*/
|
||||
uint32_t tpgm:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_wr_tim_conf2_reg_t;
|
||||
|
||||
/** Type of wr_tim_conf0_rs_bypass register
|
||||
* Configurarion register0 of eFuse programming time parameters and rs bypass
|
||||
* operation.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to bypass reed solomon correction step.
|
||||
*/
|
||||
uint32_t bypass_rs_correction:1;
|
||||
/** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
|
||||
* Configures block number of programming twice operation.
|
||||
*/
|
||||
uint32_t bypass_rs_blk_num:11;
|
||||
/** update : WT; bitpos: [12]; default: 0;
|
||||
* Set this bit to update multi-bit register signals.
|
||||
*/
|
||||
uint32_t update:1;
|
||||
/** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
|
||||
* Configures the inactive programming time.
|
||||
*/
|
||||
uint32_t tpgm_inactive:8;
|
||||
uint32_t reserved_21:11;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_wr_tim_conf0_rs_bypass_reg_t;
|
||||
|
||||
|
||||
/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
|
||||
/** Type of apb2otp_wr_dis register
|
||||
* eFuse apb2otp block0 data register1.
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user