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Merge branch 'contrib/github_pr_12093' into 'master'

Browse Source 
hal: fix compile issues with cxx

Closes IDFGH-10892, IDF-8017, and IDF-8014

See merge request espressif/esp-idf!25421
This commit is contained in:
Lu Ze Yu 2023-09-15 10:21:11 +08:00
commit 43db5fbb6e
114 changed files with 623 additions and 564 deletions
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2
components/cxx/test_apps/general/main/test_cxx_general.cpp
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@ -318,5 +318,3 @@ template<typename T> __attribute__((unused)) static void test_binary_operators()
}
//Add more types here. If any flags cannot pass the build, use FLAG_ATTR in esp_attr.h
#include "driver/timer_types_legacy.h"
template void test_binary_operators<timer_intr_t>();

1
components/driver/deprecated/driver/timer_types_legacy.h
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@ -51,7 +51,6 @@ typedef enum {
#endif
TIMER_INTR_NONE = 0
} timer_intr_t;
FLAG_ATTR(timer_intr_t)
/**
* @brief Timer count direction

1
components/esp_common/include/esp_assert.h
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@ -9,6 +9,7 @@
#include "assert.h"
/* Since IDF v5.0, C17 standard is used, which supports both _Static_assert and static_assert syntax */
/* Please do not use `_Static_assert` for C++ compatibility */
#define ESP_STATIC_ASSERT static_assert
/* Assert at compile time if possible, runtime otherwise */

2
components/hal/esp32/include/hal/aes_ll.h
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@ -125,7 +125,7 @@ static inline void aes_ll_start_transform(void)
*/
static inline esp_aes_state_t aes_ll_get_state(void)
{
return DPORT_REG_READ(AES_IDLE_REG);
return (esp_aes_state_t)DPORT_REG_READ(AES_IDLE_REG);
}
#ifdef __cplusplus

80
components/hal/esp32/include/hal/cache_ll.h
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@ -95,26 +95,26 @@ __attribute__((always_inline))
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
HAL_ASSERT(cache_id == 0 || cache_id == 1);
cache_bus_mask_t mask = 0;
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IROM0_CACHE_ADDRESS_HIGH) {
HAL_ASSERT(false); //out of range
} else if (vaddr_start >= SOC_IROM0_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS2;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS2);
} else if (vaddr_start >= SOC_IRAM1_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS1;
mask |= (vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS1);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0));
} else if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS0;
mask |= (vaddr_end >= SOC_IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
mask |= (vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0));
} else if (vaddr_start >= SOC_DRAM1_CACHE_ADDRESS_LOW) {
HAL_ASSERT(vaddr_end < SOC_DRAM1_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
mask |= CACHE_BUS_DBUS1;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS1);
} else if (vaddr_start >= SOC_DROM0_CACHE_ADDRESS_LOW) {
HAL_ASSERT(vaddr_end < SOC_DROM0_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
mask |= CACHE_BUS_DBUS0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
} else {
HAL_ASSERT(false);
}
@ -139,21 +139,21 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
uint32_t bus_mask = 0;
if (cache_id == 0) {
bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0;
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0);
bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0;
bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0;
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0);
DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
} else {
bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0;
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0);
bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0;
bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0;
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0);
DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
}
@ -169,24 +169,24 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
__attribute__((always_inline))
static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
{
cache_bus_mask_t mask = 0;
cache_bus_mask_t mask = (cache_bus_mask_t)0;
HAL_ASSERT(cache_id == 0 || cache_id == 1);
if (cache_id == 0) {
uint32_t bus_mask= DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG);
mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0;
mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0;
mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0;
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0));
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0));
mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0;
mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0;
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0));
} else {
uint32_t bus_mask= DPORT_REG_READ(DPORT_APP_CACHE_CTRL1_REG);
mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0;
mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0;
mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0;
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0));
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0));
mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0;
mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0;
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0));
}
return mask;
}
@ -206,21 +206,21 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
uint32_t bus_mask = 0;
if (cache_id == 0) {
bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0;
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0);
bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0;
bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0;
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0);
DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
} else {
bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0;
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0);
bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0;
bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0;
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0);
DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
}

11
components/hal/esp32/include/hal/i2c_ll.h
View File

@ -15,6 +15,7 @@
#include "soc/clk_tree_defs.h"
#include "hal/i2c_types.h"
#include "esp_attr.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -780,7 +781,8 @@ static inline void i2c_ll_set_scl_clk_timing(i2c_dev_t *hw, int high_period, int
__attribute__((always_inline))
static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.tx_fifo_empty) {
*event = I2C_INTR_EVENT_TXFIFO_EMPTY;
} else if (int_sts.trans_complete) {
@ -803,7 +805,8 @@ static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event
__attribute__((always_inline))
static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.arbitration_lost) {
*event = I2C_INTR_EVENT_ARBIT_LOST;
} else if (int_sts.ack_err) {
@ -959,8 +962,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo
*/
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
{
*tx_mode = hw->ctr.tx_lsb_first;
*rx_mode = hw->ctr.rx_lsb_first;
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
*rx_mode = (i2c_trans_mode_t)(hw->ctr.rx_lsb_first);
}
/**

2
components/hal/esp32/include/hal/ledc_ll.h
View File

@ -521,7 +521,7 @@ static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_
*/
static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel)
{
*timer_sel = hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel;
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
#ifdef __cplusplus

3
components/hal/esp32/include/hal/mcpwm_ll.h
View File

@ -1584,7 +1584,8 @@ static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id)
{
mcpwm_timer_cfg0_reg_t cfg0 = mcpwm->timer[timer_id].timer_cfg0;
mcpwm_timer_cfg0_reg_t cfg0;
cfg0.val = mcpwm->timer[timer_id].timer_cfg0.val;
return cfg0.timer_prescale + 1;
}

2
components/hal/esp32/include/hal/mpi_ll.h
View File

@ -7,6 +7,7 @@
#include <stdbool.h>
#include <string.h>
#include <sys/param.h>
#include "hal/assert.h"
#include "hal/mpi_types.h"
#include "soc/dport_reg.h"
@ -17,6 +18,7 @@
extern "C" {
#endif
/* Round up number of words to nearest
512 bit (16 word) block count.
*/

38
components/hal/esp32/include/hal/pcnt_ll.h
View File

@ -17,8 +17,10 @@
#include <limits.h>
#include <stdlib.h>
#include <stdbool.h>
#include <soc/soc.h>
#include "soc/pcnt_struct.h"
#include "hal/pcnt_types.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -92,7 +94,9 @@ static inline void pcnt_ll_set_level_action(pcnt_dev_t *hw, uint32_t unit, uint3
__attribute__((always_inline))
static inline int pcnt_ll_get_count(pcnt_dev_t *hw, uint32_t unit)
{
typeof(hw->cnt_unit[unit]) cnt_reg = hw->cnt_unit[unit];
typeof(hw->cnt_unit[unit]) cnt_reg;
cnt_reg.val = hw->cnt_unit[unit].val;
int16_t value = cnt_reg.cnt_val;
return value;
}
@ -248,9 +252,11 @@ static inline void pcnt_ll_disable_all_events(pcnt_dev_t *hw, uint32_t unit)
*/
static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
typeof(hw->conf_unit[unit].conf2) conf2_reg = hw->conf_unit[unit].conf2;
typeof(hw->conf_unit[unit].conf2) conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_h_lim = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@ -262,9 +268,11 @@ static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, i
*/
static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
typeof(hw->conf_unit[unit].conf2) conf2_reg = hw->conf_unit[unit].conf2;
typeof(hw->conf_unit[unit].conf2) conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_l_lim = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@ -277,13 +285,15 @@ static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, in
*/
static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres, int value)
{
typeof(hw->conf_unit[unit].conf1) conf1_reg = hw->conf_unit[unit].conf1;
typeof(hw->conf_unit[unit].conf1) conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
conf1_reg.cnt_thres0 = value;
} else {
conf1_reg.cnt_thres1 = value;
}
hw->conf_unit[unit].conf1 = conf1_reg;
hw->conf_unit[unit].conf1.val = conf1_reg.val;
}
/**
@ -295,7 +305,9 @@ static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32
*/
static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
typeof(hw->conf_unit[unit].conf2) conf2_reg = hw->conf_unit[unit].conf2;
typeof(hw->conf_unit[unit].conf2) conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_h_lim;
return value;
}
@ -309,7 +321,9 @@ static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
*/
static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
typeof(hw->conf_unit[unit].conf2) conf2_reg = hw->conf_unit[unit].conf2;
typeof(hw->conf_unit[unit].conf2) conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_l_lim;
return value;
}
@ -325,7 +339,9 @@ static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
static inline int pcnt_ll_get_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres)
{
int16_t value;
typeof(hw->conf_unit[unit].conf1) conf1_reg = hw->conf_unit[unit].conf1;
typeof(hw->conf_unit[unit].conf1) conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
value = conf1_reg.cnt_thres0;
} else {
@ -356,7 +372,7 @@ static inline uint32_t pcnt_ll_get_unit_status(pcnt_dev_t *hw, uint32_t unit)
__attribute__((always_inline))
static inline pcnt_unit_zero_cross_mode_t pcnt_ll_get_zero_cross_mode(pcnt_dev_t *hw, uint32_t unit)
{
return hw->status_unit[unit].val & 0x03;
return (pcnt_unit_zero_cross_mode_t)(hw->status_unit[unit].val & 0x03);
}
/**

4
components/hal/esp32/include/hal/sdio_slave_ll.h
View File

@ -451,7 +451,7 @@ static inline void sdio_slave_ll_host_set_reg(host_dev_t* host, int pos, uint8_t
*/
static inline sdio_slave_hostint_t sdio_slave_ll_host_get_intena(host_dev_t* host)
{
return host->slc0_func1_int_ena.val;
return (sdio_slave_hostint_t)host->slc0_func1_int_ena.val;
}
/**
@ -507,7 +507,7 @@ static inline void sdio_slave_ll_slvint_set_ena(slc_dev_t *slc, const sdio_slave
*/
static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_ll_slvint_t *out_slv_int)
{
sdio_slave_ll_slvint_t slv_int = slc->slc0_int_st.val & 0xff;
sdio_slave_ll_slvint_t slv_int = (sdio_slave_ll_slvint_t)(slc->slc0_int_st.val & 0xff);
*out_slv_int = slv_int;
slc->slc0_int_clr.val = slv_int;
}

12
components/hal/esp32/include/hal/spi_flash_ll.h
View File

@ -242,9 +242,10 @@ static inline void spi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
*/
static inline void spi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
ctrl.val &= ~(SPI_FREAD_QIO_M | SPI_FREAD_QUAD_M | SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M);
ctrl.val |= SPI_FASTRD_MODE_M;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val = ctrl.val & ~(SPI_FREAD_QIO_M | SPI_FREAD_QUAD_M | SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M);
ctrl.val = ctrl.val | SPI_FASTRD_MODE_M;
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
@ -267,7 +268,7 @@ static inline void spi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_
default:
abort();
}
dev->ctrl = ctrl;
dev->ctrl.val = ctrl.val;
}
/**
@ -318,9 +319,10 @@ static inline void spi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, uin
dev->user.usr_command = 1;
typeof(dev->user2) user2 = {
.usr_command_value = command,
.reserved16 = 0,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

4
components/hal/esp32/include/hal/uart_ll.h
View File

@ -145,7 +145,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
*/
FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
hw->int_ena.val = hw->int_ena.val | mask;
}
/**
@ -158,7 +158,7 @@ FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
*/
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val &= (~mask);
hw->int_ena.val = hw->int_ena.val & (~mask);
}
/**

2
components/hal/esp32c2/include/hal/adc_ll.h
View File

@ -544,7 +544,7 @@ static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t chann
{
(void)adc_n;
(void)channel;
return APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten;
return (adc_atten_t)(APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten);
}
#ifdef __cplusplus

14
components/hal/esp32c2/include/hal/cache_ll.h
View File

@ -166,13 +166,13 @@ __attribute__((always_inline))
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
HAL_ASSERT(cache_id == 0);
cache_bus_mask_t mask = 0;
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_IBUS0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
} else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_DBUS0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
} else {
HAL_ASSERT(0); //Out of region
}
@ -196,11 +196,11 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0);
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0);
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
}
@ -218,11 +218,11 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0);
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0);
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
}

4
components/hal/esp32c2/include/hal/ecc_ll.h
View File

@ -106,7 +106,7 @@ static inline int ecc_ll_is_calc_finished(void)
static inline ecc_mode_t ecc_ll_get_mode(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE);
return (ecc_mode_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE));
}
static inline int ecc_ll_get_verification_result(void)
@ -116,7 +116,7 @@ static inline int ecc_ll_get_verification_result(void)
static inline ecc_curve_t ecc_ll_get_curve(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
return (ecc_curve_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH));
}
static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len)

18
components/hal/esp32c2/include/hal/gpspi_flash_ll.h
View File

@ -180,12 +180,12 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -210,8 +210,10 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
*/
static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->user) user = dev->user;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
typeof (dev->user) user;
user.val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
@ -243,8 +245,8 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
abort();
}
dev->ctrl = ctrl;
dev->user = user;
dev->ctrl.val = ctrl.val;
dev->user.val = user.val;
}
/**
@ -255,7 +257,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
*/
static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock_reg_t *clock_val)
{
dev->clock = *clock_val;
dev->clock.val = (*clock_val).val;
}
/**
@ -301,7 +303,7 @@ static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, u
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

8
components/hal/esp32c2/include/hal/i2c_ll.h
View File

@ -732,7 +732,9 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in
__attribute__((always_inline))
static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
i2c_int_status_reg_t int_sts = hw->int_status;
i2c_int_status_reg_t int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.arbitration_lost_int_st) {
*event = I2C_INTR_EVENT_ARBIT_LOST;
} else if (int_sts.nack_int_st) {
@ -828,8 +830,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo
*/
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
{
*tx_mode = hw->ctr.tx_lsb_first;
*rx_mode = hw->ctr.rx_lsb_first;
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
*rx_mode = (i2c_trans_mode_t)(hw->ctr.rx_lsb_first);
}
/**

2
components/hal/esp32c2/include/hal/ledc_ll.h
View File

@ -506,7 +506,7 @@ static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_
*/
static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel)
{
*timer_sel = hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel;
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
#ifdef __cplusplus

1
components/hal/esp32c2/include/hal/mpu_ll.h
View File

@ -7,6 +7,7 @@
#include <stdint.h>
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {

2
components/hal/esp32c2/include/hal/spi_ll.h
View File

@ -63,7 +63,6 @@ typedef enum {
SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD.
SPI_LL_INTR_SEG_DONE = BIT(14),
} spi_ll_intr_t;
FLAG_ATTR(spi_ll_intr_t)
// Flags for conditions under which the transaction length should be recorded
typedef enum {
@ -72,7 +71,6 @@ typedef enum {
SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded
SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded
} spi_ll_trans_len_cond_t;
FLAG_ATTR(spi_ll_trans_len_cond_t)
// SPI base command in esp32c2
typedef enum {

12
components/hal/esp32c2/include/hal/spimem_flash_ll.h
View File

@ -396,12 +396,12 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -426,7 +426,9 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
*/
static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
switch (read_mode) {
@ -451,7 +453,7 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
default:
abort();
}
dev->ctrl = ctrl;
dev->ctrl.val = ctrl.val;
}
/**
@ -504,7 +506,7 @@ static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t comm
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

4
components/hal/esp32c2/include/hal/uart_ll.h
View File

@ -200,7 +200,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
*/
FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
hw->int_ena.val = hw->int_ena.val | mask;
}
/**
@ -213,7 +213,7 @@ FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
*/
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val &= (~mask);
hw->int_ena.val = hw->int_ena.val & (~mask);
}
/**

2
components/hal/esp32c3/include/hal/adc_ll.h
View File

@ -956,7 +956,7 @@ static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t chann
{
(void)adc_n;
(void)channel;
return APB_SARADC.onetime_sample.onetime_atten;
return (adc_atten_t)(APB_SARADC.onetime_sample.onetime_atten);
}
#ifdef __cplusplus

2
components/hal/esp32c3/include/hal/aes_ll.h
View File

@ -112,7 +112,7 @@ static inline void aes_ll_start_transform(void)
*/
static inline esp_aes_state_t aes_ll_get_state(void)
{
return REG_READ(AES_STATE_REG);
return (esp_aes_state_t)REG_READ(AES_STATE_REG);
}

14
components/hal/esp32c3/include/hal/cache_ll.h
View File

@ -168,13 +168,13 @@ __attribute__((always_inline))
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
HAL_ASSERT(cache_id == 0);
cache_bus_mask_t mask = 0;
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_IBUS0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
} else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_DBUS0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
} else {
HAL_ASSERT(0); //Out of region
}
@ -198,11 +198,11 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0);
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0);
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
}
@ -220,11 +220,11 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0);
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0);
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
}

16
components/hal/esp32c3/include/hal/gpspi_flash_ll.h
View File

@ -181,12 +181,12 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -211,8 +211,10 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
*/
static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->user) user = dev->user;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
typeof (dev->user) user;
user.val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
@ -244,8 +246,8 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
abort();
}
dev->ctrl = ctrl;
dev->user = user;
dev->ctrl.val = ctrl.val;
dev->user.val = user.val;
}
/**
@ -302,7 +304,7 @@ static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, u
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

11
components/hal/esp32c3/include/hal/i2c_ll.h
View File

@ -18,6 +18,7 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/clk_tree_defs.h"
#include "esp_attr.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -882,7 +883,8 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in
__attribute__((always_inline))
static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.arbitration_lost) {
*event = I2C_INTR_EVENT_ARBIT_LOST;
} else if (int_sts.nack) {
@ -909,7 +911,8 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even
__attribute__((always_inline))
static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.tx_fifo_wm) {
*event = I2C_INTR_EVENT_TXFIFO_EMPTY;
} else if (int_sts.trans_complete) {
@ -1051,8 +1054,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo
*/
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
{
*tx_mode = hw->ctr.tx_lsb_first;
*rx_mode = hw->ctr.rx_lsb_first;
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
*rx_mode = (i2c_trans_mode_t)(hw->ctr.rx_lsb_first);
}
/**

2
components/hal/esp32c3/include/hal/ledc_ll.h
View File

@ -506,7 +506,7 @@ static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_
*/
static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel)
{
*timer_sel = hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel;
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
#ifdef __cplusplus

2
components/hal/esp32c3/include/hal/mpi_ll.h
View File

@ -7,6 +7,7 @@
#include <stdbool.h>
#include <string.h>
#include <sys/param.h>
#include "hal/assert.h"
#include "hal/mpi_types.h"
#include "soc/hwcrypto_periph.h"
@ -17,6 +18,7 @@
extern "C" {
#endif
static inline size_t mpi_ll_calculate_hardware_words(size_t words)
{
return words;

2
components/hal/esp32c3/include/hal/mpu_ll.h
View File

@ -5,8 +5,8 @@
*/
#include <stdint.h>
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {

4
components/hal/esp32c3/include/hal/spi_ll.h
View File

@ -63,7 +63,7 @@ typedef enum {
SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD.
SPI_LL_INTR_SEG_DONE = BIT(14),
} spi_ll_intr_t;
FLAG_ATTR(spi_ll_intr_t)
// Flags for conditions under which the transaction length should be recorded
typedef enum {
@ -72,7 +72,7 @@ typedef enum {
SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded
SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded
} spi_ll_trans_len_cond_t;
FLAG_ATTR(spi_ll_trans_len_cond_t)
// SPI base command in esp32c3
typedef enum {

12
components/hal/esp32c3/include/hal/spimem_flash_ll.h
View File

@ -398,12 +398,12 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -428,7 +428,9 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
*/
static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
switch (read_mode) {
@ -453,7 +455,7 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
default:
abort();
}
dev->ctrl = ctrl;
dev->ctrl.val = ctrl.val;
}
/**
@ -506,7 +508,7 @@ static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t comm
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

4
components/hal/esp32c3/include/hal/uart_ll.h
View File

@ -199,7 +199,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
*/
FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
hw->int_ena.val = hw->int_ena.val | mask;
}
/**
@ -212,7 +212,7 @@ FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
*/
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val &= (~mask);
hw->int_ena.val = hw->int_ena.val & (~mask);
}
/**

15
components/hal/esp32c3/include/hal/uhci_ll.h
View File

@ -45,7 +45,9 @@ static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
{
if (seper_char->sub_chr_en) {
typeof(hw->esc_conf0) esc_conf0_reg = hw->esc_conf0;
typeof(hw->esc_conf0) esc_conf0_reg;
esc_conf0_reg.val = hw->esc_conf0.val;
esc_conf0_reg.seper_char = seper_char->seper_chr;
esc_conf0_reg.seper_esc_char0 = seper_char->sub_chr1;
esc_conf0_reg.seper_esc_char1 = seper_char->sub_chr2;
@ -66,10 +68,15 @@ static inline void uhci_ll_get_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper
static inline void uhci_ll_set_swflow_ctrl_sub_chr(uhci_dev_t *hw, uhci_swflow_ctrl_sub_chr_t *sub_ctr)
{
typeof(hw->escape_conf) escape_conf_reg = hw->escape_conf;
typeof(hw->escape_conf) escape_conf_reg;
escape_conf_reg.val = hw->escape_conf.val;
if (sub_ctr->flow_en == 1) {
typeof(hw->esc_conf2) esc_conf2_reg = hw->esc_conf2;
typeof(hw->esc_conf3) esc_conf3_reg = hw->esc_conf3;
typeof(hw->esc_conf2) esc_conf2_reg;
esc_conf2_reg.val = hw->esc_conf2.val;
typeof(hw->esc_conf3) esc_conf3_reg;
esc_conf3_reg.val = hw->esc_conf3.val;
esc_conf2_reg.seq1 = sub_ctr->xon_chr;
esc_conf2_reg.seq1_char0 = sub_ctr->xon_sub1;
esc_conf2_reg.seq1_char1 = sub_ctr->xon_sub2;

2
components/hal/esp32c6/include/hal/aes_ll.h
View File

@ -112,7 +112,7 @@ static inline void aes_ll_start_transform(void)
*/
static inline esp_aes_state_t aes_ll_get_state(void)
{
return REG_READ(AES_STATE_REG);
return (esp_aes_state_t)REG_READ(AES_STATE_REG);
}

12
components/hal/esp32c6/include/hal/cache_ll.h
View File

@ -165,12 +165,12 @@ __attribute__((always_inline))
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
HAL_ASSERT(cache_id == 0);
cache_bus_mask_t mask = 0;
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
//c6 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0;
mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
} else {
HAL_ASSERT(0); //Out of region
}
@ -194,11 +194,11 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0);
REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0);
REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask);
}
@ -216,11 +216,11 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0);
REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0);
REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask);
}

4
components/hal/esp32c6/include/hal/ecc_ll.h
View File

@ -106,7 +106,7 @@ static inline int ecc_ll_is_calc_finished(void)
static inline ecc_mode_t ecc_ll_get_mode(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE);
return (ecc_mode_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE));
}
static inline int ecc_ll_get_verification_result(void)
@ -116,7 +116,7 @@ static inline int ecc_ll_get_verification_result(void)
static inline ecc_curve_t ecc_ll_get_curve(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
return (ecc_curve_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH));
}
static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len)

16
components/hal/esp32c6/include/hal/gpspi_flash_ll.h
View File

@ -181,12 +181,12 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -211,8 +211,10 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
*/
static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->user) user = dev->user;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
typeof (dev->user) user;
user.val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
@ -244,8 +246,8 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
abort();
}
dev->ctrl = ctrl;
dev->user = user;
dev->ctrl.val = ctrl.val;
dev->user.val = user.val;
}
/**
@ -302,7 +304,7 @@ static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, u
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

12
components/hal/esp32c6/include/hal/i2c_ll.h
View File

@ -19,6 +19,7 @@
#include "soc/clk_tree_defs.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/lpperi_struct.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -963,7 +964,9 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in
__attribute__((always_inline))
static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
i2c_int_status_reg_t int_sts = hw->int_status;
i2c_int_status_reg_t int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.arbitration_lost_int_st) {
*event = I2C_INTR_EVENT_ARBIT_LOST;
} else if (int_sts.nack_int_st) {
@ -990,7 +993,8 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even
__attribute__((always_inline))
static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.txfifo_wm_int_st) {
*event = I2C_INTR_EVENT_TXFIFO_EMPTY;
} else if (int_sts.trans_complete_int_st) {
@ -1131,8 +1135,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo
*/
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
{
*tx_mode = hw->ctr.tx_lsb_first;
*rx_mode = hw->ctr.rx_lsb_first;
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
*rx_mode = (i2c_trans_mode_t)(hw->ctr.rx_lsb_first);
}
/**

3
components/hal/esp32c6/include/hal/mcpwm_ll.h
View File

@ -1634,7 +1634,8 @@ static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id)
{
mcpwm_timer_cfg0_reg_t cfg0 = mcpwm->timer[timer_id].timer_cfg0;
mcpwm_timer_cfg0_reg_t cfg0;
cfg0.val = mcpwm->timer[timer_id].timer_cfg0.val;
return cfg0.timer_prescale + 1;
}

2
components/hal/esp32c6/include/hal/mpi_ll.h
View File

@ -7,6 +7,7 @@
#include <stdbool.h>
#include <string.h>
#include <sys/param.h>
#include "hal/assert.h"
#include "hal/mpi_types.h"
#include "soc/pcr_reg.h"
@ -17,6 +18,7 @@
extern "C" {
#endif
static inline size_t mpi_ll_calculate_hardware_words(size_t words)
{
return words;

1
components/hal/esp32c6/include/hal/mpu_ll.h
View File

@ -7,6 +7,7 @@
#include <stdint.h>
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {

36
components/hal/esp32c6/include/hal/pcnt_ll.h
View File

@ -92,7 +92,9 @@ static inline void pcnt_ll_set_level_action(pcnt_dev_t *hw, uint32_t unit, uint3
__attribute__((always_inline))
static inline int pcnt_ll_get_count(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_cnt_reg_t cnt_reg = hw->cnt_unit[unit];
pcnt_un_cnt_reg_t cnt_reg;
cnt_reg.val = hw->cnt_unit[unit].val;
int16_t value = cnt_reg.pulse_cnt;
return value;
}
@ -248,9 +250,11 @@ static inline void pcnt_ll_disable_all_events(pcnt_dev_t *hw, uint32_t unit)
*/
static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_h_lim = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@ -262,9 +266,11 @@ static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, i
*/
static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_l_lim = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@ -277,13 +283,15 @@ static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, in
*/
static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres, int value)
{
pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
conf1_reg.cnt_thres0 = value;
} else {
conf1_reg.cnt_thres1 = value;
}
hw->conf_unit[unit].conf1 = conf1_reg;
hw->conf_unit[unit].conf1.val = conf1_reg.val;
}
/**
@ -295,7 +303,9 @@ static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32
*/
static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_h_lim ;
return value;
}
@ -309,7 +319,9 @@ static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
*/
static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_l_lim ;
return value;
}
@ -325,7 +337,9 @@ static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
static inline int pcnt_ll_get_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres)
{
int16_t value;
pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
value = conf1_reg.cnt_thres0 ;
} else {
@ -356,7 +370,7 @@ static inline uint32_t pcnt_ll_get_unit_status(pcnt_dev_t *hw, uint32_t unit)
__attribute__((always_inline))
static inline pcnt_unit_zero_cross_mode_t pcnt_ll_get_zero_cross_mode(pcnt_dev_t *hw, uint32_t unit)
{
return hw->status_unit[unit].val & 0x03;
return (pcnt_unit_zero_cross_mode_t)(hw->status_unit[unit].val & 0x03);
}
/**

4
components/hal/esp32c6/include/hal/sdio_slave_ll.h
View File

@ -451,7 +451,7 @@ static inline void sdio_slave_ll_host_set_reg(host_dev_t* host, int pos, uint8_t
*/
static inline sdio_slave_hostint_t sdio_slave_ll_host_get_intena(host_dev_t* host)
{
return host->slc0host_func1_int_ena.val;
return (sdio_slave_hostint_t)host->slc0host_func1_int_ena.val;
}
/**
@ -507,7 +507,7 @@ static inline void sdio_slave_ll_slvint_set_ena(slc_dev_t *slc, const sdio_slave
*/
static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_ll_slvint_t *out_slv_int)
{
sdio_slave_ll_slvint_t slv_int = slc->slc0int_st.val & 0xff;
sdio_slave_ll_slvint_t slv_int = (sdio_slave_ll_slvint_t)(slc->slc0int_st.val & 0xff);
*out_slv_int = slv_int;
slc->slc0int_clr.val = slv_int;
}

2
components/hal/esp32c6/include/hal/spi_ll.h
View File

@ -64,7 +64,6 @@ typedef enum {
SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD.
SPI_LL_INTR_SEG_DONE = BIT(14),
} spi_ll_intr_t;
FLAG_ATTR(spi_ll_intr_t)
// Flags for conditions under which the transaction length should be recorded
typedef enum {
@ -73,7 +72,6 @@ typedef enum {
SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded
SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded
} spi_ll_trans_len_cond_t;
FLAG_ATTR(spi_ll_trans_len_cond_t)
// SPI base command
typedef enum {

12
components/hal/esp32c6/include/hal/spimem_flash_ll.h
View File

@ -399,12 +399,12 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -429,7 +429,9 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
*/
static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
switch (read_mode) {
@ -454,7 +456,7 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
default:
abort();
}
dev->ctrl = ctrl;
dev->ctrl.val = ctrl.val;
}
/**
@ -507,7 +509,7 @@ static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t comm
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

4
components/hal/esp32c6/include/hal/uart_ll.h
View File

@ -354,7 +354,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
*/
FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
hw->int_ena.val = hw->int_ena.val | mask;
}
/**
@ -367,7 +367,7 @@ FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
*/
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val &= (~mask);
hw->int_ena.val = hw->int_ena.val & (~mask);
}
/**

2
components/hal/esp32h2/include/hal/aes_ll.h
View File

@ -112,7 +112,7 @@ static inline void aes_ll_start_transform(void)
*/
static inline esp_aes_state_t aes_ll_get_state(void)
{
return REG_READ(AES_STATE_REG);
return (esp_aes_state_t)REG_READ(AES_STATE_REG);
}

12
components/hal/esp32h2/include/hal/cache_ll.h
View File

@ -165,12 +165,12 @@ __attribute__((always_inline))
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
HAL_ASSERT(cache_id == 0);
cache_bus_mask_t mask = 0;
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
//h2 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0;
mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
} else {
HAL_ASSERT(0); //Out of region
}
@ -194,11 +194,11 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
}
@ -216,11 +216,11 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
}

6
components/hal/esp32h2/include/hal/ecc_ll.h
View File

@ -157,7 +157,7 @@ static inline int ecc_ll_is_calc_finished(void)
static inline ecc_mode_t ecc_ll_get_mode(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE);
return (ecc_mode_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE));
}
static inline int ecc_ll_get_verification_result(void)
@ -167,12 +167,12 @@ static inline int ecc_ll_get_verification_result(void)
static inline ecc_curve_t ecc_ll_get_curve(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
return (ecc_curve_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH));
}
static inline ecc_mod_base_t ecc_ll_get_mod_base(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
return (ecc_mod_base_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE));
}
static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len)

2
components/hal/esp32h2/include/hal/ecdsa_ll.h
View File

@ -240,7 +240,7 @@ static inline void ecdsa_ll_set_stage(ecdsa_ll_stage_t stage)
*/
static inline ecdsa_ll_state_t ecdsa_ll_get_state(void)
{
return REG_GET_FIELD(ECDSA_STATE_REG, ECDSA_BUSY);
return (ecdsa_ll_state_t)(REG_GET_FIELD(ECDSA_STATE_REG, ECDSA_BUSY));
}
/**

16
components/hal/esp32h2/include/hal/gpspi_flash_ll.h
View File

@ -181,12 +181,12 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -211,8 +211,10 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
*/
static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->user) user = dev->user;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
typeof (dev->user) user;
user.val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
@ -244,8 +246,8 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
abort();
}
dev->ctrl = ctrl;
dev->user = user;
dev->ctrl.val = ctrl.val;
dev->user.val = user.val;
}
/**
@ -302,7 +304,7 @@ static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, u
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

12
components/hal/esp32h2/include/hal/i2c_ll.h
View File

@ -17,6 +17,7 @@
#include "soc/pcr_struct.h"
#include "hal/i2c_types.h"
#include "soc/clk_tree_defs.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -880,7 +881,9 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in
__attribute__((always_inline))
static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
i2c_int_status_reg_t int_sts = hw->int_status;
i2c_int_status_reg_t int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.arbitration_lost_int_st) {
*event = I2C_INTR_EVENT_ARBIT_LOST;
} else if (int_sts.nack_int_st) {
@ -907,7 +910,8 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even
__attribute__((always_inline))
static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.txfifo_wm_int_st) {
*event = I2C_INTR_EVENT_TXFIFO_EMPTY;
} else if (int_sts.trans_complete_int_st) {
@ -1048,8 +1052,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo
*/
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
{
*tx_mode = hw->ctr.tx_lsb_first;
*rx_mode = hw->ctr.rx_lsb_first;
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
*rx_mode = (i2c_trans_mode_t)(hw->ctr.rx_lsb_first);
}
/**

3
components/hal/esp32h2/include/hal/mcpwm_ll.h
View File

@ -1632,7 +1632,8 @@ static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id)
{
mcpwm_timer_cfg0_reg_t cfg0 = mcpwm->timer[timer_id].timer_cfg0;
mcpwm_timer_cfg0_reg_t cfg0;
cfg0.val = mcpwm->timer[timer_id].timer_cfg0.val;
return cfg0.timer_prescale + 1;
}

2
components/hal/esp32h2/include/hal/mpi_ll.h
View File

@ -7,6 +7,7 @@
#include <stdbool.h>
#include <string.h>
#include <sys/param.h>
#include "hal/assert.h"
#include "hal/mpi_types.h"
#include "soc/pcr_reg.h"
@ -17,6 +18,7 @@
extern "C" {
#endif
static inline size_t mpi_ll_calculate_hardware_words(size_t words)
{
return words;

1
components/hal/esp32h2/include/hal/mpu_ll.h
View File

@ -7,6 +7,7 @@
#include <stdint.h>
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {

36
components/hal/esp32h2/include/hal/pcnt_ll.h
View File

@ -92,7 +92,9 @@ static inline void pcnt_ll_set_level_action(pcnt_dev_t *hw, uint32_t unit, uint3
__attribute__((always_inline))
static inline int pcnt_ll_get_count(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_cnt_reg_t cnt_reg = hw->cnt_unit[unit];
pcnt_un_cnt_reg_t cnt_reg;
cnt_reg.val = hw->cnt_unit[unit].val;
int16_t value = cnt_reg.pulse_cnt;
return value;
}
@ -248,9 +250,11 @@ static inline void pcnt_ll_disable_all_events(pcnt_dev_t *hw, uint32_t unit)
*/
static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_h_lim = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@ -262,9 +266,11 @@ static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, i
*/
static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_l_lim = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@ -277,13 +283,15 @@ static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, in
*/
static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres, int value)
{
pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
conf1_reg.cnt_thres0 = value;
} else {
conf1_reg.cnt_thres1 = value;
}
hw->conf_unit[unit].conf1 = conf1_reg;
hw->conf_unit[unit].conf1.val = conf1_reg.val;
}
/**
@ -295,7 +303,9 @@ static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32
*/
static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_h_lim ;
return value;
}
@ -309,7 +319,9 @@ static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
*/
static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_l_lim ;
return value;
}
@ -325,7 +337,9 @@ static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
static inline int pcnt_ll_get_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres)
{
int16_t value;
pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
value = conf1_reg.cnt_thres0 ;
} else {
@ -356,7 +370,7 @@ static inline uint32_t pcnt_ll_get_unit_status(pcnt_dev_t *hw, uint32_t unit)
__attribute__((always_inline))
static inline pcnt_unit_zero_cross_mode_t pcnt_ll_get_zero_cross_mode(pcnt_dev_t *hw, uint32_t unit)
{
return hw->status_unit[unit].val & 0x03;
return (pcnt_unit_zero_cross_mode_t)(hw->status_unit[unit].val & 0x03);
}
/**

2
components/hal/esp32h2/include/hal/spi_ll.h
View File

@ -66,7 +66,6 @@ typedef enum {
SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD.
SPI_LL_INTR_SEG_DONE = BIT(14),
} spi_ll_intr_t;
FLAG_ATTR(spi_ll_intr_t)
// Flags for conditions under which the transaction length should be recorded
typedef enum {
@ -75,7 +74,6 @@ typedef enum {
SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded
SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded
} spi_ll_trans_len_cond_t;
FLAG_ATTR(spi_ll_trans_len_cond_t)
// SPI base command
typedef enum {

11
components/hal/esp32h2/include/hal/spimem_flash_ll.h
View File

@ -400,12 +400,12 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -430,7 +430,8 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
*/
static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
switch (read_mode) {
@ -455,7 +456,7 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
default:
abort();
}
dev->ctrl = ctrl;
dev->ctrl.val = ctrl.val;
}
__attribute__((always_inline))
@ -529,7 +530,7 @@ static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t comm
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

4
components/hal/esp32h2/include/hal/uart_ll.h
View File

@ -233,7 +233,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
*/
FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
hw->int_ena.val = hw->int_ena.val | mask;
}
/**
@ -246,7 +246,7 @@ FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
*/
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val &= (~mask);
hw->int_ena.val = hw->int_ena.val & (~mask);
}
/**

10
components/hal/esp32p4/include/hal/cache_ll.h
View File

@ -60,15 +60,15 @@ __attribute__((always_inline))
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
HAL_ASSERT(cache_id == 0 || cache_id == 1);
cache_bus_mask_t mask = 0;
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_DRAM_FLASH_ADDRESS_LOW && vaddr_end < SOC_DRAM_FLASH_ADDRESS_HIGH) {
mask |= CACHE_BUS_IBUS0;
mask |= CACHE_BUS_DBUS0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
} else if (vaddr_start >= SOC_DRAM_PSRAM_ADDRESS_LOW && vaddr_end < SOC_DRAM_PSRAM_ADDRESS_HIGH) {
mask |= CACHE_BUS_IBUS1;
mask |= CACHE_BUS_DBUS1;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS1);
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS1);
} else {
HAL_ASSERT(0); //Out of region
}

6
components/hal/esp32p4/include/hal/clk_tree_ll.h
View File

@ -419,7 +419,7 @@ static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_tar
*/
static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void)
{
return 0;
return (soc_rtc_slow_clk_src_t)0;
}
/**
@ -439,7 +439,7 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rt
*/
static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
{
return 0;
return (soc_rtc_slow_clk_src_t)0;
}
/**
@ -459,7 +459,7 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rt
*/
static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
{
return 0;
return (soc_rtc_fast_clk_src_t)0;
}
/**

6
components/hal/esp32p4/include/hal/ecc_ll.h
View File

@ -157,7 +157,7 @@ static inline int ecc_ll_is_calc_finished(void)
static inline ecc_mode_t ecc_ll_get_mode(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE);
return (ecc_mode_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE));
}
static inline int ecc_ll_get_verification_result(void)
@ -167,12 +167,12 @@ static inline int ecc_ll_get_verification_result(void)
static inline ecc_curve_t ecc_ll_get_curve(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
return (ecc_curve_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH));
}
static inline ecc_mod_base_t ecc_ll_get_mod_base(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
return (ecc_mod_base_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE));
}
static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len)

18
components/hal/esp32p4/include/hal/gpspi_flash_ll.h
View File

@ -187,12 +187,12 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -217,8 +217,10 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
*/
static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->user) user = dev->user;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
typeof (dev->user) user;
user.val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
@ -250,8 +252,8 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
abort();
}
dev->ctrl = ctrl;
dev->user = user;
dev->ctrl.val = ctrl.val;
dev->user.val = user.val;
}
/**
@ -262,7 +264,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
*/
static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock_reg_t *clock_val)
{
dev->clock = *clock_val;
dev->clock.val = (*clock_val).val;
}
/**
@ -308,7 +310,7 @@ static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, u
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

12
components/hal/esp32p4/include/hal/i2c_ll.h
View File

@ -17,6 +17,7 @@
#include "hal/i2c_types.h"
#include "soc/clk_tree_defs.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -926,7 +927,9 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in
__attribute__((always_inline))
static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
i2c_int_status_reg_t int_sts = hw->int_status;
i2c_int_status_reg_t int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.arbitration_lost_int_st) {
*event = I2C_INTR_EVENT_ARBIT_LOST;
} else if (int_sts.nack_int_st) {
@ -953,7 +956,8 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even
__attribute__((always_inline))
static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.txfifo_wm_int_st) {
*event = I2C_INTR_EVENT_TXFIFO_EMPTY;
} else if (int_sts.trans_complete_int_st) {
@ -1094,8 +1098,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo
*/
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
{
*tx_mode = hw->ctr.tx_lsb_first;
*rx_mode = hw->ctr.rx_lsb_first;
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
*rx_mode = (i2c_trans_mode_t)(hw->ctr.rx_lsb_first);
}
/**

3
components/hal/esp32p4/include/hal/mcpwm_ll.h
View File

@ -1699,7 +1699,8 @@ static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id)
{
mcpwm_timer_cfg0_reg_t cfg0 = mcpwm->timer[timer_id].timer_cfg0;
mcpwm_timer_cfg0_reg_t cfg0;
cfg0.val = mcpwm->timer[timer_id].timer_cfg0.val;
return cfg0.timer_prescale + 1;
}

2
components/hal/esp32p4/include/hal/mpi_ll.h
View File

@ -7,6 +7,7 @@
#include <stdbool.h>
#include <string.h>
#include <sys/param.h>
#include "hal/assert.h"
#include "hal/mpi_types.h"
#include "soc/rsa_reg.h"
@ -16,6 +17,7 @@
extern "C" {
#endif
static inline size_t mpi_ll_calculate_hardware_words(size_t words)
{
return words;

1
components/hal/esp32p4/include/hal/mpu_ll.h
View File

@ -7,6 +7,7 @@
#include <stdint.h>
#include "soc/soc_caps.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {

36
components/hal/esp32p4/include/hal/pcnt_ll.h
View File

@ -93,7 +93,9 @@ static inline void pcnt_ll_set_level_action(pcnt_dev_t *hw, uint32_t unit, uint3
__attribute__((always_inline))
static inline int pcnt_ll_get_count(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_cnt_reg_t cnt_reg = hw->cnt_unit[unit];
pcnt_un_cnt_reg_t cnt_reg;
cnt_reg.val = hw->cnt_unit[unit].val;
int16_t value = cnt_reg.pulse_cnt;
return value;
}
@ -289,9 +291,11 @@ static inline void pcnt_ll_disable_all_events(pcnt_dev_t *hw, uint32_t unit)
*/
static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_h_lim = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@ -303,9 +307,11 @@ static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, i
*/
static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_l_lim = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@ -318,13 +324,15 @@ static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, in
*/
static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres, int value)
{
pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
conf1_reg.cnt_thres0 = value;
} else {
conf1_reg.cnt_thres1 = value;
}
hw->conf_unit[unit].conf1 = conf1_reg;
hw->conf_unit[unit].conf1.val = conf1_reg.val;
}
/**
@ -336,7 +344,9 @@ static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32
*/
static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_h_lim ;
return value;
}
@ -350,7 +360,9 @@ static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
*/
static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_l_lim ;
return value;
}
@ -366,7 +378,9 @@ static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
static inline int pcnt_ll_get_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres)
{
int16_t value;
pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
value = conf1_reg.cnt_thres0 ;
} else {
@ -397,7 +411,7 @@ static inline uint32_t pcnt_ll_get_unit_status(pcnt_dev_t *hw, uint32_t unit)
__attribute__((always_inline))
static inline pcnt_unit_zero_cross_mode_t pcnt_ll_get_zero_cross_mode(pcnt_dev_t *hw, uint32_t unit)
{
return hw->status_unit[unit].val & 0x03;
return (pcnt_unit_zero_cross_mode_t)(hw->status_unit[unit].val & 0x03);
}
/**

11
components/hal/esp32p4/include/hal/spimem_flash_ll.h
View File

@ -404,12 +404,12 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -434,7 +434,8 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
*/
static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
switch (read_mode) {
@ -459,7 +460,7 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
default:
abort();
}
dev->ctrl = ctrl;
dev->ctrl.val = ctrl.val;
}
/**
@ -512,7 +513,7 @@ static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t comm
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

2
components/hal/esp32s2/include/hal/aes_ll.h
View File

@ -123,7 +123,7 @@ static inline void aes_ll_cont_transform(void)
*/
static inline esp_aes_state_t aes_ll_get_state(void)
{
return REG_READ(AES_STATE_REG);
return (esp_aes_state_t)REG_READ(AES_STATE_REG);
}

68
components/hal/esp32s2/include/hal/cache_ll.h
View File

@ -418,35 +418,35 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
{
(void)cache_id;
cache_bus_mask_t mask = 0;
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM1_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS1;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS1);
} else if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS0;
mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
} else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_DBUS0;
mask |= (vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
} else if (vaddr_start >= SOC_DRAM1_ADDRESS_LOW) {
mask |= CACHE_BUS_DBUS1;
mask |= (vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS1);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
} else if (vaddr_start >= SOC_DPORT_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_DBUS2;
mask |= (vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0;
mask |= (vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS2);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
} else if (vaddr_start >= SOC_DROM0_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS2;
mask |= (vaddr_end >= SOC_DPORT_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS2 : 0;
mask |= (vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0;
mask |= (vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS2);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DPORT_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS2 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
} else {
abort();
}
@ -468,15 +468,15 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
(void)cache_id;
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0;
ibus_mask |= (mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0;
ibus_mask |= (mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0);
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0);
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0;
dbus_mask |= (mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0;
dbus_mask |= (mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0);
REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
}
@ -492,15 +492,15 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
(void)cache_id;
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0;
ibus_mask |= (mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0;
ibus_mask |= (mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0);
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0);
REG_SET_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0;
dbus_mask |= (mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0;
dbus_mask |= (mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0);
REG_SET_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
}

2
components/hal/esp32s2/include/hal/dedic_gpio_ll.h
View File

@ -31,8 +31,8 @@ static inline void dedic_gpio_ll_write_all(dedic_dev_t *dev, uint32_t value)
static inline void dedic_gpio_ll_write_mask(dedic_dev_t *dev, uint32_t channel_mask, uint32_t value)
{
dedic_gpio_out_msk_reg_t d = {
.gpio_out_value = value,
.gpio_out_msk = channel_mask,
.gpio_out_value = value
};
dev->gpio_out_msk.val = d.val;
}

16
components/hal/esp32s2/include/hal/gpspi_flash_ll.h
View File

@ -175,12 +175,12 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -209,8 +209,10 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
*/
static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->user) user = dev->user;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
typeof (dev->user) user;
user.val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
@ -242,8 +244,8 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
abort();
}
dev->ctrl = ctrl;
dev->user = user;
dev->ctrl.val = ctrl.val;
dev->user.val = user.val;
}
/**
@ -296,7 +298,7 @@ static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, u
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

12
components/hal/esp32s2/include/hal/i2c_ll.h
View File

@ -13,13 +13,13 @@
#include "soc/clk_tree_defs.h"
#include "hal/i2c_types.h"
#include "esp_attr.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief I2C hardware cmd register fields.
*/
@ -815,7 +815,8 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in
__attribute__((always_inline))
static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.arbitration_lost) {
*event = I2C_INTR_EVENT_ARBIT_LOST;
} else if (int_sts.nack) {
@ -842,7 +843,8 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even
__attribute__((always_inline))
static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.tx_fifo_wm) {
*event = I2C_INTR_EVENT_TXFIFO_EMPTY;
} else if (int_sts.trans_complete) {
@ -984,8 +986,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo
*/
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
{
*tx_mode = hw->ctr.tx_lsb_first;
*rx_mode = hw->ctr.rx_lsb_first;
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
*rx_mode = (i2c_trans_mode_t)(hw->ctr.rx_lsb_first);
}
/**

2
components/hal/esp32s2/include/hal/ledc_ll.h
View File

@ -538,7 +538,7 @@ static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_
*/
static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel)
{
*timer_sel = hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel;
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
#ifdef __cplusplus

1
components/hal/esp32s2/include/hal/memprot_peri_ll.h
View File

@ -11,6 +11,7 @@
#include "soc/dport_access.h"
#include "soc/periph_defs.h"
#include "hal/memprot_types.h"
#include "hal/memprot_ll.h"
#ifdef __cplusplus
extern "C" {

2
components/hal/esp32s2/include/hal/mpi_ll.h
View File

@ -7,6 +7,7 @@
#include <stdbool.h>
#include <string.h>
#include <sys/param.h>
#include "hal/assert.h"
#include "hal/mpi_types.h"
#include "soc/hwcrypto_periph.h"
@ -17,6 +18,7 @@
extern "C" {
#endif
static inline size_t mpi_ll_calculate_hardware_words(size_t words)
{
return words;

36
components/hal/esp32s2/include/hal/pcnt_ll.h
View File

@ -92,7 +92,9 @@ static inline void pcnt_ll_set_level_action(pcnt_dev_t *hw, uint32_t unit, uint3
__attribute__((always_inline))
static inline int pcnt_ll_get_count(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_cnt_reg_t cnt_reg = hw->cnt_unit[unit];
pcnt_un_cnt_reg_t cnt_reg;
cnt_reg.val = hw->cnt_unit[unit].val;
int16_t value = cnt_reg.pulse_cnt_un;
return value;
}
@ -248,9 +250,11 @@ static inline void pcnt_ll_disable_all_events(pcnt_dev_t *hw, uint32_t unit)
*/
static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_h_lim_un = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@ -262,9 +266,11 @@ static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, i
*/
static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_l_lim_un = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@ -277,13 +283,15 @@ static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, in
*/
static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres, int value)
{
pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
conf1_reg.cnt_thres0_un = value;
} else {
conf1_reg.cnt_thres1_un = value;
}
hw->conf_unit[unit].conf1 = conf1_reg;
hw->conf_unit[unit].conf1.val = conf1_reg.val;
}
/**
@ -295,7 +303,9 @@ static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32
*/
static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_h_lim_un;
return value;
}
@ -309,7 +319,9 @@ static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
*/
static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_l_lim_un;
return value;
}
@ -325,7 +337,9 @@ static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
static inline int pcnt_ll_get_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres)
{
int16_t value;
pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
value = conf1_reg.cnt_thres0_un;
} else {
@ -356,7 +370,7 @@ static inline uint32_t pcnt_ll_get_unit_status(pcnt_dev_t *hw, uint32_t unit)
__attribute__((always_inline))
static inline pcnt_unit_zero_cross_mode_t pcnt_ll_get_zero_cross_mode(pcnt_dev_t *hw, uint32_t unit)
{
return hw->status_unit[unit].val & 0x03;
return (pcnt_unit_zero_cross_mode_t)(hw->status_unit[unit].val & 0x03);
}
/**

2
components/hal/esp32s2/include/hal/spi_ll.h
View File

@ -73,7 +73,6 @@ typedef enum {
SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD.
SPI_LL_INTR_SEG_DONE = BIT(14),
} spi_ll_intr_t;
FLAG_ATTR(spi_ll_intr_t)
///< Flags for conditions under which the transaction length should be recorded
typedef enum {
@ -82,7 +81,6 @@ typedef enum {
SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded
SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded
} spi_ll_trans_len_cond_t;
FLAG_ATTR(spi_ll_trans_len_cond_t)
// SPI base command in esp32s2
typedef enum {

11
components/hal/esp32s2/include/hal/spimem_flash_ll.h
View File

@ -339,12 +339,12 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -369,7 +369,8 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
*/
static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
switch (read_mode) {
@ -394,7 +395,7 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
default:
abort();
}
dev->ctrl = ctrl;
dev->ctrl.val = ctrl.val;
}
/**
@ -447,7 +448,7 @@ static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t comm
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

20
components/hal/esp32s2/include/hal/touch_sensor_ll.h
View File

@ -460,7 +460,7 @@ static inline void touch_ll_set_idle_channel_connect(touch_pad_conn_type_t type)
*/
static inline void touch_ll_get_idle_channel_connect(touch_pad_conn_type_t *type)
{
*type = RTCCNTL.touch_scan_ctrl.touch_inactive_connection;
*type = (touch_pad_conn_type_t)(RTCCNTL.touch_scan_ctrl.touch_inactive_connection);
}
/**
@ -707,7 +707,7 @@ static inline void touch_ll_filter_set_smooth_mode(touch_smooth_mode_t mode)
*/
static inline void touch_ll_filter_get_smooth_mode(touch_smooth_mode_t *mode)
{
*mode = RTCCNTL.touch_filter_ctrl.touch_smooth_lvl;
*mode = (touch_smooth_mode_t)(RTCCNTL.touch_filter_ctrl.touch_smooth_lvl);
}
/**
@ -849,7 +849,7 @@ static inline void touch_ll_denoise_set_cap_level(touch_pad_denoise_cap_t cap_le
*/
static inline void touch_ll_denoise_get_cap_level(touch_pad_denoise_cap_t *cap_level)
{
*cap_level = RTCCNTL.touch_ctrl2.touch_refc;
*cap_level = (touch_pad_denoise_cap_t)(RTCCNTL.touch_ctrl2.touch_refc);
}
/**
@ -871,7 +871,7 @@ static inline void touch_ll_denoise_set_grade(touch_pad_denoise_grade_t grade)
*/
static inline void touch_ll_denoise_get_grade(touch_pad_denoise_grade_t *grade)
{
*grade = RTCCNTL.touch_scan_ctrl.touch_denoise_res;
*grade = (touch_pad_denoise_grade_t)(RTCCNTL.touch_scan_ctrl.touch_denoise_res);
}
/**
@ -903,7 +903,7 @@ static inline void touch_ll_waterproof_set_guard_pad(touch_pad_t pad_num)
*/
static inline void touch_ll_waterproof_get_guard_pad(touch_pad_t *pad_num)
{
*pad_num = RTCCNTL.touch_scan_ctrl.touch_out_ring;
*pad_num = (touch_pad_t)(RTCCNTL.touch_scan_ctrl.touch_out_ring);
}
/**
@ -927,7 +927,7 @@ static inline void touch_ll_waterproof_set_sheild_driver(touch_pad_shield_driver
*/
static inline void touch_ll_waterproof_get_sheild_driver(touch_pad_shield_driver_t *driver_level)
{
*driver_level = RTCCNTL.touch_scan_ctrl.touch_bufdrv;
*driver_level = (touch_pad_shield_driver_t)(RTCCNTL.touch_scan_ctrl.touch_bufdrv);
}
/**
@ -974,9 +974,9 @@ static inline void touch_ll_proximity_set_channel_num(const touch_pad_t prox_pad
*/
static inline void touch_ll_proximity_get_channel_num(touch_pad_t prox_pad[])
{
prox_pad[0] = SENS.sar_touch_conf.touch_approach_pad0;
prox_pad[1] = SENS.sar_touch_conf.touch_approach_pad1;
prox_pad[2] = SENS.sar_touch_conf.touch_approach_pad2;
prox_pad[0] = (touch_pad_t)(SENS.sar_touch_conf.touch_approach_pad0);
prox_pad[1] = (touch_pad_t)(SENS.sar_touch_conf.touch_approach_pad1);
prox_pad[2] = (touch_pad_t)(SENS.sar_touch_conf.touch_approach_pad2);
}
/**
@ -1052,7 +1052,7 @@ static inline void touch_ll_sleep_set_channel_num(touch_pad_t touch_num)
*/
static inline void touch_ll_sleep_get_channel_num(touch_pad_t *touch_num)
{
*touch_num = RTCCNTL.touch_slp_thres.touch_slp_pad;
*touch_num = (touch_pad_t)(RTCCNTL.touch_slp_thres.touch_slp_pad);
}
/**

4
components/hal/esp32s2/include/hal/uart_ll.h
View File

@ -143,7 +143,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
*/
FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
hw->int_ena.val = hw->int_ena.val | mask;
}
/**
@ -156,7 +156,7 @@ FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
*/
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val &= (~mask);
hw->int_ena.val = hw->int_ena.val & (~mask);
}
/**

5
components/hal/esp32s2/include/hal/usb_ll.h
View File

@ -28,13 +28,14 @@ static inline void usb_ll_ext_phy_enable(void)
static inline void usb_ll_int_phy_pullup_conf(bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
{
usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
usb_wrap_otg_conf_reg_t conf;
conf.val = USB_WRAP.otg_conf.val;
conf.pad_pull_override = 1;
conf.dp_pullup = dp_pu;
conf.dp_pulldown = dp_pd;
conf.dm_pullup = dm_pu;
conf.dm_pulldown = dm_pd;
USB_WRAP.otg_conf = conf;
USB_WRAP.otg_conf.val = conf.val;
}
#ifdef __cplusplus

5
components/hal/esp32s2/include/hal/usb_phy_ll.h
View File

@ -49,13 +49,14 @@ static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
*/
static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
{
usb_wrap_otg_conf_reg_t conf = hw->otg_conf;
usb_wrap_otg_conf_reg_t conf;
conf.val = hw->otg_conf.val;
conf.pad_pull_override = 1;
conf.dp_pullup = dp_pu;
conf.dp_pulldown = dp_pd;
conf.dm_pullup = dm_pu;
conf.dm_pulldown = dm_pd;
hw->otg_conf = conf;
hw->otg_conf.val = conf.val;
}
/**

2
components/hal/esp32s3/include/hal/aes_ll.h
View File

@ -112,7 +112,7 @@ static inline void aes_ll_start_transform(void)
*/
static inline esp_aes_state_t aes_ll_get_state(void)
{
return REG_READ(AES_STATE_REG);
return (esp_aes_state_t)REG_READ(AES_STATE_REG);
}

32
components/hal/esp32s3/include/hal/cache_ll.h
View File

@ -510,12 +510,12 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
{
HAL_ASSERT(cache_id == 0 || cache_id == 1);
cache_bus_mask_t mask = 0;
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_IBUS0; //Both cores have their own IBUS0
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0); //Both cores have their own IBUS0
} else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_DBUS0; //Both cores have their own DBUS0
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0); //Both cores have their own DBUS0
} else {
HAL_ASSERT(0); //Out of region
}
@ -540,17 +540,17 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
uint32_t ibus_mask = 0;
if (cache_id == 0) {
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0);
} else {
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0);
}
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
if (cache_id == 1) {
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0);
} else {
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0);
}
REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask);
}
@ -565,22 +565,22 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
__attribute__((always_inline))
static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
{
cache_bus_mask_t mask = 0;
cache_bus_mask_t mask = (cache_bus_mask_t)0;
HAL_ASSERT(cache_id == 0 || cache_id == 1);
//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
uint32_t ibus_mask = REG_READ(EXTMEM_ICACHE_CTRL1_REG);
if (cache_id == 0) {
mask |= (!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_IBUS0 : 0;
mask = (cache_bus_mask_t)(mask | ((!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_IBUS0 : 0));
} else {
mask |= (!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_IBUS0 : 0;
mask = (cache_bus_mask_t)(mask | ((!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_IBUS0 : 0));
}
uint32_t dbus_mask = REG_READ(EXTMEM_DCACHE_CTRL1_REG);
if (cache_id == 1) {
mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_DBUS0 : 0;
mask = (cache_bus_mask_t)(mask | ((!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_DBUS0 : 0));
} else {
mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_DBUS0 : 0;
mask = (cache_bus_mask_t)(mask | ((!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_DBUS0 : 0));
}
return mask;
@ -601,17 +601,17 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
uint32_t ibus_mask = 0;
if (cache_id == 0) {
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0);
} else {
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0);
}
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
if (cache_id == 1) {
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0);
} else {
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0);
}
REG_SET_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask);
}

16
components/hal/esp32s3/include/hal/gpspi_flash_ll.h
View File

@ -186,12 +186,12 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -216,8 +216,10 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
*/
static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->user) user = dev->user;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
typeof (dev->user) user;
user.val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
@ -249,8 +251,8 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
abort();
}
dev->ctrl = ctrl;
dev->user = user;
dev->ctrl.val = ctrl.val;
dev->user.val = user.val;
}
/**
@ -307,7 +309,7 @@ static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, u
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

11
components/hal/esp32s3/include/hal/i2c_ll.h
View File

@ -18,6 +18,7 @@
#include "hal/i2c_types.h"
#include "esp_attr.h"
#include "esp_assert.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -867,7 +868,8 @@ static inline void i2c_ll_set_scl_clk_timing(i2c_dev_t *hw, int high_period, int
__attribute__((always_inline))
static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.arbitration_lost_int_st) {
*event = I2C_INTR_EVENT_ARBIT_LOST;
} else if (int_sts.nack_int_st) {
@ -894,7 +896,8 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even
__attribute__((always_inline))
static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.txfifo_wm_int_st) {
*event = I2C_INTR_EVENT_TXFIFO_EMPTY;
} else if (int_sts.trans_complete_int_st) {
@ -1036,8 +1039,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int high_period, int low
*/
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
{
*tx_mode = hw->ctr.tx_lsb_first;
*rx_mode = hw->ctr.rx_lsb_first;
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
*rx_mode = (i2c_trans_mode_t)(hw->ctr.rx_lsb_first);
}
/**

2
components/hal/esp32s3/include/hal/ledc_ll.h
View File

@ -507,7 +507,7 @@ static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_
*/
static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel)
{
*timer_sel = hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel;
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
#ifdef __cplusplus

3
components/hal/esp32s3/include/hal/mcpwm_ll.h
View File

@ -1596,7 +1596,8 @@ static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id)
{
mcpwm_timer_cfg0_reg_t cfg0 = mcpwm->timer[timer_id].timer_cfg0;
mcpwm_timer_cfg0_reg_t cfg0;
cfg0.val = mcpwm->timer[timer_id].timer_cfg0.val;
return cfg0.timer_prescale + 1;
}

17
components/hal/esp32s3/include/hal/memprot_ll.h
View File

@ -177,7 +177,13 @@ static inline uint32_t memprot_ll_get_iram0_split_line_main_I_1_regval(void)
static inline void memprot_ll_prepare_iram0_split_line_regval(const uint32_t addr, uint32_t* regval)
{
//set category bits for given split line
uint32_t cat[7] = {[0 ... 6]=MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA};
uint32_t cat[7] = { MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA,
MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA,
MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA,
MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA,
MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA,
MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA,
MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA };
for (size_t x=0; x<7; x++) {
if (addr <= SRAM_RG3_LEVEL_HLIMITS(x)) {
cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA;
@ -1251,7 +1257,14 @@ static inline uint32_t memprot_ll_get_dram0_split_line_main_D_1_regval(void)
static inline void memprot_ll_prepare_dram0_split_line_regval(const uint32_t addr, uint32_t* regval)
{
//set category bits for given split line
uint32_t cat[7] = {[0 ... 6]=MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA};
uint32_t cat[7] = { MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA,
MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA,
MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA,
MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA,
MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA,
MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA,
MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA };
for (size_t x=0; x<7; x++) {
if (addr <= MAP_IRAM_TO_DRAM(SRAM_RG3_LEVEL_HLIMITS(x))) {
cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA;

2
components/hal/esp32s3/include/hal/mpi_ll.h
View File

@ -7,6 +7,7 @@
#include <stdbool.h>
#include <string.h>
#include <sys/param.h>
#include "hal/assert.h"
#include "hal/mpi_types.h"
#include "soc/hwcrypto_periph.h"
@ -17,6 +18,7 @@
extern "C" {
#endif
static inline size_t mpi_ll_calculate_hardware_words(size_t words)
{
return words;

2
components/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h
View File

@ -259,7 +259,7 @@ static inline mspi_timing_ll_flash_mode_t mspi_timing_ll_get_flash_mode(uint8_t
return MSPI_TIMING_LL_FLASH_SLOW_MODE;
default:
HAL_ASSERT(false);
return 0;
return (mspi_timing_ll_flash_mode_t)0;
}
}

36
components/hal/esp32s3/include/hal/pcnt_ll.h
View File

@ -92,7 +92,9 @@ static inline void pcnt_ll_set_level_action(pcnt_dev_t *hw, uint32_t unit, uint3
__attribute__((always_inline))
static inline int pcnt_ll_get_count(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_cnt_reg_t cnt_reg = hw->cnt_unit[unit];
pcnt_un_cnt_reg_t cnt_reg;
cnt_reg.val = hw->cnt_unit[unit].val;
int16_t value = cnt_reg.pulse_cnt_un;
return value;
}
@ -248,9 +250,11 @@ static inline void pcnt_ll_disable_all_events(pcnt_dev_t *hw, uint32_t unit)
*/
static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_h_lim_un = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@ -262,9 +266,11 @@ static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, i
*/
static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_l_lim_un = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@ -277,13 +283,15 @@ static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, in
*/
static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres, int value)
{
pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
conf1_reg.cnt_thres0_un = value;
} else {
conf1_reg.cnt_thres1_un = value;
}
hw->conf_unit[unit].conf1 = conf1_reg;
hw->conf_unit[unit].conf1.val = conf1_reg.val;
}
/**
@ -295,7 +303,9 @@ static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32
*/
static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_h_lim_un;
return value;
}
@ -309,7 +319,9 @@ static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
*/
static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_l_lim_un;
return value;
}
@ -325,7 +337,9 @@ static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
static inline int pcnt_ll_get_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres)
{
int16_t value;
pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
value = conf1_reg.cnt_thres0_un;
} else {
@ -356,7 +370,7 @@ static inline uint32_t pcnt_ll_get_unit_status(pcnt_dev_t *hw, uint32_t unit)
__attribute__((always_inline))
static inline pcnt_unit_zero_cross_mode_t pcnt_ll_get_zero_cross_mode(pcnt_dev_t *hw, uint32_t unit)
{
return hw->status_unit[unit].val & 0x03;
return (pcnt_unit_zero_cross_mode_t)((hw->status_unit[unit].val) & 0x03);
}
/**

2
components/hal/esp32s3/include/hal/spi_ll.h
View File

@ -65,7 +65,6 @@ typedef enum {
SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD.
SPI_LL_INTR_SEG_DONE = BIT(14),
} spi_ll_intr_t;
FLAG_ATTR(spi_ll_intr_t)
// Flags for conditions under which the transaction length should be recorded
typedef enum {
@ -74,7 +73,6 @@ typedef enum {
SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded
SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded
} spi_ll_trans_len_cond_t;
FLAG_ATTR(spi_ll_trans_len_cond_t)
// SPI base command in esp32s3
typedef enum {

12
components/hal/esp32s3/include/hal/spimem_flash_ll.h
View File

@ -396,12 +396,12 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@ -426,7 +426,9 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
*/
static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M | SPI_MEM_FCMD_OCT | SPI_MEM_FADDR_OCT | SPI_MEM_FDIN_OCT | SPI_MEM_FDOUT_OCT);
dev->ddr.fmem_ddr_en = 0;
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
@ -465,7 +467,7 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
default:
abort();
}
dev->ctrl = ctrl;
dev->ctrl.val = ctrl.val;
}
/**
@ -518,7 +520,7 @@ static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t comm
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**

24
components/hal/esp32s3/include/hal/touch_sensor_ll.h
View File

@ -186,9 +186,9 @@ static inline void touch_ll_set_slope(touch_pad_t touch_num, touch_cnt_slope_t s
static inline void touch_ll_get_slope(touch_pad_t touch_num, touch_cnt_slope_t *slope)
{
if (touch_num < TOUCH_PAD_NUM10) {
*slope = GET_PERI_REG_BITS2(RTC_CNTL_TOUCH_DAC_REG, RTC_CNTL_TOUCH_PAD0_DAC_V, (RTC_CNTL_TOUCH_PAD0_DAC_S - touch_num * 3));
*slope = (touch_cnt_slope_t)(GET_PERI_REG_BITS2(RTC_CNTL_TOUCH_DAC_REG, RTC_CNTL_TOUCH_PAD0_DAC_V, (RTC_CNTL_TOUCH_PAD0_DAC_S - touch_num * 3)));
} else {
*slope = GET_PERI_REG_BITS2(RTC_CNTL_TOUCH_DAC1_REG, RTC_CNTL_TOUCH_PAD10_DAC_V, (RTC_CNTL_TOUCH_PAD10_DAC_S - (touch_num - TOUCH_PAD_NUM10) * 3));
*slope = (touch_cnt_slope_t)(GET_PERI_REG_BITS2(RTC_CNTL_TOUCH_DAC1_REG, RTC_CNTL_TOUCH_PAD10_DAC_V, (RTC_CNTL_TOUCH_PAD10_DAC_S - (touch_num - TOUCH_PAD_NUM10) * 3)));
}
}
@ -468,7 +468,7 @@ static inline void touch_ll_set_idle_channel_connect(touch_pad_conn_type_t type)
*/
static inline void touch_ll_get_idle_channel_connect(touch_pad_conn_type_t *type)
{
*type = RTCCNTL.touch_scan_ctrl.touch_inactive_connection;
*type = (touch_pad_conn_type_t)(RTCCNTL.touch_scan_ctrl.touch_inactive_connection);
}
/**
@ -727,7 +727,7 @@ static inline void touch_ll_filter_set_smooth_mode(touch_smooth_mode_t mode)
*/
static inline void touch_ll_filter_get_smooth_mode(touch_smooth_mode_t *mode)
{
*mode = RTCCNTL.touch_filter_ctrl.touch_smooth_lvl;
*mode = (touch_smooth_mode_t)(RTCCNTL.touch_filter_ctrl.touch_smooth_lvl);
}
/**
@ -869,7 +869,7 @@ static inline void touch_ll_denoise_set_cap_level(touch_pad_denoise_cap_t cap_le
*/
static inline void touch_ll_denoise_get_cap_level(touch_pad_denoise_cap_t *cap_level)
{
*cap_level = RTCCNTL.touch_ctrl2.touch_refc;
*cap_level = (touch_pad_denoise_cap_t)(RTCCNTL.touch_ctrl2.touch_refc);
}
/**
@ -891,7 +891,7 @@ static inline void touch_ll_denoise_set_grade(touch_pad_denoise_grade_t grade)
*/
static inline void touch_ll_denoise_get_grade(touch_pad_denoise_grade_t *grade)
{
*grade = RTCCNTL.touch_scan_ctrl.touch_denoise_res;
*grade = (touch_pad_denoise_grade_t)(RTCCNTL.touch_scan_ctrl.touch_denoise_res);
}
/**
@ -923,7 +923,7 @@ static inline void touch_ll_waterproof_set_guard_pad(touch_pad_t pad_num)
*/
static inline void touch_ll_waterproof_get_guard_pad(touch_pad_t *pad_num)
{
*pad_num = RTCCNTL.touch_scan_ctrl.touch_out_ring;
*pad_num = (touch_pad_t)(RTCCNTL.touch_scan_ctrl.touch_out_ring);
}
/**
@ -947,7 +947,7 @@ static inline void touch_ll_waterproof_set_sheild_driver(touch_pad_shield_driver
*/
static inline void touch_ll_waterproof_get_sheild_driver(touch_pad_shield_driver_t *driver_level)
{
*driver_level = RTCCNTL.touch_scan_ctrl.touch_bufdrv;
*driver_level = (touch_pad_shield_driver_t)(RTCCNTL.touch_scan_ctrl.touch_bufdrv);
}
/**
@ -994,9 +994,9 @@ static inline void touch_ll_proximity_set_channel_num(const touch_pad_t prox_pad
*/
static inline void touch_ll_proximity_get_channel_num(touch_pad_t prox_pad[])
{
prox_pad[0] = SENS.sar_touch_conf.touch_approach_pad0;
prox_pad[1] = SENS.sar_touch_conf.touch_approach_pad1;
prox_pad[2] = SENS.sar_touch_conf.touch_approach_pad2;
prox_pad[0] = (touch_pad_t)(SENS.sar_touch_conf.touch_approach_pad0);
prox_pad[1] = (touch_pad_t)(SENS.sar_touch_conf.touch_approach_pad1);
prox_pad[2] = (touch_pad_t)(SENS.sar_touch_conf.touch_approach_pad2);
}
/**
@ -1072,7 +1072,7 @@ static inline void touch_ll_sleep_set_channel_num(touch_pad_t touch_num)
*/
static inline void touch_ll_sleep_get_channel_num(touch_pad_t *touch_num)
{
*touch_num = RTCCNTL.touch_slp_thres.touch_slp_pad;
*touch_num = (touch_pad_t)(RTCCNTL.touch_slp_thres.touch_slp_pad);
}
/**

4
components/hal/esp32s3/include/hal/uart_ll.h
View File

@ -172,7 +172,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
*/
FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
hw->int_ena.val = hw->int_ena.val | mask;
}
/**
@ -185,7 +185,7 @@ FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
*/
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val &= (~mask);
hw->int_ena.val = hw->int_ena.val & (~mask);
}
/**

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