From 473f39c31f00ed14dded0fc46dd165afe5552cc9 Mon Sep 17 00:00:00 2001 From: wanckl Date: Fri, 30 Aug 2024 15:41:11 +0800 Subject: [PATCH] fix(driver_spi): move macro GPIO_MATRIX_DELAY_NS out from soc.h --- components/hal/esp32/include/hal/gpio_ll.h | 3 +++ components/hal/esp32c2/include/hal/spi_ll.h | 8 ++++---- components/hal/esp32c3/include/hal/spi_ll.h | 2 +- components/hal/esp32c5/include/hal/spi_ll.h | 2 +- components/hal/esp32c6/include/hal/spi_ll.h | 2 +- components/hal/esp32h2/include/hal/spi_ll.h | 2 +- components/hal/esp32p4/include/hal/spi_ll.h | 4 ++-- components/hal/esp32s2/include/hal/spi_ll.h | 2 +- components/hal/esp32s3/include/hal/spi_ll.h | 2 +- components/hal/spi_flash_hal.c | 8 ++++++-- components/hal/spi_hal.c | 11 +++++++++-- components/soc/esp32/include/soc/soc.h | 1 - components/soc/esp32c2/include/soc/soc.h | 1 - components/soc/esp32c3/include/soc/soc.h | 1 - components/soc/esp32c5/include/soc/soc.h | 1 - components/soc/esp32c6/include/soc/soc.h | 1 - components/soc/esp32c61/include/soc/soc.h | 1 - components/soc/esp32h2/include/soc/soc.h | 1 - components/soc/esp32p4/include/soc/soc.h | 1 - components/soc/esp32s2/include/soc/soc.h | 1 - components/soc/esp32s3/include/soc/soc.h | 1 - 21 files changed, 30 insertions(+), 26 deletions(-) diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h index 6ab6dfd4da..4728683903 100644 --- a/components/hal/esp32/include/hal/gpio_ll.h +++ b/components/hal/esp32/include/hal/gpio_ll.h @@ -33,6 +33,9 @@ extern const uint8_t GPIO_PIN_MUX_REG_OFFSET[SOC_GPIO_PIN_COUNT]; // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) +// the gpio matrix signal routing const time +#define GPIO_LL_MATRIX_DELAY_NS 25 + #define GPIO_LL_APP_CPU_INTR_ENA (BIT(0)) #define GPIO_LL_APP_CPU_NMI_INTR_ENA (BIT(1)) #define GPIO_LL_PRO_CPU_INTR_ENA (BIT(2)) diff --git a/components/hal/esp32c2/include/hal/spi_ll.h b/components/hal/esp32c2/include/hal/spi_ll.h index f6ae3f4b17..4acd7b1721 100644 --- a/components/hal/esp32c2/include/hal/spi_ll.h +++ b/components/hal/esp32c2/include/hal/spi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -313,7 +313,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw) /** * Reset SPI CPU TX FIFO * - * On ESP32C3, this function is not separated + * On ESP32C2, this function is not separated * * @param hw Beginning address of the peripheral registers. */ @@ -326,7 +326,7 @@ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw) /** * Reset SPI CPU RX FIFO * - * On ESP32C3, this function is not separated + * On ESP32C2, this function is not separated * * @param hw Beginning address of the peripheral registers. */ @@ -859,7 +859,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32C2 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32c3/include/hal/spi_ll.h b/components/hal/esp32c3/include/hal/spi_ll.h index 9bb2f3ab7d..2b5ea2346a 100644 --- a/components/hal/esp32c3/include/hal/spi_ll.h +++ b/components/hal/esp32c3/include/hal/spi_ll.h @@ -861,7 +861,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32C3 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32c5/include/hal/spi_ll.h b/components/hal/esp32c5/include/hal/spi_ll.h index 5dd81c20c2..6af7784d9c 100644 --- a/components/hal/esp32c5/include/hal/spi_ll.h +++ b/components/hal/esp32c5/include/hal/spi_ll.h @@ -859,7 +859,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32C5 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32c6/include/hal/spi_ll.h b/components/hal/esp32c6/include/hal/spi_ll.h index 32e76c6ee3..9ef3d32280 100644 --- a/components/hal/esp32c6/include/hal/spi_ll.h +++ b/components/hal/esp32c6/include/hal/spi_ll.h @@ -853,7 +853,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32C6 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32h2/include/hal/spi_ll.h b/components/hal/esp32h2/include/hal/spi_ll.h index 944bad7ef4..7fbb59aa2c 100644 --- a/components/hal/esp32h2/include/hal/spi_ll.h +++ b/components/hal/esp32h2/include/hal/spi_ll.h @@ -852,7 +852,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32H2 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32p4/include/hal/spi_ll.h b/components/hal/esp32p4/include/hal/spi_ll.h index e45f484549..68299190eb 100644 --- a/components/hal/esp32p4/include/hal/spi_ll.h +++ b/components/hal/esp32p4/include/hal/spi_ll.h @@ -324,7 +324,7 @@ static inline void spi_ll_apply_config(spi_dev_t *hw) /** * Trigger start of user-defined transaction. - * The synchronization between two clock domains is required in ESP32-S3 + * The synchronization between two clock domains is required in ESP32P4 * * @param hw Beginning address of the peripheral registers. */ @@ -919,7 +919,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32P4 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h index efb690877c..19d62c57e2 100644 --- a/components/hal/esp32s2/include/hal/spi_ll.h +++ b/components/hal/esp32s2/include/hal/spi_ll.h @@ -871,7 +871,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32S2 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32s3/include/hal/spi_ll.h b/components/hal/esp32s3/include/hal/spi_ll.h index 6ccaec8533..bdbeb9267d 100644 --- a/components/hal/esp32s3/include/hal/spi_ll.h +++ b/components/hal/esp32s3/include/hal/spi_ll.h @@ -880,7 +880,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32S3 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/spi_flash_hal.c b/components/hal/spi_flash_hal.c index 75414367ef..d758608c8b 100644 --- a/components/hal/spi_flash_hal.c +++ b/components/hal/spi_flash_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,6 +11,7 @@ #include #include #include "soc/soc_caps.h" +#include "hal/gpio_ll.h" //for GPIO_LL_MATRIX_DELAY_NS #include "hal/spi_flash_hal.h" #include "hal/assert.h" #include "hal/log.h" @@ -64,7 +65,10 @@ static inline int get_dummy_n(bool gpio_is_used, int input_delay_ns, int eff_clk const int apbclk_kHz = APB_CLK_FREQ / 1000; //calculate how many apb clocks a period has const int apbclk_n = APB_CLK_FREQ / eff_clk; - const int gpio_delay_ns = gpio_is_used ? GPIO_MATRIX_DELAY_NS : 0; + int gpio_delay_ns = 0; +#if GPIO_LL_MATRIX_DELAY_NS + gpio_delay_ns = gpio_is_used ? GPIO_LL_MATRIX_DELAY_NS : 0; +#endif //calculate how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off. int apb_period_n = (1 + input_delay_ns + gpio_delay_ns) * apbclk_kHz / 1000 / 1000; diff --git a/components/hal/spi_hal.c b/components/hal/spi_hal.c index 18a17865d7..90ff24de39 100644 --- a/components/hal/spi_hal.c +++ b/components/hal/spi_hal.c @@ -9,6 +9,7 @@ #include "hal/spi_hal.h" #include "hal/log.h" #include "hal/assert.h" +#include "hal/gpio_ll.h" //for GPIO_LL_MATRIX_DELAY_NS #include "soc/soc_caps.h" #include "soc/clk_tree_defs.h" @@ -115,7 +116,10 @@ void spi_hal_cal_timing(int source_freq_hz, int eff_clk, bool gpio_is_used, int const int apbclk_kHz = source_freq_hz / 1000; //how many apb clocks a period has const int spiclk_apb_n = source_freq_hz / eff_clk; - const int gpio_delay_ns = gpio_is_used ? GPIO_MATRIX_DELAY_NS : 0; + int gpio_delay_ns = 0; +#if GPIO_LL_MATRIX_DELAY_NS + gpio_delay_ns = gpio_is_used ? GPIO_LL_MATRIX_DELAY_NS : 0; +#endif //how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off. int delay_apb_n = (1 + input_delay_ns + gpio_delay_ns) * apbclk_kHz / 1000 / 1000; @@ -146,7 +150,10 @@ void spi_hal_cal_timing(int source_freq_hz, int eff_clk, bool gpio_is_used, int int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns) { const int apbclk_kHz = APB_CLK_FREQ / 1000; - const int gpio_delay_ns = gpio_is_used ? GPIO_MATRIX_DELAY_NS : 0; + int gpio_delay_ns = 0; +#if GPIO_LL_MATRIX_DELAY_NS + gpio_delay_ns = gpio_is_used ? GPIO_LL_MATRIX_DELAY_NS : 0; +#endif //how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off. int delay_apb_n = (1 + input_delay_ns + gpio_delay_ns) * apbclk_kHz / 1000 / 1000; diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index 15a1812180..2eb996fd2b 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -166,7 +166,6 @@ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 26 // CPU is 80MHz -#define GPIO_MATRIX_DELAY_NS 25 //}} /* Overall memory map */ diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index b271cc2ca2..a57b15794a 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -152,7 +152,6 @@ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 4 #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 40 // CPU is 40MHz -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index b4969ec811..d661c4eb12 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -146,7 +146,6 @@ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 40 // CPU is 80MHz -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h index 7f4536f0d8..7134121e4b 100644 --- a/components/soc/esp32c5/include/soc/soc.h +++ b/components/soc/esp32c5/include/soc/soc.h @@ -138,7 +138,6 @@ #define APB_CLK_FREQ ( 40*1000000 ) #define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) #define REF_CLK_FREQ ( 1000000 ) -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h index 7986a5c2f1..6778a1764b 100644 --- a/components/soc/esp32c6/include/soc/soc.h +++ b/components/soc/esp32c6/include/soc/soc.h @@ -143,7 +143,6 @@ #define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) #define REF_CLK_FREQ ( 1000000 ) #define XTAL_CLK_FREQ (40*1000000) -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h index ab6fe10aac..01ed3d40db 100644 --- a/components/soc/esp32c61/include/soc/soc.h +++ b/components/soc/esp32c61/include/soc/soc.h @@ -138,7 +138,6 @@ #define APB_CLK_FREQ ( 40*1000000 ) #define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) #define REF_CLK_FREQ ( 1000000 ) -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index 1191c37e61..f3d2b2a904 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -141,7 +141,6 @@ #define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 32*1000000 ) #define REF_CLK_FREQ ( 1000000 ) #define XTAL_CLK_FREQ (32*1000000) -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h index 5c564db301..5b1b8490a6 100644 --- a/components/soc/esp32p4/include/soc/soc.h +++ b/components/soc/esp32p4/include/soc/soc.h @@ -141,7 +141,6 @@ #define APB_CLK_FREQ ( 90*1000000 ) #define REF_CLK_FREQ ( 1000000 ) #define XTAL_CLK_FREQ (40*1000000) -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index 6bca2b7bea..12d97311ff 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -152,7 +152,6 @@ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 40 // CPU is 80MHz -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 2600af7e59..056c6d9f4e 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -162,7 +162,6 @@ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 40 // CPU is 80MHz -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */