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Merge branch 'bugfix/gpio_8_16_bit_access' into 'master'

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feat(gpio): add gpio_config_as_analog() API

Closes IDF-10247 and IDFGH-12754

See merge request espressif/esp-idf!35856
This commit is contained in:
Song Ruo Jing 2025-01-10 15:14:19 +08:00
commit 486c95557a
43 changed files with 213 additions and 245 deletions
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22
components/driver/deprecated/adc_legacy.c
View File

@ -17,9 +17,8 @@
#include "esp_pm.h"
#include "soc/rtc.h"
#include "soc/soc_caps.h"
#include "driver/rtc_io.h"
#include "esp_private/gpio.h"
#include "sys/lock.h"
#include "driver/gpio.h"
#include "esp_private/adc_share_hw_ctrl.h"
#include "esp_private/sar_periph_ctrl.h"
#include "adc1_private.h"
@ -175,7 +174,6 @@ static void adc_rtc_chan_init(adc_unit_t adc_unit)
esp_err_t adc_common_gpio_init(adc_unit_t adc_unit, adc_channel_t channel)
{
ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(adc_unit), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel");
#if ADC_LL_RTC_GPIO_SUPPORTED
gpio_num_t gpio_num = 0;
//If called with `ADC_UNIT_BOTH (ADC_UNIT_1 | ADC_UNIT_2)`, both if blocks will be run
if (adc_unit == ADC_UNIT_1) {
@ -186,13 +184,7 @@ esp_err_t adc_common_gpio_init(adc_unit_t adc_unit, adc_channel_t channel)
} else {
return ESP_ERR_INVALID_ARG;
}
ESP_RETURN_ON_ERROR(rtc_gpio_init(gpio_num), ADC_TAG, "rtc_gpio_init fail");
ESP_RETURN_ON_ERROR(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED), ADC_TAG, "rtc_gpio_set_direction fail");
ESP_RETURN_ON_ERROR(rtc_gpio_pulldown_dis(gpio_num), ADC_TAG, "rtc_gpio_pulldown_dis fail");
ESP_RETURN_ON_ERROR(rtc_gpio_pullup_dis(gpio_num), ADC_TAG, "rtc_gpio_pullup_dis fail");
#endif
return ESP_OK;
return gpio_config_as_analog(gpio_num);
}
esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en)
@ -678,7 +670,6 @@ static int8_t adc_digi_get_io_num(adc_unit_t adc_unit, uint8_t adc_channel)
static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask)
{
esp_err_t ret = ESP_OK;
uint64_t gpio_mask = 0;
uint32_t n = 0;
int8_t io = 0;
@ -688,18 +679,11 @@ static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask)
if (io < 0) {
return ESP_ERR_INVALID_ARG;
}
gpio_mask |= BIT64(io);
gpio_config_as_analog(io);
}
channel_mask = channel_mask >> 1;
n++;
}
gpio_config_t cfg = {
.pin_bit_mask = gpio_mask,
.mode = GPIO_MODE_DISABLE,
};
ret = gpio_config(&cfg);
return ret;
}

9
components/driver/deprecated/dac_common_legacy.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,7 +7,7 @@
#include <string.h>
#include "esp_check.h"
#include "freertos/FreeRTOS.h"
#include "driver/rtc_io.h"
#include "esp_private/gpio.h"
#include "driver/dac_types_legacy.h"
#include "soc/dac_periph.h"
#include "hal/gpio_types.h"
@ -36,10 +36,7 @@ static esp_err_t dac_rtc_pad_init(dac_channel_t channel)
gpio_num_t gpio_num = 0;
dac_pad_get_io_num(channel, &gpio_num);
rtc_gpio_init(gpio_num);
rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED);
rtc_gpio_pullup_dis(gpio_num);
rtc_gpio_pulldown_dis(gpio_num);
gpio_config_as_analog(gpio_num);
return ESP_OK;
}

18
components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c
View File

@ -111,17 +111,17 @@ void test_adc_set_io_level(adc_unit_t unit, adc_channel_t channel, bool level)
{
TEST_ASSERT(channel < SOC_ADC_CHANNEL_NUM(unit) && "invalid channel");
#if !ADC_LL_RTC_GPIO_SUPPORTED
uint32_t io_num = ADC_GET_IO_NUM(unit, channel);
TEST_ESP_OK(gpio_set_pull_mode(io_num, (level ? GPIO_PULLUP_ONLY : GPIO_PULLDOWN_ONLY)));
#else
gpio_num_t io_num = ADC_GET_IO_NUM(unit, channel);
if (level) {
TEST_ESP_OK(rtc_gpio_pullup_en(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_dis(io_num));
} else {
TEST_ESP_OK(rtc_gpio_pullup_dis(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_en(io_num));
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
if (rtc_gpio_is_valid_gpio(io_num)) {
if (level) {
TEST_ESP_OK(rtc_gpio_pullup_en(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_dis(io_num));
} else {
TEST_ESP_OK(rtc_gpio_pullup_dis(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_en(io_num));
}
}
#endif
}

9
components/driver/touch_sensor/touch_sensor_common.c
View File

@ -15,9 +15,8 @@
#include "freertos/semphr.h"
#include "freertos/timers.h"
#include "esp_intr_alloc.h"
#include "driver/rtc_io.h"
#include "esp_private/rtc_ctrl.h"
#include "driver/gpio.h"
#include "esp_private/gpio.h"
#include "hal/touch_sensor_legacy_types.h"
#include "hal/touch_sensor_hal.h"
@ -121,11 +120,7 @@ esp_err_t touch_pad_io_init(touch_pad_t touch_num)
{
TOUCH_CHANNEL_CHECK(touch_num);
gpio_num_t gpio_num = TOUCH_GET_IO_NUM(touch_num);
rtc_gpio_init(gpio_num);
rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED);
rtc_gpio_pulldown_dis(gpio_num);
rtc_gpio_pullup_dis(gpio_num);
return ESP_OK;
return gpio_config_as_analog(gpio_num);
}
esp_err_t touch_pad_fsm_start(void)

19
components/esp_adc/adc_continuous.c
View File

@ -30,7 +30,7 @@
#include "esp_private/adc_share_hw_ctrl.h"
#include "esp_private/sar_periph_ctrl.h"
#include "esp_clk_tree.h"
#include "driver/gpio.h"
#include "esp_private/gpio.h"
#include "esp_adc/adc_continuous.h"
#include "hal/adc_types.h"
#include "hal/adc_hal.h"
@ -132,15 +132,15 @@ static IRAM_ATTR bool adc_dma_intr(adc_continuous_ctx_t *adc_digi_ctx)
static int8_t adc_digi_get_io_num(adc_unit_t adc_unit, uint8_t adc_channel)
{
assert(adc_unit < SOC_ADC_PERIPH_NUM);
uint8_t adc_n = (adc_unit == ADC_UNIT_1) ? 0 : 1;
return adc_channel_io_map[adc_n][adc_channel];
if (adc_unit >= 0 && adc_unit < SOC_ADC_PERIPH_NUM) {
return adc_channel_io_map[adc_unit][adc_channel];
}
return -1;
}
static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask)
{
esp_err_t ret = ESP_OK;
uint64_t gpio_mask = 0;
uint32_t n = 0;
int8_t io = 0;
@ -150,18 +150,11 @@ static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask)
if (io < 0) {
return ESP_ERR_INVALID_ARG;
}
gpio_mask |= BIT64(io);
gpio_config_as_analog(io);
}
channel_mask = channel_mask >> 1;
n++;
}
gpio_config_t cfg = {
.pin_bit_mask = gpio_mask,
.mode = GPIO_MODE_DISABLE,
};
ret = gpio_config(&cfg);
return ret;
}

25
components/esp_adc/adc_oneshot.c
View File

@ -17,8 +17,7 @@
#include "esp_check.h"
#include "esp_heap_caps.h"
#include "freertos/FreeRTOS.h"
#include "driver/gpio.h"
#include "driver/rtc_io.h"
#include "esp_private/gpio.h"
#include "esp_adc/adc_oneshot.h"
#include "esp_clk_tree.h"
#include "esp_private/adc_private.h"
@ -293,27 +292,7 @@ esp_err_t adc_oneshot_get_calibrated_result(adc_oneshot_unit_handle_t handle, ad
static esp_err_t s_adc_io_init(adc_unit_t unit, adc_channel_t channel)
{
ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(unit), ESP_ERR_INVALID_ARG, TAG, "invalid channel");
#if !ADC_LL_RTC_GPIO_SUPPORTED
uint32_t io_num = ADC_GET_IO_NUM(unit, channel);
gpio_config_t cfg = {
.pin_bit_mask = BIT64(io_num),
.mode = GPIO_MODE_DISABLE,
.pull_up_en = GPIO_PULLUP_DISABLE,
.pull_down_en = GPIO_PULLDOWN_DISABLE,
.intr_type = GPIO_INTR_DISABLE,
};
ESP_RETURN_ON_ERROR(gpio_config(&cfg), TAG, "IO config fail");
#else
gpio_num_t io_num = ADC_GET_IO_NUM(unit, channel);
ESP_RETURN_ON_ERROR(rtc_gpio_init(io_num), TAG, "IO config fail");
ESP_RETURN_ON_ERROR(rtc_gpio_set_direction(io_num, RTC_GPIO_MODE_DISABLED), TAG, "IO config fail");
ESP_RETURN_ON_ERROR(rtc_gpio_pulldown_dis(io_num), TAG, "IO config fail");
ESP_RETURN_ON_ERROR(rtc_gpio_pullup_dis(io_num), TAG, "IO config fail");
#endif
return ESP_OK;
return gpio_config_as_analog(ADC_GET_IO_NUM(unit, channel));
}
static bool s_adc_unit_claim(adc_unit_t unit)

33
components/esp_adc/test_apps/adc/main/test_common_adc.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
@ -99,19 +99,18 @@ void test_adc_set_io_level(adc_unit_t unit, adc_channel_t channel, bool level)
{
TEST_ASSERT(channel < SOC_ADC_CHANNEL_NUM(unit) && "invalid channel");
#if !ADC_LL_RTC_GPIO_SUPPORTED
uint32_t io_num = ADC_GET_IO_NUM(unit, channel);
TEST_ESP_OK(gpio_set_pull_mode(io_num, (level ? GPIO_PULLUP_ONLY : GPIO_PULLDOWN_ONLY)));
#else
gpio_num_t io_num = ADC_GET_IO_NUM(unit, channel);
if (level) {
TEST_ESP_OK(rtc_gpio_pullup_en(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_dis(io_num));
} else {
TEST_ESP_OK(rtc_gpio_pullup_dis(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_en(io_num));
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
if (rtc_gpio_is_valid_gpio(io_num)) {
if (level) {
TEST_ESP_OK(rtc_gpio_pullup_en(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_dis(io_num));
} else {
TEST_ESP_OK(rtc_gpio_pullup_dis(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_en(io_num));
}
}
TEST_ESP_OK(gpio_set_pull_mode(io_num, (level ? GPIO_PULLUP_ONLY : GPIO_PULLDOWN_ONLY)));
#endif
}
@ -120,14 +119,12 @@ void test_adc_set_io_middle(adc_unit_t unit, adc_channel_t channel)
TEST_ASSERT(channel < SOC_ADC_CHANNEL_NUM(unit) && "invalid channel");
uint32_t io_num = ADC_GET_IO_NUM(unit, channel);
#if !ADC_LL_RTC_GPIO_SUPPORTED
TEST_ESP_OK(gpio_set_pull_mode(io_num, GPIO_PULLUP_PULLDOWN));
#else
TEST_ESP_OK(rtc_gpio_init(io_num));
TEST_ESP_OK(rtc_gpio_pullup_en(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_en(io_num));
TEST_ESP_OK(rtc_gpio_set_direction(io_num, RTC_GPIO_MODE_DISABLED));
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
if (rtc_gpio_is_valid_gpio(io_num)) {
TEST_ESP_OK(rtc_gpio_pullup_en(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_en(io_num));
}
#endif
vTaskDelay(10 / portTICK_PERIOD_MS);
}

19
components/esp_driver_ana_cmpr/ana_cmpr.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -25,7 +25,7 @@
#include "soc/ana_cmpr_periph.h"
#include "hal/ana_cmpr_ll.h"
#include "driver/ana_cmpr.h"
#include "driver/gpio.h"
#include "esp_private/gpio.h"
#include "esp_private/io_mux.h"
#include "esp_private/esp_clk.h"
@ -96,18 +96,11 @@ static void IRAM_ATTR s_ana_cmpr_default_intr_handler(void *usr_data)
static esp_err_t s_ana_cmpr_init_gpio(ana_cmpr_handle_t cmpr, bool is_external_ref)
{
uint64_t pin_mask = BIT64(ana_cmpr_periph[cmpr->unit].src_gpio);
if (is_external_ref) {
pin_mask |= BIT64(ana_cmpr_periph[cmpr->unit].ext_ref_gpio);
esp_err_t err = gpio_config_as_analog(ana_cmpr_periph[cmpr->unit].src_gpio);
if (err == ESP_OK && is_external_ref) {
err = gpio_config_as_analog(ana_cmpr_periph[cmpr->unit].ext_ref_gpio);
}
gpio_config_t ana_cmpr_gpio_cfg = {
.pin_bit_mask = pin_mask,
.mode = GPIO_MODE_DISABLE,
.pull_up_en = GPIO_PULLUP_DISABLE,
.pull_down_en = GPIO_PULLDOWN_DISABLE,
.intr_type = GPIO_INTR_DISABLE,
};
return gpio_config(&ana_cmpr_gpio_cfg);
return err;
}
esp_err_t ana_cmpr_new_unit(const ana_cmpr_config_t *config, ana_cmpr_handle_t *ret_cmpr)

3
components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr.c
View File

@ -50,8 +50,6 @@ TEST_CASE("ana_cmpr_unit_install_uninstall", "[ana_cmpr]")
TEST_CASE("ana_cmpr_internal_reference", "[ana_cmpr]")
{
int src_chan = test_init_src_chan_gpio(TEST_ANA_CMPR_UNIT_ID);
uint32_t cnt = 0;
ana_cmpr_handle_t cmpr = NULL;
ana_cmpr_config_t config = {
@ -62,6 +60,7 @@ TEST_CASE("ana_cmpr_internal_reference", "[ana_cmpr]")
.flags.io_loop_back = 1,
};
TEST_ESP_OK(ana_cmpr_new_unit(&config, &cmpr));
int src_chan = test_init_src_chan_gpio(TEST_ANA_CMPR_UNIT_ID);
ana_cmpr_internal_ref_config_t ref_cfg = {
.ref_volt = ANA_CMPR_REF_VOLT_50_PCT_VDD,
};

12
components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr_common.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,6 +7,7 @@
#include "test_ana_cmpr.h"
#include "hal/gpio_ll.h"
#include "driver/gpio.h"
#include "esp_private/gpio.h"
#include "esp_attr.h"
bool IRAM_ATTR test_ana_cmpr_on_cross_callback(ana_cmpr_handle_t cmpr, const ana_cmpr_cross_event_data_t *edata, void *user_ctx)
@ -21,15 +22,8 @@ int test_init_src_chan_gpio(int unit_id)
int src_chan_num = -1;
TEST_ESP_OK(ana_cmpr_get_gpio(unit_id, ANA_CMPR_SOURCE_CHAN, &src_chan_num));
TEST_ASSERT(src_chan_num > 0);
gpio_config_t io_conf = {
.intr_type = GPIO_INTR_DISABLE,
.mode = GPIO_MODE_OUTPUT,
.pin_bit_mask = (1ULL << src_chan_num),
.pull_down_en = false,
.pull_up_en = false,
};
TEST_ESP_OK(gpio_config(&io_conf));
TEST_ESP_OK(gpio_set_level(src_chan_num, 0));
TEST_ESP_OK(gpio_output_enable(src_chan_num));
return src_chan_num;
}

11
components/esp_driver_dac/dac_common.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,7 +11,7 @@
#include "soc/dac_periph.h"
#include "hal/dac_types.h"
#include "hal/dac_ll.h"
#include "driver/rtc_io.h"
#include "esp_private/gpio.h"
#include "esp_check.h"
#include "dac_priv_common.h"
@ -70,10 +70,7 @@ esp_err_t dac_priv_enable_channel(dac_channel_t chan_id)
ESP_RETURN_ON_FALSE(s_dac_chan[chan_id].in_use, ESP_ERR_INVALID_STATE, TAG, "the channel is not registered");
gpio_num_t gpio_num = (gpio_num_t)dac_periph_signal.dac_channel_io_num[chan_id];
rtc_gpio_init(gpio_num);
rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED);
rtc_gpio_pullup_dis(gpio_num);
rtc_gpio_pulldown_dis(gpio_num);
gpio_config_as_analog(gpio_num);
DAC_RTC_ENTER_CRITICAL();
dac_ll_power_on(chan_id);
dac_ll_rtc_sync_by_adc(false);
@ -87,8 +84,6 @@ esp_err_t dac_priv_disable_channel(dac_channel_t chan_id)
ESP_RETURN_ON_FALSE(chan_id < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "channel id is invalid");
ESP_RETURN_ON_FALSE(s_dac_chan[chan_id].in_use, ESP_ERR_INVALID_STATE, TAG, "the channel is not registered");
gpio_num_t gpio_num = (gpio_num_t)dac_periph_signal.dac_channel_io_num[chan_id];
rtc_gpio_deinit(gpio_num);
DAC_RTC_ENTER_CRITICAL();
dac_ll_power_down(chan_id);
DAC_RTC_EXIT_CRITICAL();

4
components/esp_driver_gpio/README.md
View File

@ -23,3 +23,7 @@ If the signal is routed through IO MUX to the pin, then call `gpio_iomux_out` to
If the signal is routed through GPIO Matrix to the pin, then first call `gpio_func_sel` to let the pin use `PIN_FUNC_GPIO` function, follow by calling `gpio_input_enable` and `esp_rom_gpio_connect_in_signal` to enable the input and connect the signal to the pin.
When a peripheral driver does de-initialization, to de-configure the pin as the peripheral signal input, use `esp_rom_gpio_connect_in_signal` to connect the signal to CONST_ONE or CONST_ZERO, so that it is disconnected from the pin. It is not desired to call `gpio_input_disable`, because there might be other drivers still using this pin as an input.
# Configure an IO as analog function
When the pin is used for analog purpose, the pin needs to be left floating, so that the external analog signal is directly connected to internal analog signal. A call to `gpio_config_as_analog` will handle all the necessary IO configurations.

64
components/esp_driver_gpio/include/driver/rtc_io.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,17 +11,17 @@
#include "esp_err.h"
#include "soc/soc_caps.h"
#include "hal/rtc_io_types.h"
#include "driver/gpio.h"
#include "hal/gpio_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Determine if the specified GPIO is a valid RTC GPIO.
* @brief Determine if the specified IO is a valid RTC GPIO.
*
* @param gpio_num GPIO number
* @return true if GPIO is valid for RTC GPIO use. false otherwise.
* @return true if the IO is valid for RTC GPIO use. false otherwise.
*/
bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num);
@ -29,36 +29,34 @@ bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num);
#if SOC_RTCIO_PIN_COUNT > 0
/**
* @brief Get RTC IO index number by gpio number.
* @brief Get RTC IO index number by GPIO number.
*
* @param gpio_num GPIO number
* @return
* >=0: Index of rtcio.
* -1 : The gpio is not rtcio.
* >=0: Index of RTC IO.
* -1 : The IO is not an RTC IO.
*/
int rtc_io_number_get(gpio_num_t gpio_num);
/**
* @brief Init a GPIO as RTC GPIO
*
* This function must be called when initializing a pad for an analog function.
* @brief Init an IO to be an RTC GPIO, route to RTC IO MUX
*
* @param gpio_num GPIO number (e.g. GPIO_NUM_12)
*
* @return
* - ESP_OK success
* - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_init(gpio_num_t gpio_num);
/**
* @brief Init a GPIO as digital GPIO
* @brief Deinit an IO as an RTC GPIO, route back to IO MUX
*
* @param gpio_num GPIO number (e.g. GPIO_NUM_12)
*
* @return
* - ESP_OK success
* - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num);
@ -71,7 +69,7 @@ esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num);
* @return
* - 1 High level
* - 0 Low level
* - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
uint32_t rtc_gpio_get_level(gpio_num_t gpio_num);
@ -83,7 +81,7 @@ uint32_t rtc_gpio_get_level(gpio_num_t gpio_num);
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level);
@ -94,11 +92,11 @@ esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level);
* output and input.
*
* @param gpio_num GPIO number (e.g. GPIO_NUM_12)
* @param mode GPIO direction
* @param mode RTC GPIO direction
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_set_direction(gpio_num_t gpio_num, rtc_gpio_mode_t mode);
@ -110,11 +108,11 @@ esp_err_t rtc_gpio_set_direction(gpio_num_t gpio_num, rtc_gpio_mode_t mode);
* The rest targets support INPUT_ONLY, OUTPUT_ONLY, INPUT_OUTPUT mode.
*
* @param gpio_num GPIO number (e.g. GPIO_NUM_12)
* @param mode GPIO direction
* @param mode RTC GPIO direction
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_set_direction_in_sleep(gpio_num_t gpio_num, rtc_gpio_mode_t mode);
@ -128,7 +126,7 @@ esp_err_t rtc_gpio_set_direction_in_sleep(gpio_num_t gpio_num, rtc_gpio_mode_t m
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_pullup_en(gpio_num_t gpio_num);
@ -142,7 +140,7 @@ esp_err_t rtc_gpio_pullup_en(gpio_num_t gpio_num);
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_pulldown_en(gpio_num_t gpio_num);
@ -156,7 +154,7 @@ esp_err_t rtc_gpio_pulldown_en(gpio_num_t gpio_num);
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num);
@ -170,7 +168,7 @@ esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num);
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num);
@ -225,7 +223,7 @@ esp_err_t rtc_gpio_iomux_func_sel(gpio_num_t gpio_num, int func);
* @param gpio_num GPIO number (e.g. GPIO_NUM_12)
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num);
@ -239,7 +237,7 @@ esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num);
* @param gpio_num GPIO number (e.g. GPIO_NUM_12)
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num);
@ -275,8 +273,8 @@ esp_err_t rtc_gpio_force_hold_dis_all(void);
*
* @param gpio_num GPIO number (e.g. GPIO_NUM_12).
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if GPIO is not an RTC IO
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num);
#endif // SOC_RTCIO_HOLD_SUPPORTED && SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
@ -289,8 +287,8 @@ esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num);
* @param intr_type Wakeup on high level (GPIO_INTR_HIGH_LEVEL) or low level
* (GPIO_INTR_LOW_LEVEL)
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if gpio_num is not an RTC IO, or intr_type is not
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO, or intr_type is not
* one of GPIO_INTR_HIGH_LEVEL, GPIO_INTR_LOW_LEVEL.
*/
esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type);
@ -299,8 +297,8 @@ esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
* @brief Disable wakeup from sleep mode using specific GPIO
* @param gpio_num GPIO number
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if gpio_num is not an RTC IO
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO
*/
esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num);

10
components/esp_driver_gpio/include/esp_private/gpio.h
View File

@ -96,6 +96,16 @@ esp_err_t gpio_od_disable(gpio_num_t gpio_num);
*/
esp_err_t gpio_od_enable(gpio_num_t gpio_num);
/**
* @brief Configure the pin to be used for analog purpose (such as ADC, touch, etc.)
*
* @param gpio_num GPIO number
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG GPIO number error
*/
esp_err_t gpio_config_as_analog(gpio_num_t gpio_num);
#ifdef __cplusplus
}
#endif

20
components/esp_driver_gpio/src/gpio.c
View File

@ -433,6 +433,26 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
return ESP_OK;
}
esp_err_t gpio_config_as_analog(gpio_num_t gpio_num)
{
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
// To be used for analog function, the pin needs to be left floating
gpio_input_disable(gpio_num);
gpio_output_disable(gpio_num);
gpio_pullup_dis(gpio_num);
gpio_pulldown_dis(gpio_num);
gpio_hal_func_sel(gpio_context.gpio_hal, gpio_num, PIN_FUNC_GPIO);
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
if (rtc_gpio_is_valid_gpio(gpio_num)) {
rtc_gpio_deinit(gpio_num);
rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED);
rtc_gpio_pullup_dis(gpio_num);
rtc_gpio_pulldown_dis(gpio_num);
}
#endif
return ESP_OK;
}
esp_err_t gpio_reset_pin(gpio_num_t gpio_num)
{
assert(GPIO_IS_VALID_GPIO(gpio_num));

6
components/esp_driver_gpio/src/rtc_io.c
View File

@ -11,8 +11,6 @@
#include "esp_private/periph_ctrl.h"
#include "esp_private/io_mux.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/timers.h"
#include "driver/rtc_io.h"
#include "driver/lp_io.h"
#include "hal/rtc_io_hal.h"
@ -241,8 +239,10 @@ esp_err_t rtc_gpio_force_hold_dis_all(void)
esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
int rtcio_num = rtc_io_number_get(gpio_num);
RTCIO_ENTER_CRITICAL();
rtcio_hal_isolate(rtc_io_number_get(gpio_num));
rtcio_hal_isolate(rtcio_num);
rtcio_hal_hold_enable(rtcio_num);
RTCIO_EXIT_CRITICAL();
return ESP_OK;

10
components/esp_driver_gpio/test_apps/gpio/CMakeLists.txt
View File

@ -19,3 +19,13 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
DEPENDS ${elf}
)
endif()
include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
message(STATUS "Checking gpio registers are not read-write by half-word")
check_register_rw_half_word(SOC_MODULES "gpio" "io_mux" "rtc_cntl" "rtc_io" "pcr" "hp_sys_clkrst" "hp_system"
"lp_aon" "lp_iomux" "pmu"
HAL_MODULES "gpio")
message(STATUS "Checking rtcio registers are not read-write by half-word")
check_register_rw_half_word(SOC_MODULES "rtc_io" "sens" "pcr" "lp_aon" "lp_io" "lp_gpio" "lp_iomux" "lpperi" "pmu"
HAL_MODULES "rtc_io")

5
components/esp_driver_gpio/test_apps/gpio_extensions/main/CMakeLists.txt
View File

@ -21,3 +21,8 @@ endif()
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES unity esp_driver_gpio
WHOLE_ARCHIVE)
message(STATUS "Checking gpio_ext registers are not read-write by half-word")
include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
check_register_rw_half_word(SOC_MODULES "gpio_ext"
HAL_MODULES "gpio_etm" "gpio_glitch_filter")

5
components/esp_driver_sdm/test_apps/sigma_delta/CMakeLists.txt
View File

@ -19,3 +19,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
DEPENDS ${elf}
)
endif()
message(STATUS "Checking sdm registers are not read-write by half-word")
include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
check_register_rw_half_word(SOC_MODULES "gpio_ext" "gpio_sd"
HAL_MODULES "sdm")

7
components/esp_driver_touch_sens/common/touch_sens_common.c
View File

@ -12,7 +12,7 @@
#include "soc/rtc.h"
#include "soc/clk_tree_defs.h"
#include "soc/touch_sensor_periph.h"
#include "driver/rtc_io.h"
#include "esp_private/gpio.h"
#include "driver/touch_sens.h"
#if SOC_TOUCH_SENSOR_VERSION <= 2
@ -42,10 +42,7 @@ touch_sensor_handle_t g_touch = NULL;
static void touch_channel_pin_init(int id)
{
gpio_num_t pin = touch_sensor_channel_io_map[id];
rtc_gpio_init(pin);
rtc_gpio_set_direction(pin, RTC_GPIO_MODE_DISABLED);
rtc_gpio_pulldown_dis(pin);
rtc_gpio_pullup_dis(pin);
gpio_config_as_analog(pin);
}
static void s_touch_free_resource(touch_sensor_handle_t sens_handle)

5
components/esp_hw_support/sleep_modes.c
View File

@ -31,6 +31,7 @@
#include "soc/spi_pins.h"
#include "soc/chip_revision.h"
#include "driver/rtc_io.h"
#include "driver/gpio.h"
#include "hal/efuse_hal.h"
#include "hal/rtc_io_hal.h"
#include "hal/clk_tree_hal.h"
@ -1938,7 +1939,7 @@ static void ext1_wakeup_prepare(void)
{
// Configure all RTC IOs selected as ext1 wakeup inputs
uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask;
for (int gpio = 0; gpio < GPIO_PIN_COUNT && rtc_gpio_mask != 0; ++gpio) {
for (int gpio = 0; gpio < SOC_GPIO_PIN_COUNT && rtc_gpio_mask != 0; ++gpio) {
int rtc_pin = rtc_io_number_get(gpio);
if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) {
continue;
@ -1987,7 +1988,7 @@ uint64_t esp_sleep_get_ext1_wakeup_status(void)
uint32_t status = rtc_hal_ext1_get_wakeup_status();
// Translate bit map of RTC IO numbers into the bit map of GPIO numbers
uint64_t gpio_mask = 0;
for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) {
for (int gpio = 0; gpio < SOC_GPIO_PIN_COUNT; ++gpio) {
if (!esp_sleep_is_valid_wakeup_gpio(gpio)) {
continue;
}

3
components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c
View File

@ -9,7 +9,6 @@
#include <sys/param.h>
#include "esp_sleep.h"
#include "esp_private/esp_sleep_internal.h"
#include "driver/rtc_io.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@ -17,6 +16,8 @@
#include "hal/uart_types.h"
#include "hal/uart_ll.h"
#include "driver/uart.h"
#include "driver/rtc_io.h"
#include "driver/gpio.h"
#include "soc/rtc.h" // for wakeup trigger defines
#include "soc/rtc_periph.h" // for read rtc registers directly (cause)
#include "soc/soc.h" // for direct register read macros

1
components/hal/esp32/include/hal/adc_ll.h
View File

@ -31,7 +31,6 @@ extern "C" {
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
#define ADC_LL_RTC_GPIO_SUPPORTED (1)
/*---------------------------------------------------------------
DMA

10
components/hal/esp32c2/include/hal/gpio_ll.h
View File

@ -21,6 +21,7 @@
#include "soc/rtc_cntl_reg.h"
#include "hal/gpio_types.h"
#include "hal/assert.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -75,7 +76,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
}
if (sig_out) {
*sig_out = hw->func_out_sel_cfg[gpio_num].func_sel;
*sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
}
if (slp_sel) {
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
@ -318,10 +319,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num)
{
gpio_func_out_sel_cfg_reg_t reg = {
.func_sel = SIG_GPIO_OUT_IDX,
};
hw->func_out_sel_cfg[gpio_num].val = reg.val;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel, SIG_GPIO_OUT_IDX);
}
/**
@ -571,7 +569,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
{
gpio_func_in_sel_cfg_reg_t reg;
reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
return (reg.sig_in_sel ? reg.func_sel : -1);
return (reg.sig_in_sel ? reg.in_sel : -1);
}
/**

5
components/hal/esp32c3/include/hal/gpio_ll.h
View File

@ -23,6 +23,7 @@
#include "soc/usb_serial_jtag_reg.h"
#include "hal/gpio_types.h"
#include "hal/assert.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -544,7 +545,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
{
typeof(hw->func_in_sel_cfg[in_sig_idx]) reg;
reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
return (reg.sig_in_sel ? reg.func_sel : -1);
return (reg.sig_in_sel ? reg.in_sel : -1);
}
/**
@ -781,7 +782,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
}
if (sig_out) {
*sig_out = hw->func_out_sel_cfg[gpio_num].func_sel;
*sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
}
if (slp_sel) {
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;

1
components/hal/esp32c5/include/hal/gpio_ll.h
View File

@ -27,7 +27,6 @@
#include "soc/usb_serial_jtag_struct.h"
#include "hal/gpio_types.h"
#include "hal/assert.h"
#include "soc/lp_gpio_struct.h"
#ifdef __cplusplus
extern "C" {

12
components/hal/esp32c5/include/hal/rtc_io_ll.h
View File

@ -115,7 +115,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
*/
static inline void rtcio_ll_output_enable(int rtcio_num)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, enable_w1ts, BIT(rtcio_num));
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, out_enable_w1ts, BIT(rtcio_num));
}
/**
@ -125,7 +125,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
*/
static inline void rtcio_ll_output_disable(int rtcio_num)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, enable_w1tc, BIT(rtcio_num));
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, out_enable_w1tc, BIT(rtcio_num));
}
/**
@ -137,9 +137,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{
if (level) {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, out_w1ts, BIT(rtcio_num));
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, out_data_w1ts, BIT(rtcio_num));
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, out_w1tc, BIT(rtcio_num));
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, out_data_w1tc, BIT(rtcio_num));
}
}
@ -357,7 +357,7 @@ static inline void rtcio_ll_intr_enable(int rtcio_num, rtcio_ll_intr_type_t type
LP_GPIO.pinn[rtcio_num].pinn_int_type = type;
/* Work around for HW issue,
need to also enable this clk, so that LP_GPIO.status.status_interrupt can get updated,
need to also enable this clk, so that (LP_GPIO.status, status_interrupt) can get updated,
and trigger the interrupt on the LP Core
*/
LP_GPIO.clock_gate.clk_en = 1;
@ -450,7 +450,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void)
*/
static inline void rtcio_ll_clear_interrupt_status(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, status_w1tc, 0xff);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, status_intr_w1tc, 0xff);
}
#ifdef __cplusplus

9
components/hal/esp32c6/include/hal/gpio_ll.h
View File

@ -20,13 +20,13 @@
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/lp_aon_struct.h"
#include "soc/lp_io_struct.h"
#include "soc/pmu_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
#include "hal/gpio_types.h"
#include "hal/assert.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -81,7 +81,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
}
if (sig_out) {
*sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
*sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
}
if (slp_sel) {
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
@ -333,10 +333,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num)
{
gpio_func_out_sel_cfg_reg_t reg = {
.out_sel = SIG_GPIO_OUT_IDX,
};
hw->func_out_sel_cfg[gpio_num].val = reg.val;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel, SIG_GPIO_OUT_IDX);
}
/**

8
components/hal/esp32c6/include/hal/rtc_io_ll.h
View File

@ -136,9 +136,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{
if (level) {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1ts, out_data_w1ts, BIT(rtcio_num));
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1ts, out_w1ts, BIT(rtcio_num));
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1tc, out_data_w1tc, BIT(rtcio_num));
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1tc, out_w1tc, BIT(rtcio_num));
}
}
@ -364,7 +364,7 @@ static inline void rtcio_ll_intr_enable(int rtcio_num, rtcio_ll_intr_type_t type
LP_IO.pin[rtcio_num].int_type = type;
/* Work around for HW issue,
need to also enable this clk, so that LP_IO.status.status_interrupt can get updated,
need to also enable this clk, so that (LP_IO.status, status_interrupt) can get updated,
and trigger the interrupt on the LP Core
*/
LP_IO.date.clk_en = 1;
@ -457,7 +457,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void)
*/
static inline void rtcio_ll_clear_interrupt_status(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.status_w1tc, status_w1tc, 0xff);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.status_w1tc, status_intr_w1tc, 0xff);
}
#ifdef __cplusplus

7
components/hal/esp32h2/include/hal/gpio_ll.h
View File

@ -81,7 +81,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
}
if (sig_out) {
*sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
*sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
}
if (slp_sel) {
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
@ -378,10 +378,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num)
{
gpio_func_out_sel_cfg_reg_t reg = {
.out_sel = SIG_GPIO_OUT_IDX,
};
hw->func_out_sel_cfg[gpio_num].val = reg.val;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel, SIG_GPIO_OUT_IDX);
}
/**

8
components/hal/esp32p4/include/hal/gpio_ll.h
View File

@ -303,7 +303,9 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO0-15
LP_IOMUX.lp_pad_hys.reg_lp_gpio_hys |= bit_mask;
uint32_t hys_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hys, reg_lp_gpio_hys);
hys_mask |= bit_mask;
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hys, reg_lp_gpio_hys, hys_mask);
} else {
if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
// GPIO 16-47
@ -326,7 +328,9 @@ static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO0-15
LP_IOMUX.lp_pad_hys.reg_lp_gpio_hys &= ~bit_mask;
uint32_t hys_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hys, reg_lp_gpio_hys);
hys_mask &= ~bit_mask;
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hys, reg_lp_gpio_hys, hys_mask);
} else {
if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
// GPIO 16-47

1
components/hal/esp32s2/include/hal/adc_ll.h
View File

@ -42,7 +42,6 @@ extern "C" {
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
#define ADC_LL_RTC_GPIO_SUPPORTED (1)
/*---------------------------------------------------------------
DMA

1
components/hal/esp32s2/include/hal/gpio_ll.h
View File

@ -18,7 +18,6 @@
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_io_reg.h"
#include "soc/gpio_struct.h"
#include "hal/gpio_types.h"
#include "hal/assert.h"

1
components/hal/esp32s3/include/hal/adc_ll.h
View File

@ -44,7 +44,6 @@ extern "C" {
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
#define ADC_LL_RTC_GPIO_SUPPORTED (1)
/*---------------------------------------------------------------
DMA

1
components/hal/esp32s3/include/hal/gpio_ll.h
View File

@ -18,7 +18,6 @@
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_io_reg.h"
#include "soc/usb_serial_jtag_reg.h"
#include "hal/gpio_types.h"
#include "soc/gpio_struct.h"

3
components/hal/rtc_io_hal.c
View File

@ -77,15 +77,12 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode)
}
}
#if SOC_RTCIO_HOLD_SUPPORTED
void rtcio_hal_isolate(int rtcio_num)
{
rtcio_ll_pullup_disable(rtcio_num);
rtcio_ll_pulldown_disable(rtcio_num);
rtcio_ll_output_disable(rtcio_num);
rtcio_ll_input_disable(rtcio_num);
rtcio_ll_force_hold_enable(rtcio_num);
}
#endif
#endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED

4
components/soc/esp32c2/register/soc/gpio_struct.h
View File

@ -301,7 +301,7 @@ typedef union {
* set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
* high level. s=0x3C: set this port always low level.
*/
uint32_t func_sel:5;
uint32_t in_sel:5;
/** in_inv_sel : R/W; bitpos: [5]; default: 0;
* set this bit to invert input signal. 1:invert. 0:not invert.
*/
@ -325,7 +325,7 @@ typedef union {
* output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
* GPIO_OUT_REG[n].
*/
uint32_t func_sel:8;
uint32_t out_sel:8;
/** out_inv_sel : R/W; bitpos: [8]; default: 0;
* set this bit to invert output signal.1:invert.0:not invert.
*/

4
components/soc/esp32c3/register/soc/gpio_struct.h
View File

@ -182,7 +182,7 @@ typedef volatile struct gpio_dev_s {
uint32_t reserved_150;
union {
struct {
uint32_t func_sel: 5;
uint32_t in_sel: 5;
uint32_t sig_in_inv: 1;
uint32_t sig_in_sel: 1;
uint32_t reserved7: 25;
@ -319,7 +319,7 @@ typedef volatile struct gpio_dev_s {
uint32_t reserved_550;
union {
struct {
uint32_t func_sel: 8;
uint32_t out_sel: 8;
uint32_t inv_sel: 1;
uint32_t oen_sel: 1;
uint32_t oen_inv_sel: 1;

24
components/soc/esp32c5/register/soc/lp_gpio_struct.h
View File

@ -33,7 +33,7 @@ typedef union {
*/
typedef union {
struct {
/** out_w1ts : WT; bitpos: [7:0]; default: 0;
/** out_data_w1ts : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to enable the output register LP_IO_OUT_REG of GPIO0 ~
* GPIO7.\\
*
@ -42,7 +42,7 @@ typedef union {
* will be set to 1.
* - Recommended operation: use this register to set LP_IO_OUT_REG.
*/
uint32_t out_w1ts:8;
uint32_t out_data_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
@ -53,7 +53,7 @@ typedef union {
*/
typedef union {
struct {
/** out_w1tc : WT; bitpos: [7:0]; default: 0;
/** out_data_w1tc : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to clear the output register LP_IO_OUT_REG of GPIO0 ~
* GPIO7.\\
*
@ -62,7 +62,7 @@ typedef union {
* will be cleared.
* - Recommended operation: use this register to clear LP_IO_OUT_REG.
*/
uint32_t out_w1tc:8;
uint32_t out_data_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
@ -90,7 +90,7 @@ typedef union {
*/
typedef union {
struct {
/** enable_w1ts : WT; bitpos: [7:0]; default: 0;
/** out_enable_w1ts : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to set the output enable register LP_IO_ENABLE_REG of
* GPIO0 ~ GPIO7.\\
*
@ -99,7 +99,7 @@ typedef union {
* LP_IO_ENABLE_REG will be set to 1.
* - Recommended operation: use this register to set LP_IO_ENABLE_REG.
*/
uint32_t enable_w1ts:8;
uint32_t out_enable_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
@ -110,7 +110,7 @@ typedef union {
*/
typedef union {
struct {
/** enable_w1tc : WT; bitpos: [7:0]; default: 0;
/** out_enable_w1tc : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to clear the output enable register LP_IO_ENABLE_REG of
* GPIO0 ~ GPIO7.\\
*
@ -119,7 +119,7 @@ typedef union {
* LP_IO_ENABLE_REG will be cleared.
* - Recommended operation: use this register to clear LP_IO_ENABLE_REG.
*/
uint32_t enable_w1tc:8;
uint32_t out_enable_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
@ -165,7 +165,7 @@ typedef union {
*/
typedef union {
struct {
/** status_w1ts : WT; bitpos: [7:0]; default: 0;
/** status_intr_w1ts : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to set the interrupt status register LP_IO_STATUS_INT of
* GPIO0 ~ GPIO7.\\
*
@ -174,7 +174,7 @@ typedef union {
* LP_IO_STATUS_INT will be set to 1.
* - Recommended operation: use this register to set LP_IO_STATUS_INT.
*/
uint32_t status_w1ts:8;
uint32_t status_intr_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
@ -185,7 +185,7 @@ typedef union {
*/
typedef union {
struct {
/** status_w1tc : WT; bitpos: [7:0]; default: 0;
/** status_intr_w1tc : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to clear the interrupt status register LP_IO_STATUS_INT
* of GPIO0 ~ GPIO7. \\
*
@ -194,7 +194,7 @@ typedef union {
* LP_IO_STATUS_INT will be cleared
* - ecommended operation: use this register to clear LP_IO_STATUS_INT.
*/
uint32_t status_w1tc:8;
uint32_t status_intr_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;

18
components/soc/esp32c6/register/soc/lp_io_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -30,10 +30,10 @@ typedef union {
*/
typedef union {
struct {
/** out_data_w1ts : WT; bitpos: [7:0]; default: 0;
/** out_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t out_data_w1ts:8;
uint32_t out_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
@ -44,10 +44,10 @@ typedef union {
*/
typedef union {
struct {
/** out_data_w1tc : WT; bitpos: [7:0]; default: 0;
/** out_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t out_data_w1tc:8;
uint32_t out_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
@ -114,10 +114,10 @@ typedef union {
*/
typedef union {
struct {
/** status_w1ts : WT; bitpos: [7:0]; default: 0;
/** status_intr_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t status_w1ts:8;
uint32_t status_intr_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
@ -128,10 +128,10 @@ typedef union {
*/
typedef union {
struct {
/** status_w1tc : WT; bitpos: [7:0]; default: 0;
/** status_intr_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t status_w1tc:8;
uint32_t status_intr_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;

19
components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_adc.c
View File

@ -12,6 +12,7 @@
#include "ulp_lp_core_lp_adc_shared.h"
#include "soc/adc_periph.h"
#include "driver/gpio.h"
#include "driver/rtc_io.h"
#include "driver/temperature_sensor.h"
#include "unity.h"
@ -33,17 +34,17 @@ static void test_adc_set_io_level(adc_unit_t unit, adc_channel_t channel, bool l
{
TEST_ASSERT(channel < SOC_ADC_CHANNEL_NUM(unit) && "invalid channel");
#if !ADC_LL_RTC_GPIO_SUPPORTED
uint32_t io_num = ADC_GET_IO_NUM(unit, channel);
TEST_ESP_OK(gpio_set_pull_mode(io_num, (level ? GPIO_PULLUP_ONLY : GPIO_PULLDOWN_ONLY)));
#else
gpio_num_t io_num = ADC_GET_IO_NUM(unit, channel);
if (level) {
TEST_ESP_OK(rtc_gpio_pullup_en(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_dis(io_num));
} else {
TEST_ESP_OK(rtc_gpio_pullup_dis(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_en(io_num));
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
if (rtc_gpio_is_valid_gpio(io_num)) {
if (level) {
TEST_ESP_OK(rtc_gpio_pullup_en(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_dis(io_num));
} else {
TEST_ESP_OK(rtc_gpio_pullup_dis(io_num));
TEST_ESP_OK(rtc_gpio_pulldown_en(io_num));
}
}
#endif
}

1
examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c
View File

@ -13,6 +13,7 @@
#include "esp_sleep.h"
#include "esp_flash.h"
#include "driver/rtc_io.h"
#include "driver/gpio.h"
#include "driver/uart.h"
#include "argtable3/argtable3.h"
#include "freertos/FreeRTOS.h"

1
examples/system/console/advanced/components/cmd_system/cmd_system_sleep.c
View File

@ -22,6 +22,7 @@
#include "esp_chip_info.h"
#include "esp_sleep.h"
#include "driver/rtc_io.h"
#include "driver/gpio.h"
#include "driver/uart.h"
#include "argtable3/argtable3.h"
#include "cmd_system.h"