mirror of
https://github.com/espressif/esp-idf
synced 2025-03-10 01:29:21 -04:00
test: modify the command/address test a bit to test the LSBFIRST feature
This commit is contained in:
michael
Michael (XIAO Xufeng)
parent
a5a692ef8c
commit
4ae01aed27
@ -390,7 +390,7 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
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trans[4].rxlength = 8*4;
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trans[4].tx_buffer = data_drom;
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trans[4].flags = SPI_TRANS_USE_RXDATA;
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trans[5].length = 8*4;
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trans[5].flags = SPI_TRANS_USE_RXDATA | SPI_TRANS_USE_TXDATA;
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@ -412,7 +412,7 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
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}
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static inline void int_connect( uint32_t gpio, uint32_t sigo, uint32_t sigi )
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static inline void int_connect( uint32_t gpio, uint32_t sigo, uint32_t sigi )
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{
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gpio_matrix_out( gpio, sigo, false, false );
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gpio_matrix_in( gpio, sigi, false );
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@ -430,7 +430,7 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]")
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esp_err_t ret;
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spi_device_handle_t spi;
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spi_bus_config_t buscfg={
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.miso_io_num=PIN_NUM_MISO,
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.miso_io_num=PIN_NUM_MISO,
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.mosi_io_num=PIN_NUM_MOSI,
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.sclk_io_num=PIN_NUM_CLK,
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.quadwp_io_num=-1,
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@ -441,7 +441,7 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]")
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.mode=0, //SPI mode 0
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.spics_io_num=PIN_NUM_CS, //CS pin
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.queue_size=7, //We want to be able to queue 7 transactions at a time
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.pre_cb=NULL,
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.pre_cb=NULL,
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};
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//Initialize the SPI bus
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ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1);
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@ -454,14 +454,14 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]")
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int_connect( PIN_NUM_MOSI, HSPID_OUT_IDX, HSPIQ_IN_IDX );
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memset(rx_buf, 0x66, 320);
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for ( int i = 0; i < 8; i ++ ) {
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memset( rx_buf, 0x66, sizeof(rx_buf));
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spi_transaction_t t = {};
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t.length = 8*(i+1);
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t.rxlength = 0;
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t.tx_buffer = tx_buf+2*i;
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t.tx_buffer = tx_buf+2*i;
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t.rx_buffer = rx_buf + i;
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if ( i == 1 ) {
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@ -470,7 +470,7 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]")
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} else if ( i == 2 ) {
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//test rx length != tx_length
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t.rxlength = t.length - 8;
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}
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}
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spi_device_transmit( spi, &t );
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for( int i = 0; i < 16; i ++ ) {
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@ -486,7 +486,7 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]")
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} else {
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//normal check
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TEST_ASSERT( memcmp(t.tx_buffer, t.rx_buffer, t.length/8)==0 );
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}
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}
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}
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TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK);
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@ -495,14 +495,15 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]")
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static const char MASTER_TAG[] = "test_master";
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static const char SLAVE_TAG[] = "test_slave";
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DRAM_ATTR static uint8_t master_send[] = {0x93, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xaa, 0xcc, 0xff, 0xee, 0x55, 0x77, 0x88, 0x43};
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//DRAM_ATTR static uint8_t master_send[] = {0x93, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xaa, 0xcc, 0xff, 0xee, 0x55, 0x77, 0x88, 0x43};
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DRAM_ATTR static uint8_t slave_send[] = { 0xaa, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, 0x13, 0x57, 0x9b, 0xdf, 0x24, 0x68, 0xac, 0xe0 };
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/*
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static void master_init( spi_device_handle_t* spi, int mode, uint32_t speed)
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{
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esp_err_t ret;
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spi_bus_config_t buscfg={
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.miso_io_num=PIN_NUM_MISO,
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.miso_io_num=PIN_NUM_MISO,
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.mosi_io_num=PIN_NUM_MOSI,
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.sclk_io_num=PIN_NUM_CLK,
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.quadwp_io_num=-1,
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@ -513,7 +514,7 @@ static void master_init( spi_device_handle_t* spi, int mode, uint32_t speed)
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.mode=mode, //SPI mode 0
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.spics_io_num=PIN_NUM_CS, //CS pin
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.queue_size=16, //We want to be able to queue 7 transactions at a time
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.pre_cb=NULL,
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.pre_cb=NULL,
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.cs_ena_pretrans = 0,
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};
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//Initialize the SPI bus
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@ -546,6 +547,7 @@ static void slave_init(int mode, int dma_chan)
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//Initialize SPI slave interface
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TEST_ESP_OK( spi_slave_initialize(VSPI_HOST, &buscfg, &slvcfg, dma_chan) );
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}
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*/
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typedef struct {
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uint32_t len;
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@ -604,6 +606,7 @@ static void task_slave(void* arg)
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t.tx_buffer = txdata.start;
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t.rx_buffer = recvbuf+4;
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//loop until trans_len != 0 to skip glitches
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memset(recvbuf, 0x66, sizeof(recvbuf));
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do {
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TEST_ESP_OK( spi_slave_transmit( VSPI_HOST, &t, portMAX_DELAY ) );
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} while ( t.trans_len == 0 );
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@ -613,118 +616,177 @@ static void task_slave(void* arg)
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}
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}
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TEST_CASE("SPI master variable cmd & addr test","[spi]")
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#define TEST_SPI_HOST HSPI_HOST
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#define TEST_SLAVE_HOST VSPI_HOST
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static uint8_t bitswap(uint8_t in)
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{
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uint8_t *tx_buf=master_send;
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uint8_t rx_buf[320];
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uint8_t *rx_buf_ptr = rx_buf;
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uint8_t out = 0;
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for (int i = 0; i < 8; i++) {
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out = out >> 1;
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if (in&0x80) out |= 0x80;
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in = in << 1;
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}
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return out;
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}
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spi_slave_task_context_t slave_context = {};
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esp_err_t err = init_slave_context( &slave_context );
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TEST_ASSERT( err == ESP_OK );
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#define SPI_BUS_TEST_DEFAULT_CONFIG() {\
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.miso_io_num=PIN_NUM_MISO, \
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.mosi_io_num=PIN_NUM_MOSI,\
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.sclk_io_num=PIN_NUM_CLK,\
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.quadwp_io_num=-1,\
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.quadhd_io_num=-1\
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}
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#define SPI_DEVICE_TEST_DEFAULT_CONFIG() {\
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.clock_speed_hz=10*1000*1000,\
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.mode=0,\
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.spics_io_num=PIN_NUM_CS,\
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.queue_size=16,\
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.pre_cb=NULL, \
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.cs_ena_pretrans = 0,\
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.cs_ena_posttrans = 0,\
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}
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#define SPI_SLAVE_TEST_DEFAULT_CONFIG() {\
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.mode=0,\
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.spics_io_num=PIN_NUM_CS,\
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.queue_size=3,\
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.flags=0,\
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}
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void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)
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{
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spi_device_handle_t spi;
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//initial master, mode 0, 1MHz
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master_init( &spi, 0, 1*1000*1000 );
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//initial slave, mode 0, no dma
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slave_init(0, 0);
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ESP_LOGI(MASTER_TAG, ">>>>>>>>> TEST %s FIRST <<<<<<<<<<<", lsb_first?"LSB":"MSB");
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//do internal connection
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//initial master, mode 0, 1MHz
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spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG();
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TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1));
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spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG();
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devcfg.clock_speed_hz = 1*1000*1000;
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if (lsb_first) devcfg.flags |= SPI_DEVICE_BIT_LSBFIRST;
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TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi));
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//connecting pins to two peripherals breaks the output, fix it.
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int_connect( PIN_NUM_MOSI, HSPID_OUT_IDX, VSPIQ_IN_IDX );
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int_connect( PIN_NUM_MISO, VSPIQ_OUT_IDX, HSPID_IN_IDX );
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int_connect( PIN_NUM_CS, HSPICS0_OUT_IDX, VSPICS0_IN_IDX );
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int_connect( PIN_NUM_CLK, HSPICLK_OUT_IDX, VSPICLK_IN_IDX );
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for (int i= 0; i < 8; i++) {
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//prepare slave tx data
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slave_txdata_t slave_txdata = (slave_txdata_t) {
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.start = slave_send,
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.len = 256,
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};
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xQueueSend(slave_context->data_to_send, &slave_txdata, portMAX_DELAY);
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vTaskDelay(50);
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//prepare master tx data
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int cmd_bits = (i+1)*2;
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int addr_bits = 56-8*i;
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int round_up = (cmd_bits+addr_bits+7)/8*8;
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addr_bits = round_up - cmd_bits;
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spi_transaction_ext_t trans = (spi_transaction_ext_t) {
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.base = {
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.flags = SPI_TRANS_VARIABLE_CMD | SPI_TRANS_VARIABLE_ADDR,
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.addr = 0x456789abcdef0123,
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.cmd = 0xcdef,
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},
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.command_bits = cmd_bits,
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.address_bits = addr_bits,
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};
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ESP_LOGI( MASTER_TAG, "===== test%d =====", i );
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ESP_LOGI(MASTER_TAG, "cmd_bits： %d, addr_bits: %d", cmd_bits, addr_bits);
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TEST_ESP_OK(spi_device_transmit(spi, (spi_transaction_t*)&trans));
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//wait for both master and slave end
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size_t rcv_len;
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slave_rxdata_t *rcv_data = xRingbufferReceive(slave_context->data_received, &rcv_len, portMAX_DELAY);
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rcv_len-=4;
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uint8_t *buffer = rcv_data->data;
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ESP_LOGI(SLAVE_TAG, "trans_len: %d", rcv_len);
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TEST_ASSERT_EQUAL(rcv_len, (rcv_data->len+7)/8);
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TEST_ASSERT_EQUAL(rcv_data->len, cmd_bits+addr_bits);
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ESP_LOG_BUFFER_HEX("slave rx", buffer, rcv_len);
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uint16_t cmd_expected = trans.base.cmd & (BIT(cmd_bits) - 1);
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uint64_t addr_expected = trans.base.addr & ((1ULL<<addr_bits) - 1);
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uint8_t *data_ptr = buffer;
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uint16_t cmd_got = *(uint16_t*)data_ptr;
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data_ptr += cmd_bits/8;
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cmd_got = __builtin_bswap16(cmd_got);
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cmd_got = cmd_got >> (16-cmd_bits);
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int remain_bits = cmd_bits % 8;
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uint64_t addr_got = *(uint64_t*)data_ptr;
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data_ptr += 8;
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addr_got = __builtin_bswap64(addr_got);
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addr_got = (addr_got << remain_bits);
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addr_got |= (*data_ptr >> (8-remain_bits));
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addr_got = addr_got >> (64-addr_bits);
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if (lsb_first) {
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cmd_got = __builtin_bswap16(cmd_got);
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addr_got = __builtin_bswap64(addr_got);
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uint8_t *swap_ptr = (uint8_t*)&cmd_got;
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swap_ptr[0] = bitswap(swap_ptr[0]);
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swap_ptr[1] = bitswap(swap_ptr[1]);
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cmd_got = cmd_got >> (16-cmd_bits);
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swap_ptr = (uint8_t*)&addr_got;
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for (int j = 0; j < 8; j++) swap_ptr[j] = bitswap(swap_ptr[j]);
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addr_got = addr_got >> (64-addr_bits);
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}
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ESP_LOGI(SLAVE_TAG, "cmd_got: %04X, addr_got: %08X%08X", cmd_got, (uint32_t)(addr_got>>32), (uint32_t)addr_got);
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TEST_ASSERT_EQUAL_HEX16(cmd_expected, cmd_got);
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if (addr_bits > 0) {
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TEST_ASSERT_EQUAL_HEX32(addr_expected, addr_got);
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TEST_ASSERT_EQUAL_HEX32(addr_expected >> 8, addr_got >> 8);
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}
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//clean
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vRingbufferReturnItem(slave_context->data_received, buffer);
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}
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TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK);
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TEST_ASSERT(spi_bus_free(TEST_SPI_HOST) == ESP_OK);
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}
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TEST_CASE("SPI master variable cmd & addr test","[spi]")
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{
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spi_slave_task_context_t slave_context = {};
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esp_err_t err = init_slave_context( &slave_context );
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TEST_ASSERT( err == ESP_OK );
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TaskHandle_t handle_slave;
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xTaskCreate( task_slave, "spi_slave", 4096, &slave_context, 0, &handle_slave);
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slave_txdata_t slave_txdata[16];
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spi_transaction_ext_t trans[16];
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for( int i= 0; i < 16; i ++ ) {
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//prepare slave tx data
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slave_txdata[i] = (slave_txdata_t) {
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.start = slave_send + 4*(i%3),
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.len = 256,
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};
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xQueueSend( slave_context.data_to_send, &slave_txdata[i], portMAX_DELAY );
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//prepare master tx data
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trans[i] = (spi_transaction_ext_t) {
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.base = {
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.flags = SPI_TRANS_VARIABLE_CMD | SPI_TRANS_VARIABLE_ADDR,
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.addr = 0x456789ab,
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.cmd = 0xcdef,
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//initial slave, mode 0, no dma
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int dma_chan = 0;
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int slave_mode = 0;
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spi_bus_config_t slv_buscfg=SPI_BUS_TEST_DEFAULT_CONFIG();
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spi_slave_interface_config_t slvcfg=SPI_SLAVE_TEST_DEFAULT_CONFIG();
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slvcfg.mode = slave_mode;
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//Initialize SPI slave interface
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TEST_ESP_OK( spi_slave_initialize(TEST_SLAVE_HOST, &slv_buscfg, &slvcfg, dma_chan) );
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.length = 8*i,
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.tx_buffer = tx_buf+i,
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.rx_buffer = rx_buf_ptr,
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},
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.command_bits = ((i+1)%3) * 8,
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.address_bits = ((i/3)%5) * 8,
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};
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if ( trans[i].base.length == 0 ) {
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trans[i].base.tx_buffer = NULL;
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trans[i].base.rx_buffer = NULL;
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} else {
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rx_buf_ptr += (trans[i].base.length + 31)/32*4;
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}
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}
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vTaskDelay(10);
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for ( int i = 0; i < 16; i ++ ) {
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TEST_ESP_OK (spi_device_queue_trans( spi, (spi_transaction_t*)&trans[i], portMAX_DELAY ) );
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vTaskDelay(10);
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}
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for( int i= 0; i < 16; i ++ ) {
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//wait for both master and slave end
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ESP_LOGI( MASTER_TAG, "===== test%d =====", i );
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spi_transaction_ext_t *t;
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size_t rcv_len;
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spi_device_get_trans_result( spi, (spi_transaction_t**)&t, portMAX_DELAY );
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TEST_ASSERT( t == &trans[i] );
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if ( trans[i].base.length != 0 ) {
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ESP_LOG_BUFFER_HEX( "master tx", trans[i].base.tx_buffer, trans[i].base.length/8 );
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ESP_LOG_BUFFER_HEX( "master rx", trans[i].base.rx_buffer, trans[i].base.length/8 );
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} else {
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ESP_LOGI( "master tx", "no data" );
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ESP_LOGI( "master rx", "no data" );
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}
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slave_rxdata_t *rcv_data = xRingbufferReceive( slave_context.data_received, &rcv_len, portMAX_DELAY );
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uint8_t *buffer = rcv_data->data;
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rcv_len = rcv_data->len;
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ESP_LOGI(SLAVE_TAG, "trans_len: %d", rcv_len);
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ESP_LOG_BUFFER_HEX( "slave tx", slave_txdata[i].start, (rcv_len+7)/8);
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ESP_LOG_BUFFER_HEX( "slave rx", buffer, (rcv_len+7)/8);
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//check result
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uint8_t *ptr_addr = (uint8_t*)&t->base.addr;
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uint8_t *ptr_cmd = (uint8_t*)&t->base.cmd;
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for ( int j = 0; j < t->command_bits/8; j ++ ) {
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TEST_ASSERT_EQUAL( buffer[j], ptr_cmd[t->command_bits/8-j-1] );
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}
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for ( int j = 0; j < t->address_bits/8; j ++ ) {
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TEST_ASSERT_EQUAL( buffer[t->command_bits/8+j], ptr_addr[t->address_bits/8-j-1] );
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}
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if ( t->base.length != 0) {
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TEST_ASSERT_EQUAL_HEX8_ARRAY(t->base.tx_buffer, buffer + (t->command_bits + t->address_bits)/8, t->base.length/8);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_txdata[i].start + (t->command_bits + t->address_bits)/8, t->base.rx_buffer, t->base.length/8);
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}
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TEST_ASSERT_EQUAL( t->base.length + t->command_bits + t->address_bits, rcv_len );
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//clean
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vRingbufferReturnItem( slave_context.data_received, buffer );
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}
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test_cmd_addr(&slave_context, false);
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test_cmd_addr(&slave_context, true);
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vTaskDelete( handle_slave );
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handle_slave = 0;
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deinit_slave_context(&slave_context);
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TEST_ASSERT(spi_slave_free(VSPI_HOST) == ESP_OK);
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TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK);
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TEST_ASSERT(spi_bus_free(HSPI_HOST) == ESP_OK);
|
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TEST_ASSERT(spi_slave_free(TEST_SLAVE_HOST) == ESP_OK);
|
||||
|
||||
ESP_LOGI(MASTER_TAG, "test passed.");
|
||||
}
|
||||
|
||||
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Reference in New Issue
Block a user