test(mspi): test 120m sdr flash 200m ddr psram on esp32p4

This commit is contained in:
Armando 2024-11-19 11:48:27 +08:00
parent 1eef2e8c19
commit 4b966ef78d
21 changed files with 68 additions and 10 deletions

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@ -20,7 +20,7 @@ components/esp_hw_support/test_apps/host_test_linux:
components/esp_hw_support/test_apps/mspi:
disable:
- if: IDF_TARGET != "esp32s3"
- if: IDF_TARGET not in ["esp32s3", "esp32p4"]
components/esp_hw_support/test_apps/mspi_psram_with_dfs:
disable:

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@ -1,5 +1,5 @@
| Supported Targets | ESP32-S3 |
| ----------------- | -------- |
| Supported Targets | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- |
This project tests if Flash and PSRAM can work under different configurations.
To add new configuration, create one more sdkconfig.ci.NAME file in this directory.

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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
@ -22,9 +22,15 @@ static void sorted_array_insert(uint32_t *array, uint32_t *size, uint32_t item)
(*size)++;
}
#if CONFIG_IDF_TARGET_ESP32S3
#define TEST_TIME_CNT 10
#define TEST_TIME_LIMIT_US 10
TEST_CASE("MSPI: Test mspi timing turning time cost", "[mspi]")
#elif CONFIG_IDF_TARGET_ESP32P4
#define TEST_TIME_CNT 30
#define TEST_TIME_LIMIT_US 30
#endif
TEST_CASE("MSPI: Test mspi timing tuning time cost", "[mspi]")
{
uint64_t start, end;
uint32_t cost, index_1 = 0, index_2 = 0;

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@ -1,13 +1,12 @@
# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
import os
import pathlib
import pytest
from pytest_embedded_idf import IdfDut
MSPI_F8R8_configs = [p.name.replace('sdkconfig.ci.', '') for p in pathlib.Path(os.path.dirname(__file__)).glob('sdkconfig.ci.f8r8*')]
MSPI_F8R8_configs = [p.name.replace('sdkconfig.ci.', '') for p in pathlib.Path(os.path.dirname(__file__)).glob('sdkconfig.ci.esp32s3_f8r8*')]
@pytest.mark.esp32s3
@ -18,7 +17,7 @@ def test_flash8_psram8(dut: IdfDut) -> None:
# For F4R8 board (Quad Flash and Octal PSRAM)
MSPI_F4R8_configs = [p.name.replace('sdkconfig.ci.', '') for p in pathlib.Path(os.path.dirname(__file__)).glob('sdkconfig.ci.f4r8*')]
MSPI_F4R8_configs = [p.name.replace('sdkconfig.ci.', '') for p in pathlib.Path(os.path.dirname(__file__)).glob('sdkconfig.ci.esp32s3_f4r8*')]
@pytest.mark.esp32s3
@ -29,7 +28,7 @@ def test_flash4_psram8(dut: IdfDut) -> None:
# For F4R4 board (Quad Flash and Quad PSRAM)
MSPI_F4R4_configs = [p.name.replace('sdkconfig.ci.', '') for p in pathlib.Path(os.path.dirname(__file__)).glob('sdkconfig.ci.f4r4*')]
MSPI_F4R4_configs = [p.name.replace('sdkconfig.ci.', '') for p in pathlib.Path(os.path.dirname(__file__)).glob('sdkconfig.ci.esp32s3_f4r4*')]
@pytest.mark.esp32s3
@ -37,3 +36,16 @@ MSPI_F4R4_configs = [p.name.replace('sdkconfig.ci.', '') for p in pathlib.Path(o
@pytest.mark.parametrize('config', MSPI_F4R4_configs, indirect=True)
def test_flash4_psram4(dut: IdfDut) -> None:
dut.run_all_single_board_cases()
@pytest.mark.esp32p4
@pytest.mark.generic
@pytest.mark.parametrize(
'config',
[
'esp32p4_120sdr_200ddr',
],
indirect=True,
)
def test_flash_psram_esp32p4(dut: IdfDut) -> None:
dut.run_all_single_board_cases()

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@ -0,0 +1,8 @@
CONFIG_IDF_TARGET="esp32p4"
CONFIG_IDF_EXPERIMENTAL_FEATURES=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_SPEED_200M=y
CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
CONFIG_SPI_FLASH_HPM_ENA=y
CONFIG_BOOTLOADER_FLASH_DC_AWARE=y

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@ -1,5 +1,7 @@
# Legacy, F4R4, Flash 120M SDR, PSRAM disable
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F4R4, Flash 120M SDR, PSRAM 120M SDR
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F4R4, Flash 120M SDR, PSRAM 40M SDR
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F4R4, Flash 120M SDR, PSRAM disable, compiler -Os and silent
CONFIG_IDF_TARGET="esp32s3"
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y

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@ -1,5 +1,7 @@
# Legacy, F4R4, Flash 40M SDR, PSRAM 120M SDR
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F4R4, Flash 80M SDR, PSRAM 80M SDR
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F4R8, Flash 120M SDR, PSRAM disable
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F4R8, Flash 80M SDR, PSRAM 40M DDR
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F4R8, Flash 80M SDR, PSRAM 80M DDR
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F8R8, Flash 120M SDR, PSRAM disable
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F8R8, Flash 40M DDR, PSRAM 40M DDR
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F8R8, Flash 40M DDR, PSRAM 80M DDR
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F8R8, Flash 80M DDR, PSRAM 40M DDR
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F8R8, Flash 80M DDR, PSRAM 80M DDR
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F8R8, Flash 80M DDR, PSRAM 80M DDR
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"

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@ -1,5 +1,7 @@
# Legacy, F8R8, Flash 80M SDR, PSRAM 80M DDR
CONFIG_IDF_TARGET="esp32s3"
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"