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Merge branch 'fix/coverity_reports_security' into 'master'
fix(security): Fixed coverity warnings from `nvs_sec_provider` and `esp_tee` components Closes IDF-12190, IDF-12194, and IDF-12197 See merge request espressif/esp-idf!36721
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4e072b3f8a
@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -113,34 +113,26 @@ void panic_print_isrcause(const void *f, int core)
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{
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RvExcFrame *regs = (RvExcFrame *) f;
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/* Please keep in sync with PANIC_RSN_* defines */
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static const char *pseudo_reason[] = {
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"Unknown reason",
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"Interrupt wdt timeout on CPU0",
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"Interrupt wdt timeout on CPU1",
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"Cache error",
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};
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const void *addr = (void *) regs->mepc;
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const char *rsn = pseudo_reason[0];
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const char *rsn = "Unknown reason";
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/* The mcause has been set by the CPU when the panic occurred.
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* All SoC-level panic will call this function, thus, this register
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* lets us know which error was triggered. */
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if (regs->mcause == ETS_CACHEERR_INUM) {
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/* Panic due to a cache error, multiple cache error are possible,
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* assign function print_cache_err_details to our structure's
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* details field. As its name states, it will give more details
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* about why the error happened. */
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rsn = pseudo_reason[PANIC_RSN_CACHEERR];
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} else if (regs->mcause == ETS_INT_WDT_INUM) {
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/* Watchdog interrupt occurred, get the core on which it happened
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* and update the reason/message accordingly. */
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#if SOC_CPU_NUM > 1
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_Static_assert(PANIC_RSN_INTWDT_CPU0 + 1 == PANIC_RSN_INTWDT_CPU1,
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"PANIC_RSN_INTWDT_CPU1 must be equal to PANIC_RSN_INTWDT_CPU0 + 1");
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switch (regs->mcause) {
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case ETS_CACHEERR_INUM:
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rsn = "Cache error";
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break;
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case PANIC_RSN_INTWDT_CPU0:
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rsn = "Interrupt wdt timeout on CPU0";
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break;
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#if SOC_CPU_CORES_NUM > 1
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case PANIC_RSN_INTWDT_CPU1:
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rsn = "Interrupt wdt timeout on CPU1";
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break;
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#endif
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rsn = pseudo_reason[PANIC_RSN_INTWDT_CPU0 + core];
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default:
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break;
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}
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const char *desc = "Exception was unhandled.";
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@ -1,7 +1,7 @@
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/*
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* NVS Encryption with HMAC-based encryption key protection scheme example
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*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Unlicense OR CC0-1.0
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*/
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@ -39,14 +39,7 @@ static esp_err_t example_custom_nvs_part_init(const char *label)
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esp_err_t ret = ESP_FAIL;
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#if defined(CONFIG_NVS_ENCRYPTION) && defined(CONFIG_NVS_SEC_KEY_PROTECT_USING_HMAC)
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nvs_sec_cfg_t cfg = {};
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nvs_sec_scheme_t *sec_scheme_handle = NULL;
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nvs_sec_config_hmac_t sec_scheme_cfg = NVS_SEC_PROVIDER_CFG_HMAC_DEFAULT();
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ret = nvs_sec_provider_register_hmac(&sec_scheme_cfg, &sec_scheme_handle);
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if (ret != ESP_OK) {
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return ret;
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}
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nvs_sec_scheme_t *sec_scheme_handle = nvs_flash_get_default_security_scheme();
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ret = nvs_flash_read_security_cfg_v2(sec_scheme_handle, &cfg);
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if (ret != ESP_OK) {
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Unlicense OR CC0-1.0
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*/
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@ -72,12 +72,7 @@ static esp_err_t example_custom_nvs_part_init(const char *name)
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#if CONFIG_NVS_ENCRYPTION
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esp_err_t ret = ESP_FAIL;
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nvs_sec_cfg_t cfg = {};
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nvs_sec_scheme_t *sec_scheme_handle = NULL;
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nvs_sec_config_hmac_t sec_scheme_cfg = NVS_SEC_PROVIDER_CFG_HMAC_DEFAULT();
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ret = nvs_sec_provider_register_hmac(&sec_scheme_cfg, &sec_scheme_handle);
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if (ret != ESP_OK) {
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return ret;
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}
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nvs_sec_scheme_t *sec_scheme_handle = nvs_flash_get_default_security_scheme();
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ret = nvs_flash_read_security_cfg_v2(sec_scheme_handle, &cfg);
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if (ret != ESP_OK) {
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