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Merge branch 'bugfix/esp32c3_fix_adv_flow_control_can_not_enable' into 'master'

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fix esp32c3 BLE can't enable adv flow control func

Closes WIFI-3406, WIFI-3385, WIFI-3383, and WIFI-3284

See merge request espressif/esp-idf!12302
This commit is contained in:
Jiang Jiang Jian 2021-02-09 01:06:09 +08:00
commit 52f1f68dc7
7 changed files with 41 additions and 8 deletions
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2
components/bt/controller/lib

@ -1 +1 @@
Subproject commit 77eb1e91662fe4a5e9c783d25c5c9ae208c1af4b
Subproject commit 072dc4370b147e4b37a7e35babc5ab518185432b

27
components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h
View File

@ -148,6 +148,7 @@
#define UC_BT_SMP_SLAVE_CON_PARAMS_UPD_ENABLE FALSE
#endif
#if CONFIG_BT_CTRL_ESP32
//BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP
#ifdef CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP
#define UC_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP
@ -169,6 +170,32 @@
#define UC_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
#endif
#endif //CONFIG_BT_CTRL_ESP32
#if (CONFIG_BT_CTRL_ESP32C3 || CONFIG_BT_CTRL_ESP32S3)
//BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP
#ifdef CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP
#define UC_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP
#else
#define UC_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP FALSE
#endif
//SMP_SLAVE_CON_PARAMS_UPD_ENABLE
#ifdef CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM
#define UC_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM
#else
#define UC_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
#endif
//BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP
#ifdef CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD
#define UC_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD
#else
#define UC_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
#endif
#endif //(CONFIG_BT_CTRL_ESP32C3 || CONFIG_BT_CTRL_ESP32S3)
//BT ACL CONNECTIONS
#ifdef CONFIG_BT_ACL_CONNECTIONS
#define UC_BT_ACL_CONNECTIONS CONFIG_BT_ACL_CONNECTIONS

4
components/bt/include/esp32c3/include/esp_bt.h
View File

@ -104,8 +104,8 @@ enum {
#endif
/* normal adv cache size */
#ifdef CONFIG_BT_SCAN_DUPL_CACHE_SIZE
#define NORMAL_SCAN_DUPLICATE_CACHE_SIZE CONFIG_BT_SCAN_DUPL_CACHE_SIZE
#ifdef CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE
#define NORMAL_SCAN_DUPLICATE_CACHE_SIZE CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE
#else
#define NORMAL_SCAN_DUPLICATE_CACHE_SIZE 20
#endif

4
components/esp_hw_support/port/esp32c3/regi2c_ctrl.h
View File

@ -40,6 +40,10 @@ extern "C" {
#endif
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)

2
components/esp_hw_support/port/esp32c3/rtc_clk.c
View File

@ -221,6 +221,8 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
uint8_t dcur;
uint8_t dbias;
CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
SET_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
if (pll_freq == RTC_PLL_FREQ_480M) {
/* Set this register to let the digital part know 480M PLL is used */
SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);

8
components/esp_rom/esp32c3/ld/esp32c3.rom.ld
View File

@ -1818,7 +1818,7 @@ rom_i2c_readReg = 0x40001954;
rom_i2c_readReg_Mask = 0x40001958;
rom_i2c_writeReg = 0x4000195c;
rom_i2c_writeReg_Mask = 0x40001960;
rom_index_to_txbbgain = 0x40001964;
/* rom_index_to_txbbgain = 0x40001964; */
rom_iq_est_disable = 0x40001968;
rom_iq_est_enable = 0x4000196c;
rom_linear_to_db = 0x40001970;
@ -1853,14 +1853,14 @@ rom_set_chan_cal_interp = 0x400019e0;
rom_set_loopback_gain = 0x400019e4;
rom_set_noise_floor = 0x400019e8;
rom_set_rxclk_en = 0x400019ec;
rom_set_tx_dig_gain = 0x400019f0;
/* rom_set_tx_dig_gain = 0x400019f0; */
/* rom_set_txcap_reg = 0x400019f4; */
rom_set_txclk_en = 0x400019f8;
rom_spur_cal = 0x400019fc;
rom_spur_reg_write_one_tone = 0x40001a00;
rom_target_power_add_backoff = 0x40001a04;
rom_tx_pwctrl_bg_init = 0x40001a08;
rom_txbbgain_to_index = 0x40001a0c;
/* rom_txbbgain_to_index = 0x40001a0c; */
rom_wifi_11g_rate_chg = 0x40001a10;
rom_write_gain_mem = 0x40001a14;
chip726_phyrom_version = 0x40001a18;
@ -1931,4 +1931,4 @@ rom_write_pll_cap_mem = 0x40001b18;
rom_pll_correct_dcap = 0x40001b1c;
rom_phy_en_hw_set_freq = 0x40001b20;
rom_phy_dis_hw_set_freq = 0x40001b24;
rom_pll_vol_cal = 0x40001b28;
/* rom_pll_vol_cal = 0x40001b28; */

2
components/esp_wifi/lib

@ -1 +1 @@
Subproject commit c813b4b14704132002d154298384c985c10a2b6d
Subproject commit 682a6588dab0a18ef79630a0f3b59e551be35a43