From 099c5a8a69a8af6cd7c24e991b643c5b0a4550ac Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 27 Feb 2025 15:32:28 +0800 Subject: [PATCH 1/2] fix(axi_icm): qos can be applied to read and write independently --- .../hal/esp32p4/include/hal/axi_icm_ll.h | 23 ++++++++++++++----- 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/components/hal/esp32p4/include/hal/axi_icm_ll.h b/components/hal/esp32p4/include/hal/axi_icm_ll.h index eff188d4cd..bfeb5225b9 100644 --- a/components/hal/esp32p4/include/hal/axi_icm_ll.h +++ b/components/hal/esp32p4/include/hal/axi_icm_ll.h @@ -27,13 +27,22 @@ typedef enum { AXI_ICM_MASTER_H264_M1 = 12, // H264 master port 1 } axi_icm_ll_master_id_t; +/** + * @brief AXI ICM has independent channels for read and write access. + */ +typedef enum { + AXI_ICM_ACCESS_READ = 0, + AXI_ICM_ACCESS_WRITE = 1, +} axi_icm_ll_access_type_t; + /** * @brief Set QoS burstiness for a master port, also enable the regulator * * @param mid Master port ID * @param burstiness Burstiness value. It represents the depth of the token bucket. + * @param access_type 0: read, 1: write */ -static inline void axi_icm_ll_set_qos_burstiness(axi_icm_ll_master_id_t mid, uint32_t burstiness) +static inline void axi_icm_ll_set_qos_burstiness(axi_icm_ll_master_id_t mid, uint32_t burstiness, axi_icm_ll_access_type_t access_type) { HAL_ASSERT(burstiness >= 1 && burstiness <= 256); // wait for the previous command to finish @@ -43,8 +52,8 @@ static inline void axi_icm_ll_set_qos_burstiness(axi_icm_ll_master_id_t mid, uin AXI_ICM_QOS.data.val = (burstiness - 1) << 16 | 0x1; // command write operation AXI_ICM_QOS.cmd.reg_axi_rd_wr_cmd = 1; - // write addr channel - AXI_ICM_QOS.cmd.reg_rd_wr_chan = 1; + // set the qos for read channel or write channel + AXI_ICM_QOS.cmd.reg_rd_wr_chan = access_type; // select master port AXI_ICM_QOS.cmd.reg_axi_master_port = mid; // set command type: burstiness regulator @@ -69,8 +78,10 @@ static inline void axi_icm_ll_set_qos_burstiness(axi_icm_ll_master_id_t mid, uin * @param mid Master port ID * @param peak_level Peak level, lower value means higher rate * @param transaction_level Transaction level, lower value means higher rate + * @param access_type 0: read, 1: write */ -static inline void axi_icm_ll_set_qos_peak_transaction_rate(axi_icm_ll_master_id_t mid, uint32_t peak_level, uint32_t transaction_level) +static inline void axi_icm_ll_set_qos_peak_transaction_rate(axi_icm_ll_master_id_t mid, uint32_t peak_level, + uint32_t transaction_level, axi_icm_ll_access_type_t access_type) { HAL_ASSERT(peak_level < transaction_level && transaction_level <= 11); while (AXI_ICM_QOS.cmd.reg_axi_cmd_en); @@ -79,8 +90,8 @@ static inline void axi_icm_ll_set_qos_peak_transaction_rate(axi_icm_ll_master_id AXI_ICM_QOS.data.val = (0x80000000 >> peak_level) + (0x8000 >> transaction_level); // command write operation AXI_ICM_QOS.cmd.reg_axi_rd_wr_cmd = 1; - // write addr channel - AXI_ICM_QOS.cmd.reg_rd_wr_chan = 1; + // set the qos for read channel or write channel + AXI_ICM_QOS.cmd.reg_rd_wr_chan = access_type; // select master port AXI_ICM_QOS.cmd.reg_axi_master_port = mid; // set command type: peak rate xct rate From 2cd87223a87a8bbb7f28974d1ec46f9e059e9c53 Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 26 Feb 2025 11:30:50 +0800 Subject: [PATCH 2/2] feat(l2mem): enable buffer mode for ahb burst access --- components/esp_system/port/cpu_start.c | 6 ++++ components/hal/esp32p4/include/hal/l2mem_ll.h | 31 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 components/hal/esp32p4/include/hal/l2mem_ll.h diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index dce7177fff..82d635e757 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -58,6 +58,7 @@ #include "esp32c2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32P4 #include "soc/hp_sys_clkrst_reg.h" +#include "hal/l2mem_ll.h" #elif CONFIG_IDF_TARGET_ESP32H21 #include "esp_memprot.h" #endif @@ -403,6 +404,11 @@ void IRAM_ATTR call_start_cpu0(void) ); #endif +#if CONFIG_IDF_TARGET_ESP32P4 + // enable the buffer mode before any AHB burst happens, that's why we do it here + l2mem_ll_enable_ahb_burst_buffer(true, true); +#endif + #if SOC_BRANCH_PREDICTOR_SUPPORTED esp_cpu_branch_prediction_enable(); #endif diff --git a/components/hal/esp32p4/include/hal/l2mem_ll.h b/components/hal/esp32p4/include/hal/l2mem_ll.h new file mode 100644 index 0000000000..6275051d59 --- /dev/null +++ b/components/hal/esp32p4/include/hal/l2mem_ll.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "soc/hp_system_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the burst buffer for L2 memory + * + * @note During AHB burst access to the L2MEM, in order to reduce the AHB request to the L2MEM arbiter, + * enabling the buffer mode can improve the performance. + * @note This function must be called before any AHB burst access to the L2MEM. + */ +static inline void l2mem_ll_enable_ahb_burst_buffer(bool en_read, bool en_write) +{ + HP_SYSTEM.l2_mem_ahb_buffer_ctrl.l2_mem_ahb_rdbuffer_en = en_read; + HP_SYSTEM.l2_mem_ahb_buffer_ctrl.l2_mem_ahb_wrbuffer_en = en_write; +} + +#ifdef __cplusplus +} +#endif