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Merge branch 'bugfix/freertos_fpu_isr_pins_task' into 'master'

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FreeRTOS: Fix bug where FPU usage in ISR pins the interrupted task.

Closes IDF-6068

See merge request espressif/esp-idf!20573
This commit is contained in:
Darian 2022-10-15 00:40:04 +08:00
commit 54d286de67
2 changed files with 23 additions and 27 deletions
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45
components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_vectors.S
View File

@ -908,35 +908,32 @@ _xt_coproc_exc:
/* Get co-processor state save area of new owner thread. */
call0 XT_RTOS_CP_STATE /* a15 = new owner's save area */
#ifndef CONFIG_FREERTOS_FPU_IN_ISR
beqz a15, .L_goto_invalid
#if CONFIG_FREERTOS_FPU_IN_ISR
beqz a15, .L_skip_core_pin /* CP used in ISR, skip task pinning */
#else
beqz a15, .L_goto_invalid /* not in a thread (invalid) */
#endif
/*When FPU in ISR is enabled we could deal with zeroed a15 */
#if configNUM_CORES > 1
/* CP operations are incompatible with unpinned tasks. Thus we pin the task
to the current running core. */
movi a2, pxCurrentTCB
getcoreid a3 /* a3 = current core ID */
addx4 a2, a3, a2
l32i a2, a2, 0 /* a2 = start of pxCurrentTCB[cpuid] */
addi a2, a2, TASKTCB_XCOREID_OFFSET /* a2 = &TCB.xCoreID */
s32i a3, a2, 0 /* TCB.xCoreID = current core ID */
#endif // configNUM_CORES > 1
#if CONFIG_FREERTOS_FPU_IN_ISR
.L_skip_core_pin:
#endif
/* Enable the co-processor's bit in CPENABLE. */
movi a0, _xt_coproc_mask
rsr a4, CPENABLE /* a4 = CPENABLE */
addx4 a0, a5, a0 /* a0 = &_xt_coproc_mask[n] */
l32i a0, a0, 0 /* a0 = (n << 16) | (1 << n) */
/* FPU operations are incompatible with non-pinned tasks. If we have a FPU operation
here, to keep the entire thing from crashing, it's better to pin the task to whatever
core we're running on now. */
movi a2, pxCurrentTCB
getcoreid a3
addx4 a2, a3, a2
l32i a2, a2, 0 /* a2 = start of pxCurrentTCB[cpuid] */
addi a2, a2, TASKTCB_XCOREID_OFFSET /* offset to xCoreID in tcb struct */
s32i a3, a2, 0 /* store current cpuid */
/* Grab correct xt_coproc_owner_sa for this core */
movi a2, XCHAL_CP_MAX << 2
mull a2, a2, a3 /* multiply by current processor id */
movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
add a3, a3, a2 /* a3 = owner area needed for this processor */
extui a2, a0, 0, 16 /* coprocessor bitmask portion */
or a4, a4, a2 /* a4 = CPENABLE | (1 << n) */
wsr a4, CPENABLE
@ -946,7 +943,11 @@ Keep loading _xt_coproc_owner_sa[n] atomic (=load once, then use that value
everywhere): _xt_coproc_release assumes it works like this in order not to need
locking.
*/
/* Grab correct xt_coproc_owner_sa for this core */
movi a2, XCHAL_CP_MAX << 2
mull a2, a2, a3 /* multiply by current processor id */
movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
add a3, a3, a2 /* a3 = owner area needed for this processor */
/* Get old coprocessor owner thread (save area ptr) and assign new one. */
addx4 a3, a5, a3 /* a3 = &_xt_coproc_owner_sa[n] */

5
components/freertos/test/port/test_fpu_in_isr.c
View File

@ -106,9 +106,6 @@ Expected:
- The ISR using the FPU will not affect the unpinned task's affinity
*/
// Known issue in IDF FreeRTOS (IDF-6068), already fixed in SMP FreeRTOS
#if CONFIG_FREERTOS_SMP
static void unpinned_task(void *arg)
{
// Disable scheduling/preemption to make sure the current task doesn't switch cores
@ -159,6 +156,4 @@ TEST_CASE("FPU: Level 1 ISR does not affect unpinned task", "[freertos]")
vTaskDelay(10); // Short delay to allow task memory to be freed
}
#endif // CONFIG_FREERTOS_SMP
#endif // SOC_CPU_HAS_FPU && CONFIG_FREERTOS_FPU_IN_ISR