From 25731d0c1e0571fa7a7093c9bbe95135293d22c5 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Mon, 30 Dec 2024 20:14:40 +0800 Subject: [PATCH] feat(esp32h21): finnal introduce hello world support --- .gitlab/ci/default-build-test-rules.yml | 1 + .../subproject/main/ld/esp32h21/bootloader.ld | 308 +++ .../main/ld/esp32h21/bootloader.rom.ld | 6 + .../src/bootloader_flash_config_esp32h21.c | 286 +++ .../src/bootloader_clock_init.c | 15 +- .../bootloader_support/src/bootloader_efuse.c | 7 +- .../src/esp32h21/bootloader_esp32h21.c | 173 ++ .../src/esp32h21/bootloader_sha.c | 46 + .../src/esp32h21/bootloader_soc.c | 32 + .../flash_encryption_secure_features.c | 22 + .../esp32h21/secure_boot_secure_features.c | 22 + .../efuse/esp32h21/esp_efuse_rtc_calib.c | 3 + components/esp_driver_gpio/src/gpio.c | 8 +- components/esp_hw_support/CMakeLists.txt | 11 +- .../include/esp_private/sleep_event.h | 2 +- .../esp_hw_support/include/soc/esp32h21/rtc.h | 32 + .../port/esp32h21/CMakeLists.txt | 16 +- .../port/esp32h21/Kconfig.hw_support | 58 + .../esp_hw_support/port/esp32h21/Kconfig.rtc | 39 + .../esp_hw_support/port/esp32h21/chip_info.c | 18 + .../port/esp32h21/cpu_region_protect.c | 16 + .../port/esp32h21/esp_clk_tree.c | 46 + .../port/esp32h21/esp_cpu_intr.c | 24 + .../port/esp32h21/include/soc/rtc.h | 487 ++++ .../esp_hw_support/port/esp32h21/io_mux.c | 8 + .../esp_hw_support/port/esp32h21/rtc_clk.c | 458 ++++ .../port/esp32h21/rtc_clk_init.c | 86 + .../esp_hw_support/port/esp32h21/rtc_time.c | 292 +++ .../esp_hw_support/port/esp32h21/systimer.c | 21 + .../esp_mm/port/esp32h21/ext_mem_layout.c | 26 + components/esp_pm/pm_impl.c | 2 + .../esp32h2/include/esp32h2/rom/gpio.h | 2 +- .../esp32h21/include/esp32h21/rom/rtc.h | 18 +- .../esp_rom/esp32h21/ld/esp32h21.rom.ld | 5 +- .../esp_rom/esp32h21/ld/esp32h21.rom.libc.ld | 112 + .../esp_rom/patches/esp_rom_regi2c_esp32h21.c | 187 ++ components/esp_security/src/esp32h21/.gitkeep | 0 .../src/esp32h21/esp_crypto_clk.h | 16 + components/esp_system/crosscore_int.c | 4 + components/esp_system/fpga_overrides_clk.c | 5 +- components/esp_system/int_wdt.c | 5 + .../port/soc/esp32h21/cache_err_int.c | 10 +- components/esp_system/port/soc/esp32h21/clk.c | 1 - .../port/soc/esp32h21/system_internal.c | 11 - .../task_wdt/task_wdt_impl_timergroup.c | 5 +- .../hal/esp32h21/include/hal/clk_tree_ll.h | 4 +- .../include/hal/mspi_timing_tuning_ll.h | 7 + .../esp32h21/include/hal/spimem_flash_ll.h | 30 +- components/heap/port/esp32h21/memory_layout.c | 103 + .../esp32h21/include/soc/Kconfig.soc_caps.in | 8 - .../soc/esp32h21/include/soc/clk_tree_defs.h | 17 - components/soc/esp32h21/include/soc/soc.h | 3 +- .../soc/esp32h21/include/soc/soc_caps.h | 4 +- .../soc/esp32h21/include/soc/spi_pins.h | 24 +- .../soc/esp32h21/register/soc/gpio_struct.h | 2182 +---------------- .../spi_flash/esp32h21/Kconfig.flash_freq | 10 + .../spi_flash/esp32h21/Kconfig.soc_caps.in | 8 + .../spi_flash/esp32h21/flash_vendor_caps.h | 8 + examples/get-started/.build-test-rules.yml | 2 +- examples/get-started/hello_world/README.md | 4 +- tools/ci/build_template_app.sh | 4 +- tools/test_apps/system/.build-test-rules.yml | 2 +- .../test_apps/system/g0_components/README.md | 4 +- 63 files changed, 3087 insertions(+), 2289 deletions(-) create mode 100644 components/bootloader/subproject/main/ld/esp32h21/bootloader.ld create mode 100644 components/bootloader/subproject/main/ld/esp32h21/bootloader.rom.ld create mode 100644 components/bootloader_support/src/esp32h21/bootloader_esp32h21.c create mode 100644 components/bootloader_support/src/esp32h21/bootloader_sha.c create mode 100644 components/bootloader_support/src/esp32h21/bootloader_soc.c create mode 100644 components/bootloader_support/src/esp32h21/flash_encryption_secure_features.c create mode 100644 components/bootloader_support/src/esp32h21/secure_boot_secure_features.c create mode 100644 components/esp_hw_support/port/esp32h21/Kconfig.hw_support create mode 100644 components/esp_hw_support/port/esp32h21/Kconfig.rtc create mode 100644 components/esp_hw_support/port/esp32h21/chip_info.c create mode 100644 components/esp_hw_support/port/esp32h21/rtc_clk.c create mode 100644 components/esp_hw_support/port/esp32h21/rtc_clk_init.c create mode 100644 components/esp_hw_support/port/esp32h21/rtc_time.c create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.libc.ld delete mode 100644 components/esp_security/src/esp32h21/.gitkeep create mode 100644 components/esp_security/src/esp32h21/esp_crypto_clk.h create mode 100644 components/hal/esp32h21/include/hal/mspi_timing_tuning_ll.h create mode 100644 components/spi_flash/esp32h21/Kconfig.flash_freq create mode 100644 components/spi_flash/esp32h21/Kconfig.soc_caps.in create mode 100644 components/spi_flash/esp32h21/flash_vendor_caps.h diff --git a/.gitlab/ci/default-build-test-rules.yml b/.gitlab/ci/default-build-test-rules.yml index ade558ffe4..6edd831404 100644 --- a/.gitlab/ci/default-build-test-rules.yml +++ b/.gitlab/ci/default-build-test-rules.yml @@ -11,6 +11,7 @@ extra_default_build_targets: - esp32c61 bypass_check_test_targets: + - esp32h21 # # These lines would diff --git a/components/bootloader/subproject/main/ld/esp32h21/bootloader.ld b/components/bootloader/subproject/main/ld/esp32h21/bootloader.ld new file mode 100644 index 0000000000..c2e755175e --- /dev/null +++ b/components/bootloader/subproject/main/ld/esp32h21/bootloader.ld @@ -0,0 +1,308 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/** Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + * + * ESP32-H21 ROM static data usage is as follows: + * - 0x4083ba78 - 0x4084d380: Shared buffers, used in UART/USB/SPI download mode only + * - 0x4084d380 - 0x4084f380: PRO CPU stack, can be reclaimed as heap after RTOS startup + * - 0x4084f380 - 0x4084fee0: ROM .bss and .data used in startup code or nonos/early boot (can be freed when IDF runs) + * - 0x4084fee0 - 0x40850000: ROM .bss and .data used in startup code and when IDF runs (cannot be freed) + * + * The 2nd stage bootloader can take space up to the end of ROM shared + * buffers area (0x4084d380). + */ + +/* We consider 0x3fcdc710 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg, + * and work out iram_seg and iram_loader_seg addresses from there, backwards. + */ + +/* These lengths can be adjusted, if necessary: */ +bootloader_usable_dram_end = 0x40849a78; +bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */ +bootloader_dram_seg_len = 0x5000; +bootloader_iram_loader_seg_len = 0x7000; +bootloader_iram_seg_len = 0x2500; + +/* Start of the lower region is determined by region size and the end of the higher region */ +bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead; +bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len; +bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len; +bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len; + +MEMORY +{ + iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len + iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len + dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len +} + +/* The app may use RAM for static allocations up to the start of iram_loader_seg. + * If you have changed something above and this assert fails: + * 1. Check what the new value of bootloader_iram_loader_seg start is. + * 2. Update the value in this assert. + * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32h21/memory.ld.in to the same value. + */ +ASSERT(bootloader_iram_loader_seg_start == 0x4083ba78, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END"); + +/* Default entry point: */ +ENTRY(call_start_cpu0); + +SECTIONS +{ + + .iram_loader.text : + { + . = ALIGN (16); + _loader_text_start = ABSOLUTE(.); + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ + *liblog.a:(.literal .text .literal.* .text.*) + /* we use either libgcc or compiler-rt, so put similar entries for them here */ + *libgcc.a:(.literal .text .literal.* .text.*) + *libclang_rt.builtins.a:(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) + *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) + *libspi_flash.a:*.*(.literal .text .literal.* .text.*) + *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libhal.a:cache_hal.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) + *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) + *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) + *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libefuse.a:*.*(.literal .text .literal.* .text.*) + *(.fini.literal) + *(.fini) + *(.gnu.version) + _loader_text_end = ABSOLUTE(.); + } > iram_loader_seg + + .iram.text : + { + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + } > iram_seg + + + /* Shared RAM */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _dram_start = ABSOLUTE(.); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } > dram_seg + + .dram0.bootdesc : ALIGN(0x10) + { + _data_start = ABSOLUTE(.); + *(.data_bootloader_desc .data_bootloader_desc.*) /* Should be the first. Bootloader version info. DO NOT PUT ANYTHING BEFORE IT! */ + } > dram_seg + + .dram0.data : + { + *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */ + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + _data_end = ABSOLUTE(.); + } > dram_seg + + .dram0.rodata : + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + *(.sdata2 .sdata2.* .srodata .srodata.*) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + *(.eh_frame_hdr) + *(.eh_frame) + . = (. + 3) & ~ 3; + /* C++ constructor and destructor tables, properly ordered: */ + __init_array_start = ABSOLUTE(.); + KEEP (*crtbegin.*(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __init_array_end = ABSOLUTE(.); + KEEP (*crtbegin.*(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _dram_end = ABSOLUTE(.); + } > dram_seg + + .iram.text : + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.iram .iram.*) /* catch stray IRAM_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /** CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _etext = .; + } > iram_seg + + .riscv.attributes 0: { *(.riscv.attributes) } + + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_pubtypes 0 : { *(.debug_pubtypes) } + /* DWARF 3 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* GNU DWARF 2 extensions */ + .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) } + .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) } + /* DWARF 4 */ + .debug_types 0 : { *(.debug_types) } + /* DWARF 5 */ + .debug_addr 0 : { *(.debug_addr) } + .debug_line_str 0 : { *(.debug_line_str) } + .debug_loclists 0 : { *(.debug_loclists) } + .debug_macro 0 : { *(.debug_macro) } + .debug_names 0 : { *(.debug_names) } + .debug_rnglists 0 : { *(.debug_rnglists) } + .debug_str_offsets 0 : { *(.debug_str_offsets) } + + .comment 0 : { *(.comment) } + .note.GNU-stack 0: { *(.note.GNU-stack) } + + /** + * Discarding .rela.* sections results in the following mapping: + * .rela.text.* -> .text.* + * .rela.data.* -> .data.* + * And so forth... + */ + /DISCARD/ : { *(.rela.*) } + +} + +/** + * Appendix: Memory Usage of ROM bootloader + * + * 0x4083ba78 ------------------> _dram0_0_start + * | | + * | | + * | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h + * | | + * | | + * 0x4084d380 ------------------> __stack_sentry + * | | + * | | 2. Startup pro cpu stack (freed when IDF app is running) + * | | + * 0x4084f380 ------------------> __stack (pro cpu) + * | | + * | | + * | | 3. Shared memory only used in startup code or nonos/early boot* + * | | (can be freed when IDF runs) + * | | + * | | + * 0x4084fee0 ------------------> _dram0_rtos_reserved_start + * | | + * | | + * | | 4. Shared memory used in startup code and when IDF runs + * | | + * | | + * 0x4084ffc0 ------------------> _dram0_rtos_reserved_end + * | | + * 0x4084ffc8 ------------------> _data_start_interface + * | | + * | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible) + * | | + * 0x40850000 ------------------> _data_end_interface + */ diff --git a/components/bootloader/subproject/main/ld/esp32h21/bootloader.rom.ld b/components/bootloader/subproject/main/ld/esp32h21/bootloader.rom.ld new file mode 100644 index 0000000000..26b801f3f7 --- /dev/null +++ b/components/bootloader/subproject/main/ld/esp32h21/bootloader.rom.ld @@ -0,0 +1,6 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* No definition for ESP32-H21 target */ diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c index e69de29bb2..4c2fb160d8 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c @@ -0,0 +1,286 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "string.h" +#include "sdkconfig.h" +#include "esp_err.h" +#include "esp_log.h" +#include "esp_rom_gpio.h" +#include "flash_qio_mode.h" +#include "bootloader_flash_config.h" +#include "bootloader_flash_priv.h" +#include "bootloader_init.h" +#include "hal/mmu_hal.h" +#include "hal/cache_hal.h" +#include "hal/cache_ll.h" +#include "soc/pcr_reg.h" + +static const char *TAG = "boot.esp32h21"; + +void bootloader_flash_update_id() +{ + esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip; + chip->device_id = bootloader_read_flash_id(); +} + +void bootloader_flash_update_size(uint32_t size) +{ + rom_spiflash_legacy_data->chip.chip_size = size; +} + +void IRAM_ATTR bootloader_flash_cs_timing_config() +{ + SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); +} + +void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) +{ + uint32_t spi_clk_div = 0; + switch (pfhdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_DIV_1: + spi_clk_div = 1; + break; + case ESP_IMAGE_SPI_SPEED_DIV_2: + spi_clk_div = 2; + break; + case ESP_IMAGE_SPI_SPEED_DIV_3: + spi_clk_div = 3; + break; + case ESP_IMAGE_SPI_SPEED_DIV_4: + spi_clk_div = 4; + break; + default: + break; + } + esp_rom_spiflash_config_clk(spi_clk_div, 0); +} + +void IRAM_ATTR bootloader_configure_spi_pins(int drv) +{ + uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK; + uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO; + uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI; + uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0; + uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD; + uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP; + esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); + esp_rom_gpio_pad_set_drv(q_gpio_num, drv); + esp_rom_gpio_pad_set_drv(d_gpio_num, drv); + esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); + esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); + esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); +} + +static void IRAM_ATTR bootloader_flash_clock_init(void) +{ + // At this moment, BBPLL should be enabled, safe to switch MSPI clock source to PLL_F64M (default clock src) to raise speed + REG_SET_FIELD(PCR_MSPI_CONF_REG, PCR_MSPI_CLK_SEL, 2); +} + +static void update_flash_config(const esp_image_header_t *bootloader_hdr) +{ + uint32_t size; + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + size = 1; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + size = 2; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + size = 4; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + size = 8; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + size = 16; + break; + default: + size = 2; + } + // Set flash chip size + esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode +} + +static void print_flash_info(const esp_image_header_t *bootloader_hdr) +{ + ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic); + ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); + ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); + ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); + ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); + + const char *str; + switch (bootloader_hdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_DIV_2: + str = "32MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_3: + str = "21.3MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_4: + str = "16MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_1: + str = "64MHz"; + break; + default: + str = "16MHz"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str); + + /* SPI mode could have been set to QIO during boot already, + so test the SPI registers not the flash header */ + esp_rom_spiflash_read_mode_t spi_mode = bootloader_flash_get_spi_mode(); + switch (spi_mode) { + case ESP_ROM_SPIFLASH_QIO_MODE: + str = "QIO"; + break; + case ESP_ROM_SPIFLASH_QOUT_MODE: + str = "QOUT"; + break; + case ESP_ROM_SPIFLASH_DIO_MODE: + str = "DIO"; + break; + case ESP_ROM_SPIFLASH_DOUT_MODE: + str = "DOUT"; + break; + case ESP_ROM_SPIFLASH_FASTRD_MODE: + str = "FAST READ"; + break; + default: + str = "SLOW READ"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str); + + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + str = "1MB"; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + str = "2MB"; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + str = "4MB"; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + str = "8MB"; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + str = "16MB"; + break; + default: + str = "2MB"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str); +} + +static void IRAM_ATTR bootloader_init_flash_configure(void) +{ + bootloader_flash_clock_init(); + bootloader_configure_spi_pins(1); + bootloader_flash_cs_timing_config(); +} + +static void bootloader_spi_flash_resume(void) +{ + bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); + esp_rom_spiflash_wait_idle(&g_rom_flashchip); +} + +esp_err_t bootloader_init_spi_flash(void) +{ + bootloader_init_flash_configure(); + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + +#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + bootloader_enable_qio_mode(); +#endif + + print_flash_info(&bootloader_image_hdr); + + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); + update_flash_config(&bootloader_image_hdr); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); + + //ensure the flash is write-protected + bootloader_enable_wp(); + return ESP_OK; +} + +#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr) +{ + esp_rom_spiflash_read_mode_t mode; + switch(pfhdr->spi_mode) { + case ESP_IMAGE_SPI_MODE_QIO: + mode = ESP_ROM_SPIFLASH_QIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_QOUT: + mode = ESP_ROM_SPIFLASH_QOUT_MODE; + break; + case ESP_IMAGE_SPI_MODE_DIO: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + break; + case ESP_IMAGE_SPI_MODE_FAST_READ: + mode = ESP_ROM_SPIFLASH_FASTRD_MODE; + break; + case ESP_IMAGE_SPI_MODE_SLOW_READ: + mode = ESP_ROM_SPIFLASH_SLOWRD_MODE; + break; + default: + mode = ESP_ROM_SPIFLASH_DIO_MODE; + } + esp_rom_spiflash_config_readmode(mode); +} + +void bootloader_flash_hardware_init(void) +{ + esp_rom_spiflash_attach(0, false); + + //init cache hal + cache_hal_init(); + //init mmu + mmu_hal_init(); + // update flash ID + bootloader_flash_update_id(); + // Check and run XMC startup flow + esp_err_t ret = bootloader_flash_xmc_startup(); + assert(ret == ESP_OK); + + /* Alternative of bootloader_init_spi_flash */ + // RAM app doesn't have headers in the flash. Make a default one for it. + esp_image_header_t WORD_ALIGNED_ATTR hdr = { + .spi_mode = ESP_IMAGE_SPI_MODE_DIO, + .spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2, + .spi_size = ESP_IMAGE_FLASH_SIZE_2MB, + }; + + bootloader_configure_spi_pins(1); + bootloader_flash_set_spi_mode(&hdr); + bootloader_flash_clock_config(&hdr); + bootloader_flash_clock_init(); + bootloader_flash_cs_timing_config(); + + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + + cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); + update_flash_config(&hdr); + cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); + + //ensure the flash is write-protected + bootloader_enable_wp(); +} +#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c index e5e258a44e..73a9845e5a 100644 --- a/components/bootloader_support/src/bootloader_clock_init.c +++ b/components/bootloader_support/src/bootloader_clock_init.c @@ -9,7 +9,7 @@ #include "soc/chip_revision.h" #include "hal/efuse_hal.h" -#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5 &&! CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-5645 +#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5 &&! CONFIG_IDF_TARGET_ESP32C61 &&! CONFIG_IDF_TARGET_ESP32H21 // TODO: IDF-5645 #include "soc/rtc_cntl_reg.h" #else #include "soc/lp_wdt_reg.h" @@ -123,6 +123,19 @@ __attribute__((weak)) void bootloader_clock_configure(void) SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */ SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); /* SLP_REJECT */ SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_SLEEP_REJECT_INT_CLR); /* SLP_WAKEUP */ +#elif CONFIG_IDF_TARGET_ESP32H21 + // CLR ENA + CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */ + CLEAR_PERI_REG_MASK(LP_ANA_LP_INT_ENA_REG, LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */ + CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */ + CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */ + CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */ + // SET CLR + SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */ + SET_PERI_REG_MASK(LP_ANA_LP_INT_CLR_REG, LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */ + SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */ + SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); /* SLP_REJECT */ + SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_SLEEP_REJECT_INT_CLR); #elif CONFIG_IDF_TARGET_ESP32P4 // CLR ENA CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */ diff --git a/components/bootloader_support/src/bootloader_efuse.c b/components/bootloader_support/src/bootloader_efuse.c index 8d5fadede3..f3a51b6b3f 100644 --- a/components/bootloader_support/src/bootloader_efuse.c +++ b/components/bootloader_support/src/bootloader_efuse.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,6 +18,7 @@ IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void) int bootloader_clock_get_rated_freq_mhz(void) { + //TODO: IDF-6570, need refactor #ifdef CONFIG_IDF_TARGET_ESP32 return efuse_hal_get_rated_freq_mhz(); @@ -40,6 +41,10 @@ int bootloader_clock_get_rated_freq_mhz(void) //IDF-6570 return 96; +#elif CONFIG_IDF_TARGET_ESP32H21 + //TODO: [ESP32H21] IDF-11556, please check + return 96; + #elif CONFIG_IDF_TARGET_ESP32P4 return 400; diff --git a/components/bootloader_support/src/esp32h21/bootloader_esp32h21.c b/components/bootloader_support/src/esp32h21/bootloader_esp32h21.c new file mode 100644 index 0000000000..6745eb4a0d --- /dev/null +++ b/components/bootloader_support/src/esp32h21/bootloader_esp32h21.c @@ -0,0 +1,173 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include "sdkconfig.h" +#include "esp_attr.h" +#include "esp_log.h" +#include "esp_image_format.h" +#include "flash_qio_mode.h" +#include "esp_rom_gpio.h" +#include "esp_rom_uart.h" +#include "esp_rom_sys.h" +#include "esp_rom_spiflash.h" +#include "soc/gpio_sig_map.h" +#include "soc/io_mux_reg.h" +#include "soc/assist_debug_reg.h" +#include "esp_cpu.h" +#include "soc/rtc.h" +#include "soc/spi_periph.h" +#include "soc/cache_reg.h" +#include "soc/io_mux_reg.h" +#include "soc/pcr_reg.h" +#include "rom/ets_sys.h" +#include "bootloader_common.h" +#include "bootloader_init.h" +#include "bootloader_clock.h" +#include "bootloader_flash_config.h" +#include "bootloader_mem.h" +#include "esp_private/regi2c_ctrl.h" +#include "soc/regi2c_lp_bias.h" +#include "soc/regi2c_bias.h" +#include "bootloader_console.h" +#include "bootloader_flash_priv.h" +#include "bootloader_soc.h" +#include "esp_private/bootloader_flash_internal.h" +#include "esp_efuse.h" +#include "hal/mmu_hal.h" +#include "hal/cache_hal.h" +#include "hal/lpwdt_ll.h" +#include "soc/lp_wdt_reg.h" +#include "soc/pmu_reg.h" +#include "hal/efuse_hal.h" +#include "hal/regi2c_ctrl_ll.h" + +static const char *TAG = "boot.esp32h21"; + +static void wdt_reset_cpu0_info_enable(void) +{ + REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN); + REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN); + REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN); +} + +static void wdt_reset_info_dump(int cpu) +{ + (void) cpu; + // saved PC was already printed by the ROM bootloader. + // nothing to do here. +} + +static void bootloader_check_wdt_reset(void) +{ + int wdt_rst = 0; + soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); + if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 || + rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) { + ESP_EARLY_LOGW(TAG, "PRO CPU has been reset by WDT."); + wdt_rst = 1; + } + if (wdt_rst) { + // if reset by WDT dump info from trace port + wdt_reset_info_dump(0); + } + wdt_reset_cpu0_info_enable(); +} + +static void bootloader_super_wdt_auto_feed(void) +{ + REG_WRITE(LP_WDT_SWD_WPROTECT_REG, LP_WDT_SWD_WKEY_VALUE); + REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN); + REG_WRITE(LP_WDT_SWD_WPROTECT_REG, 0); +} + +static inline void bootloader_hardware_init(void) +{ + /* Disable RF pll by default */ + CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL); + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL); + + //TODO: [ESP32H21] IDF-11550, regi2c atomic clock + regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader + regi2c_ctrl_ll_master_configure_clock(); +} + +static inline void bootloader_ana_reset_config(void) +{ + //Enable super WDT reset. + bootloader_ana_super_wdt_reset_config(true); + //Enable BOD reset (mode1) + //TODO: [ESP32H21] IDF-11530 + // brownout_ll_ana_reset_enable(true); +} + +esp_err_t bootloader_init(void) +{ + esp_err_t ret = ESP_OK; + + bootloader_hardware_init(); + bootloader_ana_reset_config(); + bootloader_super_wdt_auto_feed(); + +// In RAM_APP, memory will be initialized in `call_start_cpu0` +#if !CONFIG_APP_BUILD_TYPE_RAM + // protect memory region + bootloader_init_mem(); + /* check that static RAM is after the stack */ + assert(&_bss_start <= &_bss_end); + assert(&_data_start <= &_data_end); + // clear bss section + bootloader_clear_bss_section(); +#endif // !CONFIG_APP_BUILD_TYPE_RAM + + // init eFuse virtual mode (read eFuses to RAM) +#ifdef CONFIG_EFUSE_VIRTUAL + ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); +#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH + esp_efuse_init_virtual_mode_in_ram(); +#endif +#endif + // config clock + bootloader_clock_configure(); + // initialize console, from now on, we can use esp_log + bootloader_console_init(); + /* print 2nd bootloader banner */ + bootloader_print_banner(); + +#if !CONFIG_APP_BUILD_TYPE_RAM + //init cache hal + cache_hal_init(); + //init mmu + mmu_hal_init(); + // update flash ID + bootloader_flash_update_id(); + // Check and run XMC startup flow + if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) { + ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); + return ret; + } + // read bootloader header + if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { + return ret; + } + // read chip revision and check if it's compatible to bootloader + if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { + return ret; + } + // initialize spi flash + if ((ret = bootloader_init_spi_flash()) != ESP_OK) { + return ret; + } +#endif // !CONFIG_APP_BUILD_TYPE_RAM + + // check whether a WDT reset happened + bootloader_check_wdt_reset(); + // config WDT + bootloader_config_wdt(); + // enable RNG early entropy source + bootloader_enable_random(); + + return ret; +} diff --git a/components/bootloader_support/src/esp32h21/bootloader_sha.c b/components/bootloader_support/src/esp32h21/bootloader_sha.c new file mode 100644 index 0000000000..75b2df88ef --- /dev/null +++ b/components/bootloader_support/src/esp32h21/bootloader_sha.c @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "bootloader_sha.h" +#include +#include +#include +#include + +#include "rom/sha.h" + +//TODO: [ESP32H21] IDF-11501 + +static SHA_CTX ctx; + +bootloader_sha256_handle_t bootloader_sha256_start() +{ + // Enable SHA hardware + ets_sha_enable(); + ets_sha_init(&ctx, SHA2_256); + return &ctx; // Meaningless non-NULL value +} + +void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len) +{ + assert(handle != NULL); + /* H21 secure boot key field consists of 1 byte of curve identifier and 64 bytes of ECDSA public key. + * While verifying the signature block, we need to calculate the SHA of this key field which is of 65 bytes. + * ets_sha_update handles it cleanly so we can safely remove the check: + * assert(data_len % 4) == 0 + */ + ets_sha_update(&ctx, data, data_len, false); +} + +void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest) +{ + assert(handle != NULL); + + if (digest == NULL) { + bzero(&ctx, sizeof(ctx)); + return; + } + ets_sha_finish(&ctx, digest); +} diff --git a/components/bootloader_support/src/esp32h21/bootloader_soc.c b/components/bootloader_support/src/esp32h21/bootloader_soc.c new file mode 100644 index 0000000000..094e25d02f --- /dev/null +++ b/components/bootloader_support/src/esp32h21/bootloader_soc.c @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include "soc/lp_analog_peri_reg.h" + +void bootloader_ana_super_wdt_reset_config(bool enable) +{ + //H21 doesn't support bypass super WDT reset + assert(enable); + REG_CLR_BIT(LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST); +} + +//TODO: [ESP32H21] IDF-11534, there is a `bootloader_ana_bod_reset_config` in verify code, please check +void bootloader_ana_bod_reset_config(bool enable) +{ + REG_CLR_BIT(LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST); + + if (enable) { + REG_SET_BIT(LP_ANA_BOD_MODE1_CNTL_REG, LP_ANA_BOD_MODE1_RESET_ENA); + } else { + REG_CLR_BIT(LP_ANA_BOD_MODE1_CNTL_REG, LP_ANA_BOD_MODE1_RESET_ENA); + } +} + +//Not supported but common bootloader calls the function. Do nothing +void bootloader_ana_clock_glitch_reset_config(bool enable) +{ + (void)enable; +} diff --git a/components/bootloader_support/src/esp32h21/flash_encryption_secure_features.c b/components/bootloader_support/src/esp32h21/flash_encryption_secure_features.c new file mode 100644 index 0000000000..adc1115a5c --- /dev/null +++ b/components/bootloader_support/src/esp32h21/flash_encryption_secure_features.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_flash_encrypt.h" +#include "esp_secure_boot.h" +#include "esp_efuse.h" +#include "esp_efuse_table.h" +#include "esp_log.h" +#include "sdkconfig.h" + +static __attribute__((unused)) const char *TAG = "flash_encrypt"; + +esp_err_t esp_flash_encryption_enable_secure_features(void) +{ + //TODO: [ESP32H21] IDF-11499 + abort(); + return ESP_OK; +} diff --git a/components/bootloader_support/src/esp32h21/secure_boot_secure_features.c b/components/bootloader_support/src/esp32h21/secure_boot_secure_features.c new file mode 100644 index 0000000000..6c4db9ea16 --- /dev/null +++ b/components/bootloader_support/src/esp32h21/secure_boot_secure_features.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_flash_encrypt.h" +#include "esp_secure_boot.h" +#include "esp_efuse.h" +#include "esp_efuse_table.h" +#include "esp_log.h" +#include "sdkconfig.h" + +static __attribute__((unused)) const char *TAG = "secure_boot"; + +esp_err_t esp_secure_boot_enable_secure_features(void) +{ + //TODO: [ESP32H21] IDF-11500 + abort(); + return ESP_OK; +} diff --git a/components/efuse/esp32h21/esp_efuse_rtc_calib.c b/components/efuse/esp32h21/esp_efuse_rtc_calib.c index 69830ec0f5..cbc135cbbb 100644 --- a/components/efuse/esp32h21/esp_efuse_rtc_calib.c +++ b/components/efuse/esp32h21/esp_efuse_rtc_calib.c @@ -24,18 +24,21 @@ int esp_efuse_rtc_calib_get_ver(void) uint32_t cali_version = 0; // TODO: [ESP32H21] IDF-11590 abort(); + return cali_version; } uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten) { // TODO: [ESP32H21] IDF-11590 abort(); + return 0; } int esp_efuse_rtc_calib_get_chan_compens(int version, uint32_t adc_unit, uint32_t adc_channel, int atten) { // TODO: [ESP32H21] IDF-11590 abort(); + return ESP_OK; } esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, int atten, uint32_t* out_digi, uint32_t* out_vol_mv) diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index eb8bac60c8..bcf512ca14 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -584,10 +584,12 @@ esp_err_t gpio_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, { GPIO_CHECK(fn, "GPIO ISR null", ESP_ERR_INVALID_ARG); gpio_isr_alloc_t p; -#if !CONFIG_IDF_TARGET_ESP32P4 //TODO: IDF-7995 - p.source = ETS_GPIO_INTR_SOURCE; -#else +#if CONFIG_IDF_TARGET_ESP32P4 //TODO: IDF-7995 p.source = ETS_GPIO_INTR0_SOURCE; +#elif CONFIG_IDF_TARGET_ESP32H21 // TODO: IDF-11611 + p.source = ETS_GPIO_INTERRUPT_PRO_SOURCE; +#else + p.source = ETS_GPIO_INTR_SOURCE; #endif p.intr_alloc_flags = intr_alloc_flags; #if SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index d2e21591a4..b72ee7a7c4 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -42,9 +42,10 @@ if(NOT non_os_build) "port/esp_clk_tree_common.c" "dma/esp_dma_utils.c" "dma/gdma_link.c" - "spi_share_hw_ctrl.c" "spi_bus_lock.c") - + if(CONFIG_SOC_GPSPI_SUPPORTED) + list(APPEND srcs "spi_share_hw_ctrl.c") + endif() if(CONFIG_SOC_ADC_SUPPORTED) list(APPEND srcs "adc_share_hw_ctrl.c") endif() @@ -157,6 +158,12 @@ set(public_include_dirs "include" "include/soc" "include/soc/${target}" "dma/include" "ldo/include" "debug_probe/include" "mspi_timing_tuning/include") +if(CONFIG_IDF_TARGET_ESP32H21) + list(REMOVE_ITEM srcs + "sleep_modes.c" # TODO: [ESP32H21] IDF-11515, IDF-11517 + ) +endif() + idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${public_include_dirs} PRIV_INCLUDE_DIRS port/include include/esp_private diff --git a/components/esp_hw_support/include/esp_private/sleep_event.h b/components/esp_hw_support/include/esp_private/sleep_event.h index 5e8a3f9aec..67fc69764a 100644 --- a/components/esp_hw_support/include/esp_private/sleep_event.h +++ b/components/esp_hw_support/include/esp_private/sleep_event.h @@ -28,7 +28,7 @@ typedef enum { SLEEP_EVENT_HW_GOTO_SLEEP, // Hardware is about to power off SLEEP_EVENT_SW_CPU_TO_MEM_START, // CPU registers are starting to be saved SLEEP_EVENT_SW_CPU_TO_MEM_END, // CPU registers have finished saving -#if CONFIG_IDF_TARGET_ESP32H2 +#if CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21 SLEEP_EVENT_HW_FLASH_BBPLL_EN_START, // Beginning of rtc_clk_bbpll_enable when using FLASH_PLL SLEEP_EVENT_HW_FLASH_BBPLL_EN_STOP, // End of rtc_clk_bbpll_enable when using FLASH_PLL #endif diff --git a/components/esp_hw_support/include/soc/esp32h21/rtc.h b/components/esp_hw_support/include/soc/esp32h21/rtc.h index e69de29bb2..8c0090b81e 100644 --- a/components/esp_hw_support/include/soc/esp32h21/rtc.h +++ b/components/esp_hw_support/include/soc/esp32h21/rtc.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file esp32h21/rtc.h + * + * This file contains declarations of rtc related functions. + */ + +/** + * @brief Get current value of RTC counter in microseconds + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter in microseconds + */ +uint64_t esp_rtc_get_time_us(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/port/esp32h21/CMakeLists.txt b/components/esp_hw_support/port/esp32h21/CMakeLists.txt index 59051829f8..922e3c6461 100644 --- a/components/esp_hw_support/port/esp32h21/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32h21/CMakeLists.txt @@ -1 +1,15 @@ -target_include_directories(${COMPONENT_LIB} PUBLIC . include) +set(srcs "rtc_clk.c" + "rtc_time.c" + "chip_info.c" + ) +if(CONFIG_SOC_PMU_SUPPORTED) + list(APPEND srcs "rtc_clk_init.c" + "pmu_param.c" + "pmu_init.c" + ) +endif() + +add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") + +target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") +target_include_directories(${COMPONENT_LIB} PUBLIC . include private_include) diff --git a/components/esp_hw_support/port/esp32h21/Kconfig.hw_support b/components/esp_hw_support/port/esp32h21/Kconfig.hw_support new file mode 100644 index 0000000000..67fa096c88 --- /dev/null +++ b/components/esp_hw_support/port/esp32h21/Kconfig.hw_support @@ -0,0 +1,58 @@ +choice ESP32H21_REV_MIN + prompt "Minimum Supported ESP32-H21 Revision" + default ESP32H21_REV_MIN_0 + help + Required minimum chip revision. ESP-IDF will check for it and + reject to boot if the chip revision fails the check. + This ensures the chip used will have some modifications (features, or bugfixes). + + The complied binary will only support chips above this revision, + this will also help to reduce binary size. + + config ESP32H21_REV_MIN_0 + bool "Rev v0.0" +endchoice + +config ESP32H21_REV_MIN_FULL + int + default 0 if ESP32H21_REV_MIN_0 + +config ESP_REV_MIN_FULL + int + default ESP32H21_REV_MIN_FULL + + # + # MAX Revision + # + + comment "Maximum Supported ESP32-H21 Revision (Rev v0.99)" + # Maximum revision that IDF supports. + # It can not be changed by user. + # Only Espressif can change it when a new version will be supported in IDF. + # Supports all chips starting from ESP32H21_REV_MIN_FULL to ESP32H21_REV_MAX_FULL + +config ESP32H21_REV_MAX_FULL + int + default 99 + # keep in sync the "Maximum Supported Revision" description with this value + +config ESP_REV_MAX_FULL + int + default ESP32H21_REV_MAX_FULL + +config ESP_EFUSE_BLOCK_REV_MIN_FULL + int "Minimum Supported ESP32-H21 eFuse Block Revision" + default 0 + help + Required minimum eFuse Block revision. ESP-IDF will check it at the 2nd bootloader stage + whether the current image can work correctly for this eFuse Block revision. + So that to avoid running an incompatible image on a SoC that contains breaking change in the eFuse Block. + If you want to update this value to run the image that not compatible with the current eFuse Block revision, + please contact to Espressif's business team for details: + https://www.espressif.com.cn/en/contact-us/sales-questions + +config ESP_EFUSE_BLOCK_REV_MAX_FULL + int + default 99 + comment "Maximum Supported ESP32-H21 eFuse Block Revision (eFuse Block Rev v0.99)" + # The revision in the comment must correspond to the default value of ESP_EFUSE_BLOCK_REV_MAX_FULL diff --git a/components/esp_hw_support/port/esp32h21/Kconfig.rtc b/components/esp_hw_support/port/esp32h21/Kconfig.rtc new file mode 100644 index 0000000000..b02d6e6cc0 --- /dev/null +++ b/components/esp_hw_support/port/esp32h21/Kconfig.rtc @@ -0,0 +1,39 @@ +choice RTC_CLK_SRC + prompt "RTC clock source" + default RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + config RTC_CLK_SRC_INT_RC + bool "Internal 136 kHz RC oscillator" + config RTC_CLK_SRC_EXT_CRYS + bool "External 32 kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + config RTC_CLK_SRC_EXT_OSC + bool "External 32 kHz oscillator at 32K_XP pin" + select ESP_SYSTEM_RTC_EXT_OSC + config RTC_CLK_SRC_INT_RC32K + bool "Internal 32 kHz RC oscillator" +endchoice + +config RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K + default 1024 if RTC_CLK_SRC_INT_RC + range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K + range 0 32766 if RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 136000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. diff --git a/components/esp_hw_support/port/esp32h21/chip_info.c b/components/esp_hw_support/port/esp32h21/chip_info.c new file mode 100644 index 0000000000..a296fa92a0 --- /dev/null +++ b/components/esp_hw_support/port/esp32h21/chip_info.c @@ -0,0 +1,18 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_chip_info.h" +#include "hal/efuse_hal.h" + +void esp_chip_info(esp_chip_info_t *out_info) +{ + memset(out_info, 0, sizeof(*out_info)); + out_info->model = CHIP_ESP32H21; + out_info->revision = efuse_hal_chip_revision(); + out_info->cores = 1; + out_info->features = CHIP_FEATURE_IEEE802154 | CHIP_FEATURE_BLE; +} diff --git a/components/esp_hw_support/port/esp32h21/cpu_region_protect.c b/components/esp_hw_support/port/esp32h21/cpu_region_protect.c index e69de29bb2..805873d714 100644 --- a/components/esp_hw_support/port/esp32h21/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32h21/cpu_region_protect.c @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdkconfig.h" +#include "soc/soc.h" +#include "esp_cpu.h" +#include "esp_fault.h" + +void esp_cpu_configure_region_protection(void) +{ + //TODO: [ESP32H21] IDF-11917 +} diff --git a/components/esp_hw_support/port/esp32h21/esp_clk_tree.c b/components/esp_hw_support/port/esp32h21/esp_clk_tree.c index e69de29bb2..56a5aa26ca 100644 --- a/components/esp_hw_support/port/esp32h21/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32h21/esp_clk_tree.c @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_clk_tree.h" +#include "esp_err.h" +#include "esp_check.h" +#include "soc/rtc.h" +#include "hal/clk_tree_hal.h" +#include "hal/clk_tree_ll.h" +#include "esp_private/esp_clk_tree_common.h" + +//TODO: [ESP32H21] IDF-11521 + +static const char *TAG = "esp_clk_tree"; + +esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision, +uint32_t *freq_value) +{ + ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src"); + ESP_RETURN_ON_FALSE(precision < ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision"); + ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer"); + + uint32_t clk_src_freq = 0; + switch (clk_src) { + case SOC_MOD_CLK_PLL_F48M: + clk_src_freq = CLK_LL_PLL_48M_FREQ_MHZ * MHZ; + break; + case SOC_MOD_CLK_PLL_F64M: + clk_src_freq = CLK_LL_PLL_64M_FREQ_MHZ * MHZ; + break; + case SOC_MOD_CLK_PLL_F96M: + clk_src_freq = CLK_LL_PLL_96M_FREQ_MHZ * MHZ; + break; + default: + break; + } + + ESP_RETURN_ON_FALSE(clk_src_freq, ESP_FAIL, TAG, + "freq shouldn't be 0, calibration failed"); + *freq_value = clk_src_freq; + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32h21/esp_cpu_intr.c b/components/esp_hw_support/port/esp32h21/esp_cpu_intr.c index e69de29bb2..79769f6018 100644 --- a/components/esp_hw_support/port/esp32h21/esp_cpu_intr.c +++ b/components/esp_hw_support/port/esp32h21/esp_cpu_intr.c @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On the ESP32-H21, interrupt: + * - 1 is for Wi-Fi + * - 6 for "permanently disabled interrupt" + * + * Interrupts 3, 4 and 7 are unavailable for PULP CPU as they are bound to Core-Local Interrupts (CLINT) + */ + //TODO: [ESP32H21] IDF-11537 + const uint32_t rsvd_mask = BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7); + + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask); +} diff --git a/components/esp_hw_support/port/esp32h21/include/soc/rtc.h b/components/esp_hw_support/port/esp32h21/include/soc/rtc.h index e69de29bb2..51f3514652 100644 --- a/components/esp_hw_support/port/esp32h21/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32h21/include/soc/rtc.h @@ -0,0 +1,487 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include +#include "soc/soc.h" +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************************************************************************/ +/***************** THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE *****************/ +/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/ +/************************************************************************************/ + +/** + * @file rtc.h + * @brief Low-level RTC power, clock functions. + * + * Functions in this file facilitate configuration of ESP32H21's RTC_CNTL peripheral. + * RTC_CNTL peripheral handles many functions: + * - enables/disables clocks and power to various parts of the chip; this is + * done using direct register access (forcing power up or power down) or by + * allowing state machines to control power and clocks automatically + * - handles sleep and wakeup functions + * - maintains a 48-bit counter which can be used for timekeeping + * + * These functions are not thread safe, and should not be viewed as high level + * APIs. For example, while this file provides a function which can switch + * CPU frequency, this function is on its own is not sufficient to implement + * frequency switching in ESP-IDF context: some coordination with RTOS, + * peripheral drivers, and WiFi/BT stacks is also required. + * + * These functions will normally not be used in applications directly. + * ESP-IDF provides, or will provide, drivers and other facilities to use + * RTC subsystem functionality. + * + * The functions are loosely split into the following groups: + * - rtc_clk: clock switching, calibration + * - rtc_time: reading RTC counter, conversion between counter values and time + * - rtc_sleep: entry into sleep modes + */ + +#define MHZ (1000000) + +#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) +#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value + +#define OTHER_BLOCKS_POWERUP 1 +#define OTHER_BLOCKS_WAIT 1 + +/* Delays for various clock sources to be enabled/switched. + * All values are in microseconds. + */ +#define SOC_DELAY_RTC_FAST_CLK_SWITCH 3 +#define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300 +#define SOC_DELAY_RC_FAST_ENABLE 50 +#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 +#define SOC_DELAY_RC32K_ENABLE 300 +#define SOC_DELAY_LP_PLL_SWITCH 3 +#define SOC_DELAY_LP_PLL_ENABLE 50 + +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 + +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 860 +#define RTC_CNTL_SCK_DCAP_DEFAULT 85 +#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700 + +/* Various delays to be programmed into power control state machines */ +#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) +#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) +#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) +#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) +#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) +#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) +#define RTC_CNTL_MIN_SLP_VAL_MIN (2) + +/* +set sleep_init default param +*/ +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_SLEEP_ON 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 +#define RTC_CNTL_PD_CUR_SLEEP_ON 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + +/* +The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value +storing in efuse (based on ATE 5k ECO3 chips) +*/ +#define K_RTC_MID_MUL10000 215 +#define K_DIG_MID_MUL10000 213 +#define V_RTC_MID_MUL10000 10800 +#define V_DIG_MID_MUL10000 10860 + +/** + * @brief CPU clock configuration structure + */ +typedef struct rtc_cpu_freq_config_s { + soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived + uint32_t source_freq_mhz; //!< Source clock frequency + uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div + uint32_t freq_mhz; //!< CPU clock frequency +} rtc_cpu_freq_config_t; + +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO +#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO + +/** + * @brief Clock source to be calibrated using rtc_clk_cal function + * + * @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL + * However, this is not true on ESP32H21. The conversion to register field values is explicitly done in + * rtc_clk_cal_internal + */ +typedef enum { + RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK + RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150kHz RC oscillator + RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock + RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock + RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpiox, as one type of 32k clock + RTC_CAL_RC_FAST //!< Internal 8MHz RC oscillator +} rtc_cal_sel_t; + +/** + * Initialization parameters for rtc_clk_init + */ +typedef struct { + soc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose + soc_rtc_slow_clk_src_t slow_clk_src : 3; //!< RTC_SLOW_CLK clock source to choose + uint32_t clk_rtc_clk_div : 8; + uint32_t clk_8m_clk_div : 3; //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 10; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency) + uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency) +} rtc_clk_config_t; + +/** + * Default initializer for rtc_clk_config_t + */ +#define RTC_CLK_CONFIG_DEFAULT() { \ + .xtal_freq = SOC_XTAL_FREQ_32M, \ + .cpu_freq_mhz = 96, \ + .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ + .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ + .clk_rtc_clk_div = 0, \ + .clk_8m_clk_div = 0, \ + .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ + .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ + .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \ +} + +/** + * Initialize clocks and set CPU frequency + * + * @param cfg clock configuration as rtc_clk_config_t + */ +void rtc_clk_init(rtc_clk_config_t cfg); + +/** + * @brief Get main XTAL frequency + * + * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to + * rtc_clk_init function + * + * @return XTAL frequency, one of soc_xtal_freq_t + */ +soc_xtal_freq_t rtc_clk_xtal_freq_get(void); + +/** + * @brief Update XTAL frequency + * + * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored + * after startup. + * + * @param xtal_freq New frequency value + */ +void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq); + +/** + * @brief Enable or disable 32 kHz XTAL oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_32k_enable(bool en); + +/** + * @brief Configure 32 kHz XTAL oscillator to accept external clock signal + */ +void rtc_clk_32k_enable_external(void); + +/** + * @brief Get the state of 32k XTAL oscillator + * @return true if 32k XTAL oscillator has been enabled + */ +bool rtc_clk_32k_enabled(void); + +/** + * @brief Enable 32k oscillator, configuring it for fast startup time. + * Note: to achieve higher frequency stability, rtc_clk_32k_enable function + * must be called one the 32k XTAL oscillator has started up. This function + * will initially disable the 32k XTAL oscillator, so it should not be called + * when the system is using 32k XTAL as RTC_SLOW_CLK. + * + * @param cycle Number of 32kHz cycles to bootstrap external crystal. + * If 0, no square wave will be used to bootstrap crystal oscillation. + */ +void rtc_clk_32k_bootstrap(uint32_t cycle); + +/** + * @brief Enable or disable 32 kHz internal rc oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_rc32k_enable(bool enable); + +/** + * @brief Enable or disable 8 MHz internal oscillator + * + * @param clk_8m_en true to enable 8MHz generator + */ +void rtc_clk_8m_enable(bool clk_8m_en); + +/** + * @brief Get the state of 8 MHz internal oscillator + * @return true if the oscillator is enabled + */ +bool rtc_clk_8m_enabled(void); + +/** + * @brief Enable or disable LP_PLL_CLK + * Note that to be able to use LP_PLL clock, besides turn on the power for LP_PLL, also needs to turn on the power for + * the LP_PLL clock source (either XTAL32K or RC32K). + * @param enable true to enable, false to disable + */ +void rtc_clk_lp_pll_enable(bool enable); + +/** + * @brief Select clock source for LP_PLL_CLK + * @param clk_src clock source (one of soc_lp_pll_clk_src_t values) + */ +void rtc_clk_lp_pll_src_set(soc_lp_pll_clk_src_t clk_src); + +/** + * @brief Select source for RTC_SLOW_CLK + * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values) + */ +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src); + +/** + * @brief Get the RTC_SLOW_CLK source + * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) + */ +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); + +/** + * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000 + * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768 + * + * rtc_clk_cal function can be used to get more precise value by comparing + * RTC_SLOW_CLK frequency to the frequency of main XTAL. + * + * @return RTC_SLOW_CLK frequency, in Hz + */ +uint32_t rtc_clk_slow_freq_get_hz(void); + +/** + * @brief Select source for RTC_FAST_CLK + * @param clk_src clock source (one of soc_rtc_fast_clk_src_t values) + */ +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src); + +/** + * @brief Get the RTC_FAST_CLK source + * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) + */ +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); + +/** + * @brief Get CPU frequency config for a given frequency + * @param freq_mhz Frequency in MHz + * @param[out] out_config Output, CPU frequency configuration structure + * @return true if frequency can be obtained, false otherwise + */ +bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU frequency + * + * This function sets CPU frequency according to the given configuration + * structure. It enables PLLs, if necessary. + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config); + +/** + * @brief Switch CPU frequency (optimized for speed) + * + * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. + * It works faster because it does not disable PLLs when switching from PLL to + * XTAL and does not enabled them when switching back. If PLL is not already + * enabled when this function is called to switch from XTAL to PLL frequency, + * or the PLL which is enabled is the wrong one, this function will fall back + * to calling rtc_clk_cpu_freq_set_config. + * + * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, + * so it is less safe to use it e.g. from a panic handler (when memory might + * be corrupted). + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config); + +/** + * @brief Get the currently used CPU frequency configuration + * @param[out] out_config Output, CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU clock source to XTAL + * + * Short form for filling in rtc_cpu_freq_config_t structure and calling + * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. + * Assumes that XTAL frequency has been determined — don't call in startup code. + * + * @note On ESP32H21, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be + * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + */ +void rtc_clk_cpu_freq_set_xtal(void); + +/** + * @brief Get the current stored APB frequency. + * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz. + */ +uint32_t rtc_clk_apb_freq_get(void); + +/** + * @brief Measure RTC slow clock's period, based on main XTAL frequency + * + * This function will time out and return 0 if the time for the given number + * of cycles to be counted exceeds the expected time twice. This may happen if + * 32k XTAL is being calibrated, but the oscillator has not started up (due to + * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). + * + * @param cal_clk clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average slow clock period in microseconds, Q13.19 fixed point format, + * or 0 if calibration has timed out + */ +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles + * @param time_in_us Time interval in microseconds + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return number of slow clock cycles + */ +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); + +/** + * @brief Convert time interval from RTC_SLOW_CLK to microseconds + * @param time_in_us Time interval in RTC_SLOW_CLK cycles + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return time interval in microseconds + */ +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); + +/** + * @brief Get current value of RTC counter + * + * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK + * cycles. Counter value is not writable by software. The value is not adjusted + * when switching to a different RTC_SLOW_CLK source. + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter + */ +uint64_t rtc_time_get(void); + +/** + * @brief Enable the rtc digital 8M clock + * + * This function is used to enable the digital rtc 8M clock to support peripherals. + * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above. + */ +void rtc_dig_clk8m_enable(void); + +/** + * @brief Disable the rtc digital 8M clock + * + * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals. + */ +void rtc_dig_clk8m_disable(void); + +/** + * @brief Get whether the rtc digital 8M clock is enabled + */ +bool rtc_dig_8m_enabled(void); + +/** + * @brief Calculate the real clock value after the clock calibration + * + * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal` + * @return Frequency of the clock in Hz + */ +uint32_t rtc_clk_freq_cal(uint32_t cal_val); + +// -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- +// **WARNING**: The following are only for backwards compatibility. +// Please use the declarations in soc/clk_tree_defs.h instead. +/** + * @brief CPU clock source + */ +typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t; +#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL +#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (96M) +#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 8M RTC oscillator + +/** + * @brief RTC SLOW_CLK frequency values + */ +typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t; +#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator +#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL + +/** + * @brief RTC FAST_CLK frequency values + */ +typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t; +#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2 +#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator + +/** + * @brief Possible main XTAL frequency values. + */ +typedef soc_xtal_freq_t rtc_xtal_freq_t; +#define RTC_XTAL_FREQ_32M SOC_XTAL_FREQ_32M //!< 32 MHz XTAL + +/* Alias of frequency related macros */ +#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX +#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX +#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX +#define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX + +/* Alias of deprecated function names */ +#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq) +#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get() +#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq) +#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get() + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/port/esp32h21/io_mux.c b/components/esp_hw_support/port/esp32h21/io_mux.c index e69de29bb2..38762bd4f7 100644 --- a/components/esp_hw_support/port/esp32h21/io_mux.c +++ b/components/esp_hw_support/port/esp32h21/io_mux.c @@ -0,0 +1,8 @@ + +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +//TODO: [ESP32H21] IDF-11611 diff --git a/components/esp_hw_support/port/esp32h21/rtc_clk.c b/components/esp_hw_support/port/esp32h21/rtc_clk.c new file mode 100644 index 0000000000..fda52e20e2 --- /dev/null +++ b/components/esp_hw_support/port/esp32h21/rtc_clk.c @@ -0,0 +1,458 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include "sdkconfig.h" +#include "rom/rtc.h" +#include "soc/rtc.h" +#include "esp_private/rtc_clk.h" +#include "esp_hw_log.h" +#include "esp_rom_sys.h" +#include "hal/clk_tree_ll.h" +#include "hal/regi2c_ctrl_ll.h" +#include "soc/io_mux_reg.h" +#include "soc/lp_aon_reg.h" +#include "esp_private/sleep_event.h" +#include "esp_private/regi2c_ctrl.h" + +static const char *TAG = "rtc_clk"; + +// Current PLL frequency, in 96MHz. Zero if PLL is not enabled. +static int s_cur_pll_freq; + +static uint32_t s_bbpll_digi_consumers_ref_count = 0; // Currently, it only tracks whether the 48MHz PHY clock is in-use by USB Serial/JTAG + +void rtc_clk_bbpll_add_consumer(void) +{ + s_bbpll_digi_consumers_ref_count += 1; +} + +void rtc_clk_bbpll_remove_consumer(void) +{ + s_bbpll_digi_consumers_ref_count -= 1; +} + +void rtc_clk_32k_enable(bool enable) +{ + if (enable) { + clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL); + } else { + clk_ll_xtal32k_disable(); + } +} + +void rtc_clk_32k_enable_external(void) +{ + // EXT_OSC_SLOW_GPIO_NUM == GPIO_NUM_13 + PIN_INPUT_ENABLE(IO_MUX_GPIO13_REG); + REG_SET_BIT(LP_AON_GPIO_HOLD0_REG, BIT(EXT_OSC_SLOW_GPIO_NUM)); + clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL); +} + +void rtc_clk_32k_bootstrap(uint32_t cycle) +{ + /* No special bootstrapping needed for ESP32-H2, 'cycle' argument is to keep the signature + * same as for the ESP32. Just enable the XTAL here. + */ + (void)cycle; + rtc_clk_32k_enable(true); +} + +bool rtc_clk_32k_enabled(void) +{ + return clk_ll_xtal32k_is_enabled(); +} + +void rtc_clk_rc32k_enable(bool enable) +{ + if (enable) { + clk_ll_rc32k_enable(); + esp_rom_delay_us(SOC_DELAY_RC32K_ENABLE); + } else { + clk_ll_rc32k_disable(); + } +} + +void rtc_clk_8m_enable(bool clk_8m_en) +{ + if (clk_8m_en) { + clk_ll_rc_fast_enable(); + esp_rom_delay_us(SOC_DELAY_RC_FAST_ENABLE); + } else { + clk_ll_rc_fast_disable(); + } +} + +bool rtc_clk_8m_enabled(void) +{ + return clk_ll_rc_fast_is_enabled(); +} + +void rtc_clk_lp_pll_enable(bool enable) +{ + if (enable) { + clk_ll_lp_pll_enable(); + esp_rom_delay_us(SOC_DELAY_LP_PLL_ENABLE); + } else { + clk_ll_lp_pll_disable(); + } +} + +void rtc_clk_lp_pll_src_set(soc_lp_pll_clk_src_t clk_src) +{ + clk_ll_lp_pll_set_src(clk_src); + esp_rom_delay_us(SOC_DELAY_LP_PLL_SWITCH); +} + +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src) +{ + clk_ll_rtc_slow_set_src(clk_src); + esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH); +} + +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void) +{ + return clk_ll_rtc_slow_get_src(); +} + +uint32_t rtc_clk_slow_freq_get_hz(void) +{ + switch (rtc_clk_slow_src_get()) { + case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: return SOC_CLK_OSC_SLOW_FREQ_APPROX; + default: return 0; + } +} + +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src) +{ + clk_ll_rtc_fast_set_src(clk_src); + esp_rom_delay_us(SOC_DELAY_RTC_FAST_CLK_SWITCH); +} + +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void) +{ + return clk_ll_rtc_fast_get_src(); +} + +static void rtc_clk_bbpll_disable(void) +{ + clk_ll_bbpll_disable(); + s_cur_pll_freq = 0; +} + +static void rtc_clk_bbpll_enable(void) +{ + clk_ll_bbpll_enable(); +} + +static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) +{ + /* Digital part */ + clk_ll_bbpll_set_freq_mhz(pll_freq); + + /* Analog part */ + ANALOG_CLOCK_ENABLE(); + /* BBPLL CALIBRATION START */ + regi2c_ctrl_ll_bbpll_calibration_start(); + clk_ll_bbpll_set_config(pll_freq, xtal_freq); + /* WAIT CALIBRATION DONE */ + while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + esp_rom_delay_us(10); + /* BBPLL CALIBRATION STOP */ + regi2c_ctrl_ll_bbpll_calibration_stop(); + ANALOG_CLOCK_DISABLE(); + + s_cur_pll_freq = pll_freq; +} + +/** + * Switch to use XTAL as the CPU clock source. + * Must satisfy: cpu_freq = XTAL_FREQ / div. + * Does not disable the PLL. + */ +static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div) +{ + // let f_cpu = f_ahb + clk_ll_cpu_set_divider(div); + clk_ll_ahb_set_divider(div); + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL); + clk_ll_bus_update(); + esp_rom_set_cpu_ticks_per_us(cpu_freq); +} + +static void rtc_clk_cpu_freq_to_8m(void) +{ + // let f_cpu = f_ahb + clk_ll_cpu_set_divider(1); + clk_ll_ahb_set_divider(1); + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST); + clk_ll_bus_update(); + esp_rom_set_cpu_ticks_per_us(8); +} + +/** + * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL. + * PLL must already be enabled. + * @param cpu_freq new CPU frequency + */ +static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) +{ + // f_hp_root = 96MHz + uint32_t cpu_divider = CLK_LL_PLL_96M_FREQ_MHZ / cpu_freq_mhz; + clk_ll_cpu_set_divider(cpu_divider); + // Constraint: f_ahb <= 32MHz; f_cpu = N * f_ahb (N = 1, 2, 3...) + uint32_t ahb_divider = (cpu_divider == 1) ? 3 : + (cpu_divider == 2) ? 4 : cpu_divider; + clk_ll_ahb_set_divider(ahb_divider); + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL); + clk_ll_bus_update(); + esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz); +} + +/** + * Switch to FLASH_PLL as cpu clock source. + * On ESP32H2, FLASH_PLL frequency is 64MHz. + * PLL must already be enabled. + */ +static void rtc_clk_cpu_freq_to_flash_pll(uint32_t cpu_freq_mhz, uint32_t cpu_divider) +{ + // f_hp_root = 64MHz + clk_ll_cpu_set_divider(cpu_divider); + // Constraint: f_ahb <= 32MHz; f_cpu = N * f_ahb (N = 1, 2, 3...) + uint32_t ahb_divider = (cpu_divider == 1) ? 2 : cpu_divider; + clk_ll_ahb_set_divider(ahb_divider); + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_FLASH_PLL); + clk_ll_bus_update(); + esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz); +} + +bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config) +{ + uint32_t source_freq_mhz; + soc_cpu_clk_src_t source; + uint32_t divider; // divider = freq of SOC_ROOT_CLK / freq of CPU_CLK + uint32_t real_freq_mhz; + + uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get(); + if (freq_mhz <= xtal_freq && freq_mhz != 0) { + divider = xtal_freq / freq_mhz; + real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ + if (real_freq_mhz != freq_mhz) { + // no suitable divider + return false; + } + + source_freq_mhz = xtal_freq; + source = SOC_CPU_CLK_SRC_XTAL; + } else if (freq_mhz == 96) { + real_freq_mhz = freq_mhz; + source = SOC_CPU_CLK_SRC_PLL; + source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ; + divider = 1; + } else if (freq_mhz == 64) { + real_freq_mhz = freq_mhz; + source = SOC_CPU_CLK_SRC_FLASH_PLL; + source_freq_mhz = CLK_LL_PLL_64M_FREQ_MHZ; + divider = 1; + } else if (freq_mhz == 48) { + real_freq_mhz = freq_mhz; + source = SOC_CPU_CLK_SRC_PLL; + source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ; + divider = 2; + } else { + // unsupported frequency + return false; + } + *out_config = (rtc_cpu_freq_config_t) { + .source = source, + .div = divider, + .source_freq_mhz = source_freq_mhz, + .freq_mhz = real_freq_mhz + }; + return true; +} + +__attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id) +{ +} + +void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) +{ + soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src(); + if (config->source == SOC_CPU_CLK_SRC_XTAL) { + rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); + if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL || old_cpu_clk_src == SOC_CPU_CLK_SRC_FLASH_PLL) && + !s_bbpll_digi_consumers_ref_count) { + rtc_clk_bbpll_disable(); + } + } else if (config->source == SOC_CPU_CLK_SRC_PLL) { + if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL && old_cpu_clk_src != SOC_CPU_CLK_SRC_FLASH_PLL) { + rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START); + rtc_clk_bbpll_enable(); + rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz); + } + rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); + rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP); + } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { + rtc_clk_cpu_freq_to_8m(); + if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL || old_cpu_clk_src == SOC_CPU_CLK_SRC_FLASH_PLL) && + !s_bbpll_digi_consumers_ref_count) { + rtc_clk_bbpll_disable(); + } + } else if (config->source == SOC_CPU_CLK_SRC_FLASH_PLL) { + if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL && old_cpu_clk_src != SOC_CPU_CLK_SRC_FLASH_PLL) { + // On ESP32H2, FLASH_PLL (64MHz) is directly derived from the BBPLL (96MHz) + // Therefore, enabling and configuration are applied to BBPLL. + rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_FLASH_BBPLL_EN_START); + rtc_clk_bbpll_enable(); + rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_96M_FREQ_MHZ); + } + rtc_clk_cpu_freq_to_flash_pll(config->freq_mhz, config->div); + rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_FLASH_BBPLL_EN_STOP); + } +} + +void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) +{ + soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); + uint32_t source_freq_mhz; + uint32_t div = clk_ll_cpu_get_divider(); // div = freq of SOC_ROOT_CLK / freq of CPU_CLK + uint32_t freq_mhz; + switch (source) { + case SOC_CPU_CLK_SRC_XTAL: { + source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get(); + freq_mhz = source_freq_mhz / div; + break; + } + case SOC_CPU_CLK_SRC_PLL: { + source_freq_mhz = clk_ll_bbpll_get_freq_mhz(); + freq_mhz = source_freq_mhz / div; + break; + } + case SOC_CPU_CLK_SRC_RC_FAST: + source_freq_mhz = 8; + freq_mhz = source_freq_mhz / div; + break; + case SOC_CPU_CLK_SRC_FLASH_PLL: + source_freq_mhz = clk_ll_flash_pll_get_freq_mhz(); + freq_mhz = source_freq_mhz / div; + break; + default: + ESP_HW_LOGE(TAG, "unsupported frequency configuration"); + abort(); + } + *out_config = (rtc_cpu_freq_config_t) { + .source = source, + .source_freq_mhz = source_freq_mhz, + .div = div, + .freq_mhz = freq_mhz + }; +} + +void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) +{ + if (config->source == SOC_CPU_CLK_SRC_XTAL) { + rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); + } else if (config->source == SOC_CPU_CLK_SRC_PLL && + s_cur_pll_freq == config->source_freq_mhz) { + rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); + } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { + rtc_clk_cpu_freq_to_8m(); + } else if (config->source == SOC_CPU_CLK_SRC_FLASH_PLL && + s_cur_pll_freq == clk_ll_bbpll_get_freq_mhz()) { + // On ESP32H2, FLASH_PLL (64MHz) is directly derived from the BBPLL (96MHz) + // Therefore, as long as bbpll was not disabled, no need to re-enable and re-configure parameters for the source clock + rtc_clk_cpu_freq_to_flash_pll(config->freq_mhz, config->div); + } else { + /* fallback */ + rtc_clk_cpu_freq_set_config(config); + } +} + +void rtc_clk_cpu_freq_set_xtal(void) +{ + rtc_clk_cpu_set_to_default_config(); + rtc_clk_bbpll_disable(); +} + +void rtc_clk_cpu_set_to_default_config(void) +{ + int freq_mhz = (int)rtc_clk_xtal_freq_get(); + + rtc_clk_cpu_freq_to_xtal(freq_mhz, 1); + s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep +} + +soc_xtal_freq_t rtc_clk_xtal_freq_get(void) +{ + uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz(); + if (xtal_freq_mhz == 0) { + ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 32MHz"); + return SOC_XTAL_FREQ_32M; + } + return (soc_xtal_freq_t)xtal_freq_mhz; +} + +void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq) +{ + clk_ll_xtal_store_freq_mhz(xtal_freq); +} + +static uint32_t rtc_clk_ahb_freq_get(void) +{ + soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); + uint32_t soc_root_freq_mhz; + uint32_t divider = clk_ll_ahb_get_divider(); + switch (source) { + case SOC_CPU_CLK_SRC_XTAL: + soc_root_freq_mhz = rtc_clk_xtal_freq_get(); + break; + case SOC_CPU_CLK_SRC_PLL: + soc_root_freq_mhz = clk_ll_bbpll_get_freq_mhz(); + break; + case SOC_CPU_CLK_SRC_RC_FAST: + soc_root_freq_mhz = 8; + break; + case SOC_CPU_CLK_SRC_FLASH_PLL: + soc_root_freq_mhz = clk_ll_flash_pll_get_freq_mhz(); + break; + default: + // Unknown SOC_ROOT clock source + soc_root_freq_mhz = 0; + ESP_HW_LOGE(TAG, "Invalid SOC_ROOT_CLK"); + break; + } + return soc_root_freq_mhz / divider; +} + +uint32_t rtc_clk_apb_freq_get(void) +{ + return rtc_clk_ahb_freq_get() / clk_ll_apb_get_divider() * MHZ; +} + +void rtc_dig_clk8m_enable(void) +{ + clk_ll_rc_fast_digi_enable(); + esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH); +} + +void rtc_dig_clk8m_disable(void) +{ + clk_ll_rc_fast_digi_disable(); + esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH); +} + +bool rtc_dig_8m_enabled(void) +{ + return clk_ll_rc_fast_digi_is_enabled(); +} diff --git a/components/esp_hw_support/port/esp32h21/rtc_clk_init.c b/components/esp_hw_support/port/esp32h21/rtc_clk_init.c new file mode 100644 index 0000000000..488e764b79 --- /dev/null +++ b/components/esp_hw_support/port/esp32h21/rtc_clk_init.c @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "rom/ets_sys.h" +#include "rom/rtc.h" +#include "rom/uart.h" +#include "soc/rtc.h" +#include "esp_cpu.h" +#include "regi2c_ctrl.h" +#include "soc/lp_clkrst_reg.h" +#include "soc/regi2c_pmu.h" +#include "esp_hw_log.h" +#include "sdkconfig.h" +#include "esp_rom_uart.h" +#include "hal/clk_tree_ll.h" +#include "soc/pmu_reg.h" +#include "pmu_param.h" + +static const char *TAG = "rtc_clk_init"; + +void rtc_clk_init(rtc_clk_config_t cfg) +{ + rtc_cpu_freq_config_t old_config, new_config; + + /* Set tuning parameters for RC_FAST, RC_SLOW, and RC32K clocks. + * Note: this doesn't attempt to set the clocks to precise frequencies. + * Instead, we calibrate these clocks against XTAL frequency later, when necessary. + * - SCK_DCAP value controls tuning of RC_SLOW clock. + * The higher the value of DCAP is, the lower is the frequency. + * - CK8M_DFREQ value controls tuning of RC_FAST clock. + * CLK_8M_DFREQ constant gives the best temperature characteristics. + * - RC32K_DFREQ value controls tuning of RC32K clock. + */ + REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq); + REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OC_SCK_DCAP, cfg.slow_clk_dcap); + REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq); + + REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, 0); + REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, 0); + + uint32_t hp_cali_dbias = get_act_hp_dbias(); + uint32_t lp_cali_dbias = get_act_lp_dbias(); + + SET_PERI_REG_BITS(PMU_HP_MODEM_HP_REGULATOR0_REG, PMU_HP_MODEM_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_MODEM_HP_REGULATOR_DBIAS_S); + SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S); + SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, lp_cali_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S); + + soc_xtal_freq_t xtal_freq = cfg.xtal_freq; + esp_rom_output_tx_wait_idle(0); + rtc_clk_xtal_freq_update(xtal_freq); + + /* Set CPU frequency */ + rtc_clk_cpu_freq_get_config(&old_config); + uint32_t freq_before = old_config.freq_mhz; + bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config); + if (!res) { + ESP_HW_LOGE(TAG, "invalid CPU frequency value"); + abort(); + } + rtc_clk_cpu_freq_set_config(&new_config); + + /* Re-calculate the ccount to make time calculation correct. */ + esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); + + /* Slow & fast clocks setup */ + // We will not power off RC_FAST in bootloader stage even if it is not being used as any + // cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage. + bool need_rc_fast_en = true; + if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + rtc_clk_32k_enable(true); + } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { + rtc_clk_32k_enable_external(); + } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { + rtc_clk_rc32k_enable(true); + } + rtc_clk_8m_enable(need_rc_fast_en); + rtc_clk_fast_src_set(cfg.fast_clk_src); + rtc_clk_slow_src_set(cfg.slow_clk_src); +} diff --git a/components/esp_hw_support/port/esp32h21/rtc_time.c b/components/esp_hw_support/port/esp32h21/rtc_time.c new file mode 100644 index 0000000000..1da5fdab43 --- /dev/null +++ b/components/esp_hw_support/port/esp32h21/rtc_time.c @@ -0,0 +1,292 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "rom/ets_sys.h" +#include "soc/rtc.h" +#include "hal/lp_timer_hal.h" +#include "hal/clk_tree_ll.h" +#include "hal/timer_ll.h" +#include "soc/timer_group_reg.h" +#include "soc/pcr_reg.h" +#include "esp_rom_sys.h" +#include "assert.h" +#include "hal/efuse_hal.h" +#include "soc/chip_revision.h" +#include "esp_private/periph_ctrl.h" + +__attribute__((unused)) static const char *TAG = "rtc_time"; + +/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. + * This feature counts the number of XTAL clock cycles within a given number of + * RTC_SLOW_CLK cycles. + * + * Slow clock calibration feature has two modes of operation: one-off and cycling. + * In cycling mode (which is enabled by default on SoC reset), counting of XTAL + * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled + * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed + * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is + * enabled using TIMG_RTC_CALI_START bit. + */ + +/* On ESP32H21, TIMG_RTC_CALI_CLK_SEL can config to 0, 1, 2, 3 + * 0 or 3: calibrate RC_SLOW clock + * 1: calibrate RC_FAST clock + * 2: calibrate 32K clock, which 32k depends on reg_32k_sel: 0: Internal 32 kHz RC oscillator, 1: External 32 kHz XTAL, 2: External 32kHz clock input by gpio13 + */ +#define TIMG_RTC_CALI_CLK_SEL_RC_SLOW 0 +#define TIMG_RTC_CALI_CLK_SEL_RC_FAST 1 +#define TIMG_RTC_CALI_CLK_SEL_32K 2 + +/** + * @brief Clock calibration function used by rtc_clk_cal + * + * Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. + * This feature counts the number of XTAL clock cycles within a given number of + * RTC_SLOW_CLK cycles. + * + * Slow clock calibration feature has two modes of operation: one-off and cycling. + * In cycling mode (which is enabled by default on SoC reset), counting of XTAL + * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled + * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed + * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is + * enabled using TIMG_RTC_CALI_START bit. + * + * @param cal_clk which clock to calibrate + * @param slowclk_cycles number of slow clock cycles to count + * @return number of XTAL clock cycles within the given number of slow clock cycles + */ +static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) +{ + assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V); + + uint32_t cali_clk_sel = 0; + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); + soc_rtc_slow_clk_src_t old_32k_cal_clk_sel = clk_ll_32k_calibration_get_target(); + if (cal_clk == RTC_CAL_RTC_MUX) { + cal_clk = (rtc_cal_sel_t)slow_clk_src; + } + if (cal_clk == RTC_CAL_RC_FAST) { + cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_FAST; + } else if (cal_clk == RTC_CAL_RC_SLOW) { + cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_SLOW; + } else { + cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_32K; + clk_ll_32k_calibration_set_target((soc_rtc_slow_clk_src_t)cal_clk); + } + + + /* Enable requested clock (150k clock is always on) */ + // All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock + // Only enable if originally was disabled, and set back to the disable state after calibration is done + // If the clock is already on, then do nothing + bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); + if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { + clk_ll_xtal32k_digi_enable(); + } + + bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); + bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled(); + if (cal_clk == RTC_CAL_RC_FAST) { + if (!rc_fast_enabled) { + rtc_clk_8m_enable(true); + } + if (!dig_rc_fast_enabled) { + rtc_dig_clk8m_enable(); + } + } + + bool rc32k_enabled = clk_ll_rc32k_is_enabled(); + bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled(); + if (cal_clk == RTC_CAL_RC32K) { + if (!rc32k_enabled) { + rtc_clk_rc32k_enable(true); + } + if (!dig_rc32k_enabled) { + clk_ll_rc32k_digi_enable(); + } + } + + /* There may be another calibration process already running during we call this function, + * so we should wait the last process is done. + */ + if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { + /** + * Set a small timeout threshold to accelerate the generation of timeout. + * The internal circuit will be reset when the timeout occurs and will not affect the next calibration. + */ + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1); + while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) + && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); + } + + /* Prepare calibration */ + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel); + if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_RC_FAST) { + clk_ll_rc_fast_tick_conf(); + } + CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); + /* Figure out how long to wait for calibration to finish */ + + /* Set timeout reg and expect time delay*/ + uint32_t expected_freq; + if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_32K) { + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; + } else if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_RC_FAST) { + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX; + if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) { + expected_freq = expected_freq >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; + } + } else { + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; + } + uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); + /* Start calibration */ + CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); + SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); + + /* Wait for calibration to finish up to another us_time_estimate */ + esp_rom_delay_us(us_time_estimate); + uint32_t cal_val; + while (true) { + if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { + cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); + + /*The Fosc CLK of calibration circuit is divided by 32 for ECO2. + So we need to multiply the frequency of the Fosc for ECO2 and above chips by 32 times. + And ensure that this modification will not affect ECO0 and ECO1. + And the 32-divider belongs to REF_TICK module, so we need to enable its clock during + calibration. */ + if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) { + if (cal_clk == RTC_CAL_RC_FAST) { + cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; + CLEAR_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); + } + } + break; + } + if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { + cal_val = 0; + break; + } + } + CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); + + /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ + if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { + clk_ll_xtal32k_digi_disable(); + } + + if (cal_clk == RTC_CAL_RC_FAST) { + if (!dig_rc_fast_enabled) { + rtc_dig_clk8m_disable(); + } + if (!rc_fast_enabled) { + rtc_clk_8m_enable(false); + } + } + + if (cal_clk == RTC_CAL_RC32K) { + if (!dig_rc32k_enabled) { + clk_ll_rc32k_digi_disable(); + } + if (!rc32k_enabled) { + rtc_clk_rc32k_enable(false); + } + } + + // Always set back the calibration 32kHz clock selection + if (old_32k_cal_clk_sel != SOC_RTC_SLOW_CLK_SRC_INVALID) { + clk_ll_32k_calibration_set_target(old_32k_cal_clk_sel); + } + + return cal_val; +} + +static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles) +{ + uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768 + uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 = 0.05% error range + return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); +} + +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) +{ + assert(slowclk_cycles); + soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); + + /*The Fosc CLK of calibration circuit is divided by 32 for ECO2. + So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to + avoid excessive calibration time.*/ + if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) { + if (cal_clk == RTC_CAL_RC_FAST) { + slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; + SET_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); + } + } + + uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); + + if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { + return 0; + } + + uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; + uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; + uint32_t period = (uint32_t)(period_64 & UINT32_MAX); + return period; +} + +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) +{ + assert(period); + /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days. + * TODO: fix overflow. + */ + return (time_in_us << RTC_CLK_CAL_FRACT) / period; +} + +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period) +{ + return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT; +} + +uint64_t rtc_time_get(void) +{ + ESP_EARLY_LOGW(TAG, "rtc_timer has not been implemented yet"); + return 0; + //TODO: [ESP32H21] IDF-11548 + // return lp_timer_hal_get_cycle_count(); +} + +uint32_t rtc_clk_freq_cal(uint32_t cal_val) +{ + if (cal_val == 0) { + return 0; // cal_val will be denominator, return 0 as the symbol of failure. + } + return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val; +} + +/// @brief if the calibration is used, we need to enable the timer group0 first +__attribute__((constructor)) +static void enable_timer_group0_for_calibration(void) +{ +#ifndef BOOTLOADER_BUILD + PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { + if (ref_count == 0) { + timer_ll_enable_bus_clock(0, true); + timer_ll_reset_register(0); + } + } +#else + _timer_ll_enable_bus_clock(0, true); + _timer_ll_reset_register(0); +#endif +} diff --git a/components/esp_hw_support/port/esp32h21/systimer.c b/components/esp_hw_support/port/esp32h21/systimer.c index e69de29bb2..f6c0c912bf 100644 --- a/components/esp_hw_support/port/esp32h21/systimer.c +++ b/components/esp_hw_support/port/esp32h21/systimer.c @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_private/systimer.h" + +/** + * @brief When systimer's clock source is XTAL (32MHz), it has a fixed fractional divider (2). + * So the resolution of the systimer is 32MHz/2 = 16MHz. + */ +uint64_t systimer_ticks_to_us(uint64_t ticks) +{ + return ticks / 16; +} + +uint64_t systimer_us_to_ticks(uint64_t us) +{ + return us * 16; +} diff --git a/components/esp_mm/port/esp32h21/ext_mem_layout.c b/components/esp_mm/port/esp32h21/ext_mem_layout.c index e69de29bb2..8ab04d1c58 100644 --- a/components/esp_mm/port/esp32h21/ext_mem_layout.c +++ b/components/esp_mm/port/esp32h21/ext_mem_layout.c @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "sdkconfig.h" +#include "soc/ext_mem_defs.h" +#include "../ext_mem_layout.h" +#include "hal/mmu_types.h" + +/** + * The start addresses in this list should always be sorted from low to high, as MMU driver will need to + * coalesce adjacent regions + */ +const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = { + [0] = { + .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW, + .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH, + .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR), + .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0, + .targets = MMU_TARGET_FLASH0, + .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT, + }, +}; diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c index 7fcca7d450..cfd29a8627 100644 --- a/components/esp_pm/pm_impl.c +++ b/components/esp_pm/pm_impl.c @@ -103,6 +103,8 @@ #define REF_CLK_DIV_MIN 2 #elif CONFIG_IDF_TARGET_ESP32H2 #define REF_CLK_DIV_MIN 2 +#elif CONFIG_IDF_TARGET_ESP32H21 +#define REF_CLK_DIV_MIN 2 #elif CONFIG_IDF_TARGET_ESP32P4 #define REF_CLK_DIV_MIN 2 #endif diff --git a/components/esp_rom/esp32h2/include/esp32h2/rom/gpio.h b/components/esp_rom/esp32h2/include/esp32h2/rom/gpio.h index acd5bac6ca..5829765c60 100644 --- a/components/esp_rom/esp32h2/include/esp32h2/rom/gpio.h +++ b/components/esp_rom/esp32h2/include/esp32h2/rom/gpio.h @@ -84,7 +84,7 @@ uint32_t gpio_input_get(void); */ void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); -/**c +/** * @brief disable GPIOs to wakeup the ESP32. * Please do not call this function in SDK. * diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h b/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h index 4f72fa87e5..768bbabdf2 100644 --- a/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h @@ -53,14 +53,16 @@ extern "C" { */ //TODO: [ESP32H21] IDF-1154, need to check from esp_rom -#define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG -#define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG -#define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG -#define RTC_XTAL_FREQ_REG LP_AON_STORE4_REG -#define RTC_ENTRY_LENGTH_REG LP_AON_STORE5_REG -#define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG -#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG -#define ROM_LOG_CTRL_REG LP_AON_STORE4_REG +#define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG +#define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG +#define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG +#define RTC_XTAL_FREQ_REG LP_AON_STORE4_REG +#define RTC_APB_FREQ_REG LP_AON_STORE5_REG +#define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG +#define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG +#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG +#define RTC_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG +#define RTC_SLEEP_MODE_REG LP_AON_STORE9_REG #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.ld index 78ef116c3d..564e5dbd1c 100644 --- a/components/esp_rom/esp32h21/ld/esp32h21.rom.ld +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.ld @@ -226,9 +226,8 @@ gpio_input_get = 0x4000069c; gpio_matrix_in = 0x400006a0; gpio_matrix_out = 0x400006a4; -//TODO: [ESP32H21] IDF-11621 -gpio_output_disable = 0x400006a8; -gpio_output_enable = 0x400006ac; +/*gpio_output_disable = 0x400006a8;*/ +/*gpio_output_enable = 0x400006ac;*/ gpio_output_set = 0x400006b0; gpio_pad_hold = 0x400006b4; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.libc.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.libc.ld new file mode 100644 index 0000000000..af79c5322c --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.libc.ld @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.libgcc.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group libgcc + ***************************************/ + +/* Functions */ +__absvdi2 = 0x4000084c; +__absvsi2 = 0x40000850; +__adddf3 = 0x40000854; +__addsf3 = 0x40000858; +__addvdi3 = 0x4000085c; +__addvsi3 = 0x40000860; +__ashldi3 = 0x40000864; +__ashrdi3 = 0x40000868; +__bswapdi2 = 0x4000086c; +__bswapsi2 = 0x40000870; +__clear_cache = 0x40000874; +__clrsbdi2 = 0x40000878; +__clrsbsi2 = 0x4000087c; +__clzdi2 = 0x40000880; +__clzsi2 = 0x40000884; +__cmpdi2 = 0x40000888; +__ctzdi2 = 0x4000088c; +__ctzsi2 = 0x40000890; +__divdc3 = 0x40000894; +__divdf3 = 0x40000898; +__divdi3 = 0x4000089c; +__divsc3 = 0x400008a0; +__divsf3 = 0x400008a4; +__divsi3 = 0x400008a8; +__eqdf2 = 0x400008ac; +__eqsf2 = 0x400008b0; +__extendsfdf2 = 0x400008b4; +__ffsdi2 = 0x400008b8; +__ffssi2 = 0x400008bc; +__fixdfdi = 0x400008c0; +__fixdfsi = 0x400008c4; +__fixsfdi = 0x400008c8; +__fixsfsi = 0x400008cc; +__fixunsdfsi = 0x400008d0; +__fixunssfdi = 0x400008d4; +__fixunssfsi = 0x400008d8; +__floatdidf = 0x400008dc; +__floatdisf = 0x400008e0; +__floatsidf = 0x400008e4; +__floatsisf = 0x400008e8; +__floatundidf = 0x400008ec; +__floatundisf = 0x400008f0; +__floatunsidf = 0x400008f4; +__floatunsisf = 0x400008f8; +__gcc_bcmp = 0x400008fc; +__gedf2 = 0x40000900; +__gesf2 = 0x40000904; +__gtdf2 = 0x40000908; +__gtsf2 = 0x4000090c; +__ledf2 = 0x40000910; +__lesf2 = 0x40000914; +__lshrdi3 = 0x40000918; +__ltdf2 = 0x4000091c; +__ltsf2 = 0x40000920; +__moddi3 = 0x40000924; +__modsi3 = 0x40000928; +__muldc3 = 0x4000092c; +__muldf3 = 0x40000930; +__muldi3 = 0x40000934; +__mulsc3 = 0x40000938; +__mulsf3 = 0x4000093c; +__mulsi3 = 0x40000940; +__mulvdi3 = 0x40000944; +__mulvsi3 = 0x40000948; +__nedf2 = 0x4000094c; +__negdf2 = 0x40000950; +__negdi2 = 0x40000954; +__negsf2 = 0x40000958; +__negvdi2 = 0x4000095c; +__negvsi2 = 0x40000960; +__nesf2 = 0x40000964; +__paritysi2 = 0x40000968; +__popcountdi2 = 0x4000096c; +__popcountsi2 = 0x40000970; +__powidf2 = 0x40000974; +__powisf2 = 0x40000978; +__subdf3 = 0x4000097c; +__subsf3 = 0x40000980; +__subvdi3 = 0x40000984; +__subvsi3 = 0x40000988; +__truncdfsf2 = 0x4000098c; +__ucmpdi2 = 0x40000990; +__udivdi3 = 0x40000994; +__udivmoddi4 = 0x40000998; +__udivsi3 = 0x4000099c; +__udiv_w_sdiv = 0x400009a0; +__umoddi3 = 0x400009a4; +__umodsi3 = 0x400009a8; +__unorddf2 = 0x400009ac; +__unordsf2 = 0x400009b0; +__extenddftf2 = 0x400009b4; +__trunctfdf2 = 0x400009b8; diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32h21.c b/components/esp_rom/patches/esp_rom_regi2c_esp32h21.c index e69de29bb2..3186c74d7b 100644 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32h21.c +++ b/components/esp_rom/patches/esp_rom_regi2c_esp32h21.c @@ -0,0 +1,187 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "esp_rom_sys.h" +#include "esp_attr.h" +#include "soc/i2c_ana_mst_reg.h" +#include "hal/regi2c_ctrl_ll.h" + +/** + * BB - 0x67 - BIT0 + * TXRF - 0x6B - BIT1 + * SDM - 0x63 - BIT2 + * PLL - 0x62 - BIT3 + * BIAS - 0x6A - BIT4 + * BBPLL - 0x66 - BIT5 + * ULP - 0x61 - BIT6 + * SAR - 0x69 - BIT7 + * PMU - 0x6d - BIT8 +*/ + +#define REGI2C_BIAS_MST_SEL (BIT(8)) +#define REGI2C_BBPLL_MST_SEL (BIT(9)) +#define REGI2C_ULP_CAL_MST_SEL (BIT(10)) +#define REGI2C_SAR_I2C_MST_SEL (BIT(11)) +#define REGI2C_DIG_REG_MST_SEL (BIT(12)) + +#define REGI2C_BIAS_RD_MASK (~BIT(6) & I2C_MST_ANA_CONF1_M) +#define REGI2C_BBPLL_RD_MASK (~BIT(7) & I2C_MST_ANA_CONF1_M) +#define REGI2C_ULP_CAL_RD_MASK (~BIT(8) & I2C_MST_ANA_CONF1_M) +#define REGI2C_SAR_I2C_RD_MASK (~BIT(9) & I2C_MST_ANA_CONF1_M) +#define REGI2C_DIG_REG_RD_MASK (~BIT(10) & I2C_MST_ANA_CONF1_M) + +#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG + +#define REGI2C_RTC_BUSY (BIT(25)) +#define REGI2C_RTC_BUSY_M (BIT(25)) +#define REGI2C_RTC_BUSY_V 0x1 +#define REGI2C_RTC_BUSY_S 25 + +#define REGI2C_RTC_WR_CNTL (BIT(24)) +#define REGI2C_RTC_WR_CNTL_M (BIT(24)) +#define REGI2C_RTC_WR_CNTL_V 0x1 +#define REGI2C_RTC_WR_CNTL_S 24 + +#define REGI2C_RTC_DATA 0x000000FF +#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S)) +#define REGI2C_RTC_DATA_V 0xFF +#define REGI2C_RTC_DATA_S 16 + +#define REGI2C_RTC_ADDR 0x000000FF +#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S)) +#define REGI2C_RTC_ADDR_V 0xFF +#define REGI2C_RTC_ADDR_S 8 + +#define REGI2C_RTC_SLAVE_ID 0x000000FF +#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S)) +#define REGI2C_RTC_SLAVE_ID_V 0xFF +#define REGI2C_RTC_SLAVE_ID_S 0 + +/* SLAVE */ + +#define REGI2C_BBPLL (0x66) +#define REGI2C_BBPLL_HOSTID 0 + +#define REGI2C_BIAS (0x6a) +#define REGI2C_BIAS_HOSTID 0 + +#define REGI2C_PMU (0x6d) +#define REGI2C_PMU_HOSTID 0 + +#define REGI2C_ULP_CAL (0x61) +#define REGI2C_ULP_CAL_HOSTID 0 + +#define REGI2C_SAR_I2C (0x69) +#define REGI2C_SAR_I2C_HOSTID 0 + +/* SLAVE END */ + +uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); +uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); +void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); +void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); + +static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +{ + uint32_t i2c_sel = 0; + regi2c_ctrl_ll_master_enable_clock(true); + + /* Before config I2C register, enable corresponding slave. */ + switch (block) { + case REGI2C_BBPLL : + i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL); + REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK); + break; + case REGI2C_BIAS : + i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); + REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK); + break; + case REGI2C_PMU: + i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); + REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK); + break; + case REGI2C_ULP_CAL: + i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL); + REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK); + break; + case REGI2C_SAR_I2C: + i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); + REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK); + break; + } + + return (uint8_t)(i2c_sel ? 0: 1); +} + +uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +{ + (void)host_id; + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + + return ret; +} + +uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +{ + assert(msb - lsb < 8); + uint8_t i2c_sel = regi2c_enable_block(block); + + (void)host_id; + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); + + return ret; +} + +void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +{ + (void)host_id; + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; + | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + +} + +void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +{ + (void)host_id; + assert(msb - lsb < 8); + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + /*Read the i2c bus register*/ + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + /*Write the i2c bus register*/ + temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); + temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; + temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); +} diff --git a/components/esp_security/src/esp32h21/.gitkeep b/components/esp_security/src/esp32h21/.gitkeep deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/components/esp_security/src/esp32h21/esp_crypto_clk.h b/components/esp_security/src/esp32h21/esp_crypto_clk.h new file mode 100644 index 0000000000..f56da30058 --- /dev/null +++ b/components/esp_security/src/esp32h21/esp_crypto_clk.h @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/soc.h" +#include "soc/pcr_reg.h" + +#pragma once + +static inline void esp_crypto_clk_init(void) +{ + // Set crypto clock (`clk_sec`) to use 96M PLL clock + REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3); +} diff --git a/components/esp_system/crosscore_int.c b/components/esp_system/crosscore_int.c index c7059e82a3..551184b525 100644 --- a/components/esp_system/crosscore_int.c +++ b/components/esp_system/crosscore_int.c @@ -20,6 +20,10 @@ #include "esp_gdbstub.h" #endif +#if CONFIG_IDF_TARGET_ESP32H21 +#define ETS_FROM_CPU_INTR0_SOURCE ETS_CPU_INTR_FROM_CPU_0_SOURCE +#endif + #define REASON_YIELD BIT(0) #define REASON_FREQ_SWITCH BIT(1) #define REASON_PRINT_BACKTRACE BIT(2) diff --git a/components/esp_system/fpga_overrides_clk.c b/components/esp_system/fpga_overrides_clk.c index 3c6fc73af6..29b53a01ee 100644 --- a/components/esp_system/fpga_overrides_clk.c +++ b/components/esp_system/fpga_overrides_clk.c @@ -50,8 +50,11 @@ void bootloader_clock_configure(void) { s_warn(); esp_rom_output_tx_wait_idle(0); - +#if CONFIG_IDF_TARGET_ESP32H21 + uint32_t xtal_freq_mhz = 32; +#else uint32_t xtal_freq_mhz = 40; +#endif #ifdef CONFIG_IDF_TARGET_ESP32S2 uint32_t apb_freq_hz = 20000000; #else diff --git a/components/esp_system/int_wdt.c b/components/esp_system/int_wdt.c index 4a3476ae2d..90f9daf719 100644 --- a/components/esp_system/int_wdt.c +++ b/components/esp_system/int_wdt.c @@ -28,6 +28,11 @@ #include "esp_private/sleep_retention.h" #endif +#if CONFIG_IDF_TARGET_ESP32H21 +#define ETS_TG0_WDT_LEVEL_INTR_SOURCE ETS_TG0_WDT_INTR_SOURCE +#define ETS_TG1_WDT_LEVEL_INTR_SOURCE ETS_TG1_WDT_INTR_SOURCE +#endif + #if SOC_TIMER_GROUPS > 1 /* If we have two hardware timer groups, use the second one for interrupt watchdog. */ diff --git a/components/esp_system/port/soc/esp32h21/cache_err_int.c b/components/esp_system/port/soc/esp32h21/cache_err_int.c index 9e7f1ba07f..c5085eb1ea 100644 --- a/components/esp_system/port/soc/esp32h21/cache_err_int.c +++ b/components/esp_system/port/soc/esp32h21/cache_err_int.c @@ -17,6 +17,7 @@ #include "soc/periph_defs.h" #include "riscv/interrupt.h" #include "hal/cache_ll.h" +#include "esp_private/cache_err_int.h" // TODO: [ESP32H21] IDF-11524 @@ -24,14 +25,15 @@ static const char *TAG = "CACHE_ERR"; const char cache_error_msg[] = "Cache access error"; -const char *esp_cache_err_panic_string(void) +void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info) { + if (err_info == NULL) { + return; + } const uint32_t access_err_status = cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); /* Return the error string if a cache error is active */ - const char* err_str = access_err_status ? cache_error_msg : NULL; - - return err_str; + err_info->err_str = access_err_status ? cache_error_msg : NULL; } bool esp_cache_err_has_active_err(void) diff --git a/components/esp_system/port/soc/esp32h21/clk.c b/components/esp_system/port/soc/esp32h21/clk.c index 40c120f036..3477f1a0f2 100644 --- a/components/esp_system/port/soc/esp32h21/clk.c +++ b/components/esp_system/port/soc/esp32h21/clk.c @@ -42,7 +42,6 @@ #define MHZ (1000000) static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src); -static __attribute__((unused)) void recalib_bbpll(void); static const char *TAG = "clk"; diff --git a/components/esp_system/port/soc/esp32h21/system_internal.c b/components/esp_system/port/soc/esp32h21/system_internal.c index 17319fafc6..d5799f12b2 100644 --- a/components/esp_system/port/soc/esp32h21/system_internal.c +++ b/components/esp_system/port/soc/esp32h21/system_internal.c @@ -23,7 +23,6 @@ #include "hal/wdt_hal.h" #include "hal/spimem_flash_ll.h" #include "esp_private/cache_err_int.h" -#include "esp_private/mspi_timing_tuning.h" #include "esp32h21/rom/cache.h" #include "esp32h21/rom/rtc.h" @@ -98,16 +97,6 @@ void IRAM_ATTR esp_restart_noos(void) esp_system_reset_modules_on_exit(); -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - /** - * Turn down MSPI speed - * - * We set MSPI clock to a high speed one before, ROM doesn't have such high speed clock source option. - * This function will change clock source to a ROM supported one when system restarts. - */ - mspi_timing_change_speed_mode_cache_safe(true); -#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - // Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader. #if !CONFIG_IDF_ENV_FPGA rtc_clk_cpu_set_to_default_config(); diff --git a/components/esp_system/task_wdt/task_wdt_impl_timergroup.c b/components/esp_system/task_wdt/task_wdt_impl_timergroup.c index 56cf317eea..628e5bb7f5 100644 --- a/components/esp_system/task_wdt/task_wdt_impl_timergroup.c +++ b/components/esp_system/task_wdt/task_wdt_impl_timergroup.c @@ -29,8 +29,11 @@ #define TWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz #define TWDT_PERIPH_MODULE PERIPH_TIMG0_MODULE #define TWDT_TIMER_GROUP 0 +#if CONFIG_IDF_TARGET_ESP32H21 +#define TWDT_INTR_SOURCE ETS_TG0_WDT_INTR_SOURCE +#else #define TWDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE - +#endif /** * Context for the software implementation of the Task WatchDog Timer. * This will be passed as a parameter to public functions below. */ diff --git a/components/hal/esp32h21/include/hal/clk_tree_ll.h b/components/hal/esp32h21/include/hal/clk_tree_ll.h index fb55e881c4..8dc7bb0eea 100644 --- a/components/hal/esp32h21/include/hal/clk_tree_ll.h +++ b/components/hal/esp32h21/include/hal/clk_tree_ll.h @@ -45,8 +45,8 @@ Set the frequency division factor of ref_tick The FOSC of rtc calibration uses the 32 frequency division clock for ECO2, So the frequency division factor of ref_tick must be greater than or equal to 32 */ -#define CLK_LL_RC_FAST_TICK_DIV_BITS 5 -#define REG_FOSC_TICK_NUM 255 +#define CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS 5 +#define REG_FOSC_TICK_NUM 255 /** * @brief XTAL32K_CLK enable modes diff --git a/components/hal/esp32h21/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32h21/include/hal/mspi_timing_tuning_ll.h new file mode 100644 index 0000000000..88e169d594 --- /dev/null +++ b/components/hal/esp32h21/include/hal/mspi_timing_tuning_ll.h @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +//TODO: [ESP32H21] IDF-11918 diff --git a/components/hal/esp32h21/include/hal/spimem_flash_ll.h b/components/hal/esp32h21/include/hal/spimem_flash_ll.h index 0eb26858c8..875f784ff5 100644 --- a/components/hal/esp32h21/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32h21/include/hal/spimem_flash_ll.h @@ -242,13 +242,14 @@ static inline void spimem_flash_set_cs_hold_delay(spi_mem_dev_t *dev, uint32_t c * Initialize auto wait idle mode * * @param dev Beginning address of the peripheral registers. - * @param auto_waiti Enable/disable auto wait-idle function + * @param per_waiti Enable wait-idle with time delay function after resume. + * @param pes_waiti Enable wait-idle with time delay function after suspend. */ -static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti) +static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool per_waiti, bool pes_waiti) { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05); - dev->flash_sus_ctrl.flash_per_wait_en = auto_waiti; - dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti; + dev->flash_sus_ctrl.flash_per_wait_en = per_waiti; + dev->flash_sus_ctrl.flash_pes_wait_en = pes_waiti; } /** @@ -474,27 +475,6 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i dev->ctrl.val = ctrl.val; } -__attribute__((always_inline)) -static inline void spimem_flash_ll_set_clock_source(soc_periph_mspi_clk_src_t clk_src) -{ - switch (clk_src) { - case MSPI_CLK_SRC_XTAL: - PCR.mspi_conf.mspi_clk_sel = 0; - break; - case MSPI_CLK_SRC_RC_FAST: - PCR.mspi_conf.mspi_clk_sel = 1; - break; - case MSPI_CLK_SRC_PLL_F64M: - PCR.mspi_conf.mspi_clk_sel = 2; - break; - case MSPI_CLK_SRC_PLL_F48M: - PCR.mspi_conf.mspi_clk_sel = 3; - break; - default: - HAL_ASSERT(false); - } -} - /** * Set clock frequency to work at. * diff --git a/components/heap/port/esp32h21/memory_layout.c b/components/heap/port/esp32h21/memory_layout.c index e69de29bb2..d2105c1dd1 100644 --- a/components/heap/port/esp32h21/memory_layout.c +++ b/components/heap/port/esp32h21/memory_layout.c @@ -0,0 +1,103 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "esp_attr.h" +#include "sdkconfig.h" +#include "soc/soc.h" +#include "heap_memory_layout.h" +#include "esp_heap_caps.h" + +//TODO: [ESP32H21] IDF-11525 + +/** + * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. + * Each type of memory map consists of one or more regions in the address space. + * Each type contains an array of prioritized capabilities. + * Types with later entries are only taken if earlier ones can't fulfill the memory request. + * + * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory. + * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM. + * - Most other malloc caps only fit in one region anyway. + * + */ +/* Index of memory in `soc_memory_types[]` */ +enum { + SOC_MEMORY_TYPE_RAM = 0, + SOC_MEMORY_TYPE_RTCRAM = 1, + SOC_MEMORY_TYPE_NUM, +}; + +/* COMMON_CAPS is the set of attributes common to all types of memory on this chip */ +#ifdef CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT +#define ESP32H21_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT) +#else +#define ESP32H21_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC) +#endif + +/** + * Defined the attributes and allocation priority of each memory on the chip, + * The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first, + * if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching + * in turn to continue matching. + */ +const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { + /* Mem Type Name High Priority Matching Medium Priority Matching Low Priority Matching */ + [SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32H21_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }}, + [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, ESP32H21_MEM_COMMON_CAPS, 0 }}, +}; + +const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); + +/** + * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type. + * + * @note Because of requirements in the coalescing code which merges adjacent regions, + * this list should always be sorted from low to high by start address. + * + */ + +/** + * Register the shared buffer area of the last memory block into the heap during heap initialization + */ +#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) + +const soc_memory_region_t soc_memory_regions[] = { + { 0x40800000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level 0 + { 0x40810000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40810000, false}, //D/IRAM level 1 + { 0x40820000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40820000, false}, //D/IRAM level 2 + { 0x40830000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40830000, false}, //D/IRAM level 3 + { 0x40840000, APP_USABLE_DRAM_END-0x40840000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level 4 + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level 4 +#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP + { 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory +#endif +}; + +const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); + + +extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; +extern int _rtc_reserved_start, _rtc_reserved_end; + +/** + * Reserved memory regions. + * These are removed from the soc_memory_regions array when heaps are created. + * + */ + +// Static data region. DRAM used by data+bss and possibly rodata +SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); + +// Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips +SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code); + +#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP +SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data); +#endif + +SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data); diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index 930f0cc82b..ffe58f6947 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -195,10 +195,6 @@ config SOC_DS_KEY_CHECK_MAX_WAIT_US int default 1100 -config SOC_AHB_GDMA_VERSION - int - default 1 - config SOC_GDMA_NUM_GROUPS_MAX int default 1 @@ -507,10 +503,6 @@ config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK bool default y -config SOC_EFUSE_ECDSA_USE_HARDWARE_K - bool - default y - config SOC_EFUSE_ECDSA_KEY bool default y diff --git a/components/soc/esp32h21/include/soc/clk_tree_defs.h b/components/soc/esp32h21/include/soc/clk_tree_defs.h index cf93f78736..2fd998c947 100644 --- a/components/soc/esp32h21/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h21/include/soc/clk_tree_defs.h @@ -230,23 +230,6 @@ typedef enum { MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL as the default clock choice */ } soc_periph_mwdt_clk_src_t; -//////////////////////////////////////////////////MSPI/////////////////////////////////////////////////////////////////// -/** - * @brief Array initializer for all supported clock sources of MSPI digital controller - */ -#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_PLL_F48M} -/** - * @brief MSPI digital controller clock source - */ -typedef enum { - MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - MSPI_CLK_SRC_PLL_F64M = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the source clock */ - MSPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */ - MSPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the default clock choice */ - MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ -} soc_periph_mspi_clk_src_t; - //////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// typedef enum { CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */ diff --git a/components/soc/esp32h21/include/soc/soc.h b/components/soc/esp32h21/include/soc/soc.h index f68c567545..3456ea4334 100644 --- a/components/soc/esp32h21/include/soc/soc.h +++ b/components/soc/esp32h21/include/soc/soc.h @@ -19,10 +19,11 @@ // TODO: IDF-11856 #define DR_REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) #define DR_REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) +#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) #define DR_REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) #define DR_UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) #define DR_REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H21 -#define DR_REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define DR_REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i)*0x1000) #define DR_REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) #define DR_REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI #define DR_REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000) diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 8264a000c5..2f5f4bbe30 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -176,7 +176,7 @@ #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) /*-------------------------- GDMA CAPS -------------------------------------*/ -#define SOC_AHB_GDMA_VERSION 1U +// #define SOC_AHB_GDMA_VERSION 1U #define SOC_GDMA_NUM_GROUPS_MAX 1U #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 // #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule @@ -459,7 +459,7 @@ #define SOC_EFUSE_SOFT_DIS_JTAG 1 #define SOC_EFUSE_DIS_ICACHE 1 #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES and ECDSA key purposes not supported for this block -#define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA +// #define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA #define SOC_EFUSE_ECDSA_KEY 1 /*-------------------------- Secure Boot CAPS----------------------------*/ diff --git a/components/soc/esp32h21/include/soc/spi_pins.h b/components/soc/esp32h21/include/soc/spi_pins.h index 661ef589ad..631b645227 100644 --- a/components/soc/esp32h21/include/soc/spi_pins.h +++ b/components/soc/esp32h21/include/soc/spi_pins.h @@ -9,20 +9,20 @@ // MSPI IOMUX PINs #define MSPI_FUNC_NUM 0 -#define MSPI_IOMUX_PIN_NUM_HD 18 -#define MSPI_IOMUX_PIN_NUM_WP 17 -#define MSPI_IOMUX_PIN_NUM_CS0 15 -#define MSPI_IOMUX_PIN_NUM_CLK 19 -#define MSPI_IOMUX_PIN_NUM_MOSI 20 -#define MSPI_IOMUX_PIN_NUM_MISO 16 +#define MSPI_IOMUX_PIN_NUM_HD 23 +#define MSPI_IOMUX_PIN_NUM_WP 22 +#define MSPI_IOMUX_PIN_NUM_CS0 20 +#define MSPI_IOMUX_PIN_NUM_CLK 24 +#define MSPI_IOMUX_PIN_NUM_MOSI 25 +#define MSPI_IOMUX_PIN_NUM_MISO 21 // GPSPI2 IOMUX PINs #define SPI2_FUNC_NUM 2 -#define SPI2_IOMUX_PIN_NUM_MISO 0 -#define SPI2_IOMUX_PIN_NUM_HD 3 -#define SPI2_IOMUX_PIN_NUM_WP 2 -#define SPI2_IOMUX_PIN_NUM_CLK 4 -#define SPI2_IOMUX_PIN_NUM_MOSI 5 -#define SPI2_IOMUX_PIN_NUM_CS 1 +#define SPI2_IOMUX_PIN_NUM_MISO 4 +#define SPI2_IOMUX_PIN_NUM_HD 1 +#define SPI2_IOMUX_PIN_NUM_WP 0 +#define SPI2_IOMUX_PIN_NUM_CLK 2 +#define SPI2_IOMUX_PIN_NUM_MOSI 3 +#define SPI2_IOMUX_PIN_NUM_CS 12 #endif diff --git a/components/soc/esp32h21/register/soc/gpio_struct.h b/components/soc/esp32h21/register/soc/gpio_struct.h index 17326f7e68..5d1d7b88e5 100644 --- a/components/soc/esp32h21/register/soc/gpio_struct.h +++ b/components/soc/esp32h21/register/soc/gpio_struct.h @@ -247,6 +247,7 @@ typedef union { uint32_t val; } gpio_pinn_reg_t; +/** Group: Input Configuration Registers */ /** Type of func0_in_sel_cfg register * GPIO input function configuration register */ @@ -256,2089 +257,19 @@ typedef union { * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always * high level. s=0x30: set this port always low level. */ - uint32_t func0_in_sel:6; + uint32_t func_in_sel:6; /** func0_in_inv_sel : R/W; bitpos: [6]; default: 0; * set this bit to invert input signal. 1:invert. 0:not invert. */ - uint32_t func0_in_inv_sel:1; + uint32_t func_in_inv_sel:1; /** sig0_in_sel : R/W; bitpos: [7]; default: 0; * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ - uint32_t sig0_in_sel:1; + uint32_t sig_in_sel:1; uint32_t reserved_8:24; }; uint32_t val; -} gpio_func0_in_sel_cfg_reg_t; - -/** Type of func6_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func6_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func6_in_sel:6; - /** func6_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func6_in_inv_sel:1; - /** sig6_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig6_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func6_in_sel_cfg_reg_t; - -/** Type of func7_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func7_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func7_in_sel:6; - /** func7_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func7_in_inv_sel:1; - /** sig7_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig7_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func7_in_sel_cfg_reg_t; - -/** Type of func8_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func8_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func8_in_sel:6; - /** func8_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func8_in_inv_sel:1; - /** sig8_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig8_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func8_in_sel_cfg_reg_t; - -/** Type of func9_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func9_in_sel : R/W; bitpos: [5:0]; default: 32; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func9_in_sel:6; - /** func9_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func9_in_inv_sel:1; - /** sig9_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig9_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func9_in_sel_cfg_reg_t; - -/** Type of func10_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func10_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func10_in_sel:6; - /** func10_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func10_in_inv_sel:1; - /** sig10_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig10_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func10_in_sel_cfg_reg_t; - -/** Type of func11_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func11_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func11_in_sel:6; - /** func11_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func11_in_inv_sel:1; - /** sig11_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig11_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func11_in_sel_cfg_reg_t; - -/** Type of func12_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func12_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func12_in_sel:6; - /** func12_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func12_in_inv_sel:1; - /** sig12_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig12_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func12_in_sel_cfg_reg_t; - -/** Type of func13_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func13_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func13_in_sel:6; - /** func13_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func13_in_inv_sel:1; - /** sig13_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig13_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func13_in_sel_cfg_reg_t; - -/** Type of func14_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func14_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func14_in_sel:6; - /** func14_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func14_in_inv_sel:1; - /** sig14_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig14_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func14_in_sel_cfg_reg_t; - -/** Type of func15_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func15_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func15_in_sel:6; - /** func15_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func15_in_inv_sel:1; - /** sig15_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig15_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func15_in_sel_cfg_reg_t; - -/** Type of func16_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func16_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func16_in_sel:6; - /** func16_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func16_in_inv_sel:1; - /** sig16_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig16_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func16_in_sel_cfg_reg_t; - -/** Type of func17_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func17_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func17_in_sel:6; - /** func17_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func17_in_inv_sel:1; - /** sig17_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig17_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func17_in_sel_cfg_reg_t; - -/** Type of func19_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func19_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func19_in_sel:6; - /** func19_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func19_in_inv_sel:1; - /** sig19_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig19_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func19_in_sel_cfg_reg_t; - -/** Type of func28_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func28_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func28_in_sel:6; - /** func28_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func28_in_inv_sel:1; - /** sig28_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig28_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func28_in_sel_cfg_reg_t; - -/** Type of func29_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func29_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func29_in_sel:6; - /** func29_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func29_in_inv_sel:1; - /** sig29_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig29_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func29_in_sel_cfg_reg_t; - -/** Type of func30_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func30_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func30_in_sel:6; - /** func30_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func30_in_inv_sel:1; - /** sig30_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig30_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func30_in_sel_cfg_reg_t; - -/** Type of func31_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func31_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func31_in_sel:6; - /** func31_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func31_in_inv_sel:1; - /** sig31_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig31_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func31_in_sel_cfg_reg_t; - -/** Type of func32_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func32_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func32_in_sel:6; - /** func32_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func32_in_inv_sel:1; - /** sig32_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig32_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func32_in_sel_cfg_reg_t; - -/** Type of func33_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func33_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func33_in_sel:6; - /** func33_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func33_in_inv_sel:1; - /** sig33_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig33_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func33_in_sel_cfg_reg_t; - -/** Type of func34_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func34_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func34_in_sel:6; - /** func34_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func34_in_inv_sel:1; - /** sig34_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig34_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func34_in_sel_cfg_reg_t; - -/** Type of func35_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func35_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func35_in_sel:6; - /** func35_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func35_in_inv_sel:1; - /** sig35_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig35_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func35_in_sel_cfg_reg_t; - -/** Type of func40_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func40_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func40_in_sel:6; - /** func40_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func40_in_inv_sel:1; - /** sig40_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig40_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func40_in_sel_cfg_reg_t; - -/** Type of func41_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func41_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func41_in_sel:6; - /** func41_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func41_in_inv_sel:1; - /** sig41_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig41_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func41_in_sel_cfg_reg_t; - -/** Type of func42_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func42_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func42_in_sel:6; - /** func42_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func42_in_inv_sel:1; - /** sig42_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig42_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func42_in_sel_cfg_reg_t; - -/** Type of func45_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func45_in_sel : R/W; bitpos: [5:0]; default: 32; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func45_in_sel:6; - /** func45_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func45_in_inv_sel:1; - /** sig45_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig45_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func45_in_sel_cfg_reg_t; - -/** Type of func46_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func46_in_sel : R/W; bitpos: [5:0]; default: 32; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func46_in_sel:6; - /** func46_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func46_in_inv_sel:1; - /** sig46_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig46_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func46_in_sel_cfg_reg_t; - -/** Type of func47_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func47_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func47_in_sel:6; - /** func47_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func47_in_inv_sel:1; - /** sig47_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig47_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func47_in_sel_cfg_reg_t; - -/** Type of func48_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func48_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func48_in_sel:6; - /** func48_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func48_in_inv_sel:1; - /** sig48_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig48_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func48_in_sel_cfg_reg_t; - -/** Type of func49_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func49_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func49_in_sel:6; - /** func49_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func49_in_inv_sel:1; - /** sig49_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig49_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func49_in_sel_cfg_reg_t; - -/** Type of func50_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func50_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func50_in_sel:6; - /** func50_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func50_in_inv_sel:1; - /** sig50_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig50_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func50_in_sel_cfg_reg_t; - -/** Type of func51_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func51_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func51_in_sel:6; - /** func51_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func51_in_inv_sel:1; - /** sig51_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig51_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func51_in_sel_cfg_reg_t; - -/** Type of func52_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func52_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func52_in_sel:6; - /** func52_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func52_in_inv_sel:1; - /** sig52_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig52_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func52_in_sel_cfg_reg_t; - -/** Type of func53_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func53_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func53_in_sel:6; - /** func53_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func53_in_inv_sel:1; - /** sig53_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig53_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func53_in_sel_cfg_reg_t; - -/** Type of func54_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func54_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func54_in_sel:6; - /** func54_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func54_in_inv_sel:1; - /** sig54_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig54_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func54_in_sel_cfg_reg_t; - -/** Type of func55_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func55_in_sel : R/W; bitpos: [5:0]; default: 32; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func55_in_sel:6; - /** func55_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func55_in_inv_sel:1; - /** sig55_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig55_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func55_in_sel_cfg_reg_t; - -/** Type of func56_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func56_in_sel : R/W; bitpos: [5:0]; default: 32; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func56_in_sel:6; - /** func56_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func56_in_inv_sel:1; - /** sig56_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig56_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func56_in_sel_cfg_reg_t; - -/** Type of func63_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func63_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func63_in_sel:6; - /** func63_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func63_in_inv_sel:1; - /** sig63_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig63_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func63_in_sel_cfg_reg_t; - -/** Type of func64_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func64_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func64_in_sel:6; - /** func64_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func64_in_inv_sel:1; - /** sig64_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig64_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func64_in_sel_cfg_reg_t; - -/** Type of func65_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func65_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func65_in_sel:6; - /** func65_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func65_in_inv_sel:1; - /** sig65_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig65_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func65_in_sel_cfg_reg_t; - -/** Type of func66_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func66_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func66_in_sel:6; - /** func66_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func66_in_inv_sel:1; - /** sig66_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig66_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func66_in_sel_cfg_reg_t; - -/** Type of func67_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func67_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func67_in_sel:6; - /** func67_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func67_in_inv_sel:1; - /** sig67_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig67_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func67_in_sel_cfg_reg_t; - -/** Type of func68_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func68_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func68_in_sel:6; - /** func68_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func68_in_inv_sel:1; - /** sig68_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig68_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func68_in_sel_cfg_reg_t; - -/** Type of func69_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func69_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func69_in_sel:6; - /** func69_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func69_in_inv_sel:1; - /** sig69_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig69_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func69_in_sel_cfg_reg_t; - -/** Type of func70_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func70_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func70_in_sel:6; - /** func70_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func70_in_inv_sel:1; - /** sig70_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig70_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func70_in_sel_cfg_reg_t; - -/** Type of func71_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func71_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func71_in_sel:6; - /** func71_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func71_in_inv_sel:1; - /** sig71_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig71_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func71_in_sel_cfg_reg_t; - -/** Type of func72_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func72_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func72_in_sel:6; - /** func72_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func72_in_inv_sel:1; - /** sig72_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig72_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func72_in_sel_cfg_reg_t; - -/** Type of func73_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func73_in_sel : R/W; bitpos: [5:0]; default: 32; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func73_in_sel:6; - /** func73_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func73_in_inv_sel:1; - /** sig73_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig73_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func73_in_sel_cfg_reg_t; - -/** Type of func77_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func77_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func77_in_sel:6; - /** func77_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func77_in_inv_sel:1; - /** sig77_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig77_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func77_in_sel_cfg_reg_t; - -/** Type of func78_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func78_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func78_in_sel:6; - /** func78_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func78_in_inv_sel:1; - /** sig78_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig78_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func78_in_sel_cfg_reg_t; - -/** Type of func79_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func79_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func79_in_sel:6; - /** func79_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func79_in_inv_sel:1; - /** sig79_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig79_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func79_in_sel_cfg_reg_t; - -/** Type of func80_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func80_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func80_in_sel:6; - /** func80_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func80_in_inv_sel:1; - /** sig80_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig80_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func80_in_sel_cfg_reg_t; - -/** Type of func81_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func81_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func81_in_sel:6; - /** func81_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func81_in_inv_sel:1; - /** sig81_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig81_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func81_in_sel_cfg_reg_t; - -/** Type of func82_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func82_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func82_in_sel:6; - /** func82_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func82_in_inv_sel:1; - /** sig82_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig82_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func82_in_sel_cfg_reg_t; - -/** Type of func87_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func87_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func87_in_sel:6; - /** func87_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func87_in_inv_sel:1; - /** sig87_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig87_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func87_in_sel_cfg_reg_t; - -/** Type of func88_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func88_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func88_in_sel:6; - /** func88_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func88_in_inv_sel:1; - /** sig88_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig88_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func88_in_sel_cfg_reg_t; - -/** Type of func89_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func89_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func89_in_sel:6; - /** func89_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func89_in_inv_sel:1; - /** sig89_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig89_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func89_in_sel_cfg_reg_t; - -/** Type of func90_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func90_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func90_in_sel:6; - /** func90_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func90_in_inv_sel:1; - /** sig90_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig90_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func90_in_sel_cfg_reg_t; - -/** Type of func91_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func91_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func91_in_sel:6; - /** func91_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func91_in_inv_sel:1; - /** sig91_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig91_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func91_in_sel_cfg_reg_t; - -/** Type of func92_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func92_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func92_in_sel:6; - /** func92_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func92_in_inv_sel:1; - /** sig92_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig92_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func92_in_sel_cfg_reg_t; - -/** Type of func93_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func93_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func93_in_sel:6; - /** func93_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func93_in_inv_sel:1; - /** sig93_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig93_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func93_in_sel_cfg_reg_t; - -/** Type of func94_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func94_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func94_in_sel:6; - /** func94_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func94_in_inv_sel:1; - /** sig94_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig94_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func94_in_sel_cfg_reg_t; - -/** Type of func95_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func95_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func95_in_sel:6; - /** func95_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func95_in_inv_sel:1; - /** sig95_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig95_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func95_in_sel_cfg_reg_t; - -/** Type of func97_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func97_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func97_in_sel:6; - /** func97_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func97_in_inv_sel:1; - /** sig97_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig97_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func97_in_sel_cfg_reg_t; - -/** Type of func98_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func98_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func98_in_sel:6; - /** func98_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func98_in_inv_sel:1; - /** sig98_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig98_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func98_in_sel_cfg_reg_t; - -/** Type of func99_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func99_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func99_in_sel:6; - /** func99_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func99_in_inv_sel:1; - /** sig99_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig99_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func99_in_sel_cfg_reg_t; - -/** Type of func100_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func100_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func100_in_sel:6; - /** func100_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func100_in_inv_sel:1; - /** sig100_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig100_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func100_in_sel_cfg_reg_t; - -/** Type of func101_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func101_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func101_in_sel:6; - /** func101_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func101_in_inv_sel:1; - /** sig101_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig101_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func101_in_sel_cfg_reg_t; - -/** Type of func102_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func102_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func102_in_sel:6; - /** func102_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func102_in_inv_sel:1; - /** sig102_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig102_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func102_in_sel_cfg_reg_t; - -/** Type of func103_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func103_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func103_in_sel:6; - /** func103_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func103_in_inv_sel:1; - /** sig103_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig103_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func103_in_sel_cfg_reg_t; - -/** Type of func104_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func104_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func104_in_sel:6; - /** func104_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func104_in_inv_sel:1; - /** sig104_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig104_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func104_in_sel_cfg_reg_t; - -/** Type of func105_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func105_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func105_in_sel:6; - /** func105_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func105_in_inv_sel:1; - /** sig105_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig105_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func105_in_sel_cfg_reg_t; - -/** Type of func106_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func106_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func106_in_sel:6; - /** func106_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func106_in_inv_sel:1; - /** sig106_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig106_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func106_in_sel_cfg_reg_t; - -/** Type of func107_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func107_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func107_in_sel:6; - /** func107_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func107_in_inv_sel:1; - /** sig107_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig107_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func107_in_sel_cfg_reg_t; - -/** Type of func108_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func108_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func108_in_sel:6; - /** func108_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func108_in_inv_sel:1; - /** sig108_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig108_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func108_in_sel_cfg_reg_t; - -/** Type of func109_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func109_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func109_in_sel:6; - /** func109_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func109_in_inv_sel:1; - /** sig109_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig109_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func109_in_sel_cfg_reg_t; - -/** Type of func110_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func110_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func110_in_sel:6; - /** func110_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func110_in_inv_sel:1; - /** sig110_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig110_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func110_in_sel_cfg_reg_t; - -/** Type of func111_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func111_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func111_in_sel:6; - /** func111_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func111_in_inv_sel:1; - /** sig111_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig111_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func111_in_sel_cfg_reg_t; - -/** Type of func112_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func112_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func112_in_sel:6; - /** func112_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func112_in_inv_sel:1; - /** sig112_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig112_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func112_in_sel_cfg_reg_t; - -/** Type of func113_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func113_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func113_in_sel:6; - /** func113_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func113_in_inv_sel:1; - /** sig113_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig113_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func113_in_sel_cfg_reg_t; - -/** Type of func114_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func114_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func114_in_sel:6; - /** func114_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func114_in_inv_sel:1; - /** sig114_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig114_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func114_in_sel_cfg_reg_t; - -/** Type of func115_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func115_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func115_in_sel:6; - /** func115_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func115_in_inv_sel:1; - /** sig115_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig115_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func115_in_sel_cfg_reg_t; - -/** Type of func116_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func116_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func116_in_sel:6; - /** func116_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func116_in_inv_sel:1; - /** sig116_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig116_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func116_in_sel_cfg_reg_t; - -/** Type of func117_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func117_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func117_in_sel:6; - /** func117_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func117_in_inv_sel:1; - /** sig117_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig117_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func117_in_sel_cfg_reg_t; - -/** Type of func118_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func118_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func118_in_sel:6; - /** func118_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func118_in_inv_sel:1; - /** sig118_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig118_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func118_in_sel_cfg_reg_t; - -/** Type of func119_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func119_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func119_in_sel:6; - /** func119_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func119_in_inv_sel:1; - /** sig119_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig119_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func119_in_sel_cfg_reg_t; - -/** Type of func120_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func120_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func120_in_sel:6; - /** func120_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func120_in_inv_sel:1; - /** sig120_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig120_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func120_in_sel_cfg_reg_t; - -/** Type of func121_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func121_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func121_in_sel:6; - /** func121_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func121_in_inv_sel:1; - /** sig121_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig121_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func121_in_sel_cfg_reg_t; - -/** Type of func122_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func122_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func122_in_sel:6; - /** func122_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func122_in_inv_sel:1; - /** sig122_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig122_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func122_in_sel_cfg_reg_t; - -/** Type of func123_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func123_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func123_in_sel:6; - /** func123_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func123_in_inv_sel:1; - /** sig123_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig123_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func123_in_sel_cfg_reg_t; - -/** Type of func124_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func124_in_sel : R/W; bitpos: [5:0]; default: 48; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x20: set this port always - * high level. s=0x30: set this port always low level. - */ - uint32_t func124_in_sel:6; - /** func124_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func124_in_inv_sel:1; - /** sig124_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig124_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func124_in_sel_cfg_reg_t; +} gpio_func_in_sel_cfg_reg_t; /** Type of funcn_out_sel_cfg register * GPIO output function select register @@ -2421,107 +352,8 @@ typedef struct { uint32_t reserved_0c8[3]; volatile gpio_pinn_reg_t pinn[30]; uint32_t reserved_14c[98]; - volatile gpio_func0_in_sel_cfg_reg_t func0_in_sel_cfg; - uint32_t reserved_2d8[5]; - volatile gpio_func6_in_sel_cfg_reg_t func6_in_sel_cfg; - volatile gpio_func7_in_sel_cfg_reg_t func7_in_sel_cfg; - volatile gpio_func8_in_sel_cfg_reg_t func8_in_sel_cfg; - volatile gpio_func9_in_sel_cfg_reg_t func9_in_sel_cfg; - volatile gpio_func10_in_sel_cfg_reg_t func10_in_sel_cfg; - volatile gpio_func11_in_sel_cfg_reg_t func11_in_sel_cfg; - volatile gpio_func12_in_sel_cfg_reg_t func12_in_sel_cfg; - volatile gpio_func13_in_sel_cfg_reg_t func13_in_sel_cfg; - volatile gpio_func14_in_sel_cfg_reg_t func14_in_sel_cfg; - volatile gpio_func15_in_sel_cfg_reg_t func15_in_sel_cfg; - volatile gpio_func16_in_sel_cfg_reg_t func16_in_sel_cfg; - volatile gpio_func17_in_sel_cfg_reg_t func17_in_sel_cfg; - uint32_t reserved_31c; - volatile gpio_func19_in_sel_cfg_reg_t func19_in_sel_cfg; - uint32_t reserved_324[8]; - volatile gpio_func28_in_sel_cfg_reg_t func28_in_sel_cfg; - volatile gpio_func29_in_sel_cfg_reg_t func29_in_sel_cfg; - volatile gpio_func30_in_sel_cfg_reg_t func30_in_sel_cfg; - volatile gpio_func31_in_sel_cfg_reg_t func31_in_sel_cfg; - volatile gpio_func32_in_sel_cfg_reg_t func32_in_sel_cfg; - volatile gpio_func33_in_sel_cfg_reg_t func33_in_sel_cfg; - volatile gpio_func34_in_sel_cfg_reg_t func34_in_sel_cfg; - volatile gpio_func35_in_sel_cfg_reg_t func35_in_sel_cfg; - uint32_t reserved_364[4]; - volatile gpio_func40_in_sel_cfg_reg_t func40_in_sel_cfg; - volatile gpio_func41_in_sel_cfg_reg_t func41_in_sel_cfg; - volatile gpio_func42_in_sel_cfg_reg_t func42_in_sel_cfg; - uint32_t reserved_380[2]; - volatile gpio_func45_in_sel_cfg_reg_t func45_in_sel_cfg; - volatile gpio_func46_in_sel_cfg_reg_t func46_in_sel_cfg; - volatile gpio_func47_in_sel_cfg_reg_t func47_in_sel_cfg; - volatile gpio_func48_in_sel_cfg_reg_t func48_in_sel_cfg; - volatile gpio_func49_in_sel_cfg_reg_t func49_in_sel_cfg; - volatile gpio_func50_in_sel_cfg_reg_t func50_in_sel_cfg; - volatile gpio_func51_in_sel_cfg_reg_t func51_in_sel_cfg; - volatile gpio_func52_in_sel_cfg_reg_t func52_in_sel_cfg; - volatile gpio_func53_in_sel_cfg_reg_t func53_in_sel_cfg; - volatile gpio_func54_in_sel_cfg_reg_t func54_in_sel_cfg; - volatile gpio_func55_in_sel_cfg_reg_t func55_in_sel_cfg; - volatile gpio_func56_in_sel_cfg_reg_t func56_in_sel_cfg; - uint32_t reserved_3b8[6]; - volatile gpio_func63_in_sel_cfg_reg_t func63_in_sel_cfg; - volatile gpio_func64_in_sel_cfg_reg_t func64_in_sel_cfg; - volatile gpio_func65_in_sel_cfg_reg_t func65_in_sel_cfg; - volatile gpio_func66_in_sel_cfg_reg_t func66_in_sel_cfg; - volatile gpio_func67_in_sel_cfg_reg_t func67_in_sel_cfg; - volatile gpio_func68_in_sel_cfg_reg_t func68_in_sel_cfg; - volatile gpio_func69_in_sel_cfg_reg_t func69_in_sel_cfg; - volatile gpio_func70_in_sel_cfg_reg_t func70_in_sel_cfg; - volatile gpio_func71_in_sel_cfg_reg_t func71_in_sel_cfg; - volatile gpio_func72_in_sel_cfg_reg_t func72_in_sel_cfg; - volatile gpio_func73_in_sel_cfg_reg_t func73_in_sel_cfg; - uint32_t reserved_3fc[3]; - volatile gpio_func77_in_sel_cfg_reg_t func77_in_sel_cfg; - volatile gpio_func78_in_sel_cfg_reg_t func78_in_sel_cfg; - volatile gpio_func79_in_sel_cfg_reg_t func79_in_sel_cfg; - volatile gpio_func80_in_sel_cfg_reg_t func80_in_sel_cfg; - volatile gpio_func81_in_sel_cfg_reg_t func81_in_sel_cfg; - volatile gpio_func82_in_sel_cfg_reg_t func82_in_sel_cfg; - uint32_t reserved_420[4]; - volatile gpio_func87_in_sel_cfg_reg_t func87_in_sel_cfg; - volatile gpio_func88_in_sel_cfg_reg_t func88_in_sel_cfg; - volatile gpio_func89_in_sel_cfg_reg_t func89_in_sel_cfg; - volatile gpio_func90_in_sel_cfg_reg_t func90_in_sel_cfg; - volatile gpio_func91_in_sel_cfg_reg_t func91_in_sel_cfg; - volatile gpio_func92_in_sel_cfg_reg_t func92_in_sel_cfg; - volatile gpio_func93_in_sel_cfg_reg_t func93_in_sel_cfg; - volatile gpio_func94_in_sel_cfg_reg_t func94_in_sel_cfg; - volatile gpio_func95_in_sel_cfg_reg_t func95_in_sel_cfg; - uint32_t reserved_454; - volatile gpio_func97_in_sel_cfg_reg_t func97_in_sel_cfg; - volatile gpio_func98_in_sel_cfg_reg_t func98_in_sel_cfg; - volatile gpio_func99_in_sel_cfg_reg_t func99_in_sel_cfg; - volatile gpio_func100_in_sel_cfg_reg_t func100_in_sel_cfg; - volatile gpio_func101_in_sel_cfg_reg_t func101_in_sel_cfg; - volatile gpio_func102_in_sel_cfg_reg_t func102_in_sel_cfg; - volatile gpio_func103_in_sel_cfg_reg_t func103_in_sel_cfg; - volatile gpio_func104_in_sel_cfg_reg_t func104_in_sel_cfg; - volatile gpio_func105_in_sel_cfg_reg_t func105_in_sel_cfg; - volatile gpio_func106_in_sel_cfg_reg_t func106_in_sel_cfg; - volatile gpio_func107_in_sel_cfg_reg_t func107_in_sel_cfg; - volatile gpio_func108_in_sel_cfg_reg_t func108_in_sel_cfg; - volatile gpio_func109_in_sel_cfg_reg_t func109_in_sel_cfg; - volatile gpio_func110_in_sel_cfg_reg_t func110_in_sel_cfg; - volatile gpio_func111_in_sel_cfg_reg_t func111_in_sel_cfg; - volatile gpio_func112_in_sel_cfg_reg_t func112_in_sel_cfg; - volatile gpio_func113_in_sel_cfg_reg_t func113_in_sel_cfg; - volatile gpio_func114_in_sel_cfg_reg_t func114_in_sel_cfg; - volatile gpio_func115_in_sel_cfg_reg_t func115_in_sel_cfg; - volatile gpio_func116_in_sel_cfg_reg_t func116_in_sel_cfg; - volatile gpio_func117_in_sel_cfg_reg_t func117_in_sel_cfg; - volatile gpio_func118_in_sel_cfg_reg_t func118_in_sel_cfg; - volatile gpio_func119_in_sel_cfg_reg_t func119_in_sel_cfg; - volatile gpio_func120_in_sel_cfg_reg_t func120_in_sel_cfg; - volatile gpio_func121_in_sel_cfg_reg_t func121_in_sel_cfg; - volatile gpio_func122_in_sel_cfg_reg_t func122_in_sel_cfg; - volatile gpio_func123_in_sel_cfg_reg_t func123_in_sel_cfg; - volatile gpio_func124_in_sel_cfg_reg_t func124_in_sel_cfg; - uint32_t reserved_4c8[387]; + volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128]; //0-128. reserved: 0-6, 17-19, 19-28, 35-40, 42-45, 56-6, 73-77, 82-87, 95-97, 124-128; + uint32_t reserved_4ac[384]; volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[30]; uint32_t reserved_b4c[171]; volatile gpio_clock_gate_reg_t clock_gate; diff --git a/components/spi_flash/esp32h21/Kconfig.flash_freq b/components/spi_flash/esp32h21/Kconfig.flash_freq new file mode 100644 index 0000000000..f173f3fd88 --- /dev/null +++ b/components/spi_flash/esp32h21/Kconfig.flash_freq @@ -0,0 +1,10 @@ +choice ESPTOOLPY_FLASHFREQ + prompt "Flash SPI speed" + default ESPTOOLPY_FLASHFREQ_32M + config ESPTOOLPY_FLASHFREQ_64M + bool "64 MHz" + config ESPTOOLPY_FLASHFREQ_32M + bool "32 MHz" + config ESPTOOLPY_FLASHFREQ_16M + bool "16 MHz" +endchoice diff --git a/components/spi_flash/esp32h21/Kconfig.soc_caps.in b/components/spi_flash/esp32h21/Kconfig.soc_caps.in new file mode 100644 index 0000000000..87accd576f --- /dev/null +++ b/components/spi_flash/esp32h21/Kconfig.soc_caps.in @@ -0,0 +1,8 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config SPI_FLASH_VENDOR_XMC_SUPPORTED + bool + default y diff --git a/components/spi_flash/esp32h21/flash_vendor_caps.h b/components/spi_flash/esp32h21/flash_vendor_caps.h new file mode 100644 index 0000000000..4c03f22479 --- /dev/null +++ b/components/spi_flash/esp32h21/flash_vendor_caps.h @@ -0,0 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) diff --git a/examples/get-started/.build-test-rules.yml b/examples/get-started/.build-test-rules.yml index 6cd6db80ae..e347d2c03e 100644 --- a/examples/get-started/.build-test-rules.yml +++ b/examples/get-started/.build-test-rules.yml @@ -10,4 +10,4 @@ examples/get-started/blink: examples/get-started/hello_world: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["linux", "esp32c5", "esp32c61"] + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["linux", "esp32h21"] diff --git a/examples/get-started/hello_world/README.md b/examples/get-started/hello_world/README.md index c3e1ee394e..80127a6c91 100644 --- a/examples/get-started/hello_world/README.md +++ b/examples/get-started/hello_world/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | ----- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | ----- | # Hello World Example diff --git a/tools/ci/build_template_app.sh b/tools/ci/build_template_app.sh index 59457ad0cb..6e63fa3583 100755 --- a/tools/ci/build_template_app.sh +++ b/tools/ci/build_template_app.sh @@ -64,7 +64,7 @@ build_stage2() { --size-file size.json \ --keep-going \ --collect-size-info size_info.txt \ - --default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32p4 esp32c61 + --default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32p4 esp32c61 esp32h21 } build_stage1() { @@ -78,7 +78,7 @@ build_stage1() { --build-log ${BUILD_LOG_CMAKE} \ --size-file size.json \ --collect-size-info size_info.txt \ - --default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32p4 esp32c61 + --default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32p4 esp32c61 esp32h21 } # Default arguments diff --git a/tools/test_apps/system/.build-test-rules.yml b/tools/test_apps/system/.build-test-rules.yml index 33b559db90..89062e98d2 100644 --- a/tools/test_apps/system/.build-test-rules.yml +++ b/tools/test_apps/system/.build-test-rules.yml @@ -32,7 +32,7 @@ tools/test_apps/system/esp_intr_dump: tools/test_apps/system/g0_components: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32p4", "esp32c5", "esp32c61"] # preview targets + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32p4", "esp32c5", "esp32c61", "esp32h21"] # preview targets tools/test_apps/system/g1_components: diff --git a/tools/test_apps/system/g0_components/README.md b/tools/test_apps/system/g0_components/README.md index 7bcd7e6211..a901ef30f3 100644 --- a/tools/test_apps/system/g0_components/README.md +++ b/tools/test_apps/system/g0_components/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # "G0"-components-only app