refactor(soc): sort esp32p4 soc headers

components/soc/esp32p4/include/soc/dport_access.h

@@ -9,7 +9,6 @@
 
 #include <stdint.h>
 #include "soc.h"
-#include "uart_reg.h"
 
 #ifdef __cplusplus
 extern "C" {

components/soc/esp32p4/include/soc/reset_reasons.h

@@ -45,7 +45,7 @@ typedef enum {
     RESET_REASON_CORE_USB_JTAG     = 0x16, // USB Serial/JTAG controller's JTAG resets the digital core
     RESET_REASON_CORE_USB_UART     = 0x17, // USB Serial/JTAG controller's UART resets the digital core
     RESET_REASON_CPU_JTAG          = 0x18, // Triggered when a reset command from JTAG is received
-    RESET_REASON_CPU_LOCKUP        = 0x1A, // Triggered when the CPU enters lockup (exception inside the execption handler would cause this)
+    RESET_REASON_CPU_LOCKUP        = 0x1A, // Triggered when the CPU enters lockup (exception inside the exception handler would cause this)
 } soc_reset_reason_t;
 
 

components/soc/esp32p4/include/soc/soc.h

@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 

components/soc/esp32p4/include/soc/usb_dwc_struct.h

@@ -33,7 +33,7 @@ typedef union {
         uint32_t hnpreq: 1;
         uint32_t hstsethnpen: 1;
         uint32_t devhnpen: 1;
-        uint32_t ehen: 1;
+        uint32_t ehen: 1;    // codespell:ignore ehen
         uint32_t reserved_13: 2;
         uint32_t dbncefltrbypass: 1;
         uint32_t conidsts: 1;

components/soc/esp32p4/register/soc/assist_debug_reg.h

@@ -435,7 +435,7 @@ extern "C" {
  */
 #define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
 /** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
- *  core0 sp region configuration regsiter
+ *  core0 sp region configuration register
  */
 #define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
@@ -459,7 +459,7 @@ extern "C" {
  */
 #define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
 /** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
- *  This regsiter stores the PC when trigger stack monitor.
+ *  This register stores the PC when trigger stack monitor.
  */
 #define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
@@ -486,7 +486,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
 
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
- *  record status regsiter
+ *  record status register
  */
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
@@ -498,7 +498,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
 
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
- *  record status regsiter
+ *  record status register
  */
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
@@ -1103,7 +1103,7 @@ extern "C" {
  */
 #define ASSIST_DEBUG_CORE_1_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb8)
 /** ASSIST_DEBUG_CORE_1_SP_MIN : R/W; bitpos: [31:0]; default: 0;
- *  core1 sp region configuration regsiter
+ *  core1 sp region configuration register
  */
 #define ASSIST_DEBUG_CORE_1_SP_MIN    0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_1_SP_MIN_M  (ASSIST_DEBUG_CORE_1_SP_MIN_V << ASSIST_DEBUG_CORE_1_SP_MIN_S)
@@ -1127,7 +1127,7 @@ extern "C" {
  */
 #define ASSIST_DEBUG_CORE_1_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc0)
 /** ASSIST_DEBUG_CORE_1_SP_PC : RO; bitpos: [31:0]; default: 0;
- *  This regsiter stores the PC when trigger stack monitor.
+ *  This register stores the PC when trigger stack monitor.
  */
 #define ASSIST_DEBUG_CORE_1_SP_PC    0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_1_SP_PC_M  (ASSIST_DEBUG_CORE_1_SP_PC_V << ASSIST_DEBUG_CORE_1_SP_PC_S)
@@ -1154,7 +1154,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_S  1
 
 /** ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG register
- *  record status regsiter
+ *  record status register
  */
 #define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc8)
 /** ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
@@ -1166,7 +1166,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S  0
 
 /** ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_REG register
- *  record status regsiter
+ *  record status register
  */
 #define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0xcc)
 /** ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;

components/soc/esp32p4/register/soc/assist_debug_struct.h

@@ -197,7 +197,7 @@ typedef union {
 typedef union {
     struct {
         /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
-         *  core0 sp region configuration regsiter
+         *  core0 sp region configuration register
          */
         uint32_t core_0_sp_min:32;
     };
@@ -223,7 +223,7 @@ typedef union {
 typedef union {
     struct {
         /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
-         *  This regsiter stores the PC when trigger stack monitor.
+         *  This register stores the PC when trigger stack monitor.
          */
         uint32_t core_0_sp_pc:32;
     };
@@ -416,7 +416,7 @@ typedef union {
 typedef union {
     struct {
         /** core_1_sp_min : R/W; bitpos: [31:0]; default: 0;
-         *  core1 sp region configuration regsiter
+         *  core1 sp region configuration register
          */
         uint32_t core_1_sp_min:32;
     };
@@ -442,7 +442,7 @@ typedef union {
 typedef union {
     struct {
         /** core_1_sp_pc : RO; bitpos: [31:0]; default: 0;
-         *  This regsiter stores the PC when trigger stack monitor.
+         *  This register stores the PC when trigger stack monitor.
          */
         uint32_t core_1_sp_pc:32;
     };
@@ -752,7 +752,7 @@ typedef union {
 } assist_debug_core_1_intr_clr_reg_t;
 
 
-/** Group: pc reording configuration register */
+/** Group: pc recording configuration register */
 /** Type of core_0_rcd_en register
  *  record enable configuration register
  */
@@ -790,9 +790,9 @@ typedef union {
 } assist_debug_core_1_rcd_en_reg_t;
 
 
-/** Group: pc reording status register */
+/** Group: pc recording status register */
 /** Type of core_0_rcd_pdebugpc register
- *  record status regsiter
+ *  record status register
  */
 typedef union {
     struct {
@@ -805,7 +805,7 @@ typedef union {
 } assist_debug_core_0_rcd_pdebugpc_reg_t;
 
 /** Type of core_0_rcd_pdebugsp register
- *  record status regsiter
+ *  record status register
  */
 typedef union {
     struct {
@@ -818,7 +818,7 @@ typedef union {
 } assist_debug_core_0_rcd_pdebugsp_reg_t;
 
 /** Type of core_1_rcd_pdebugpc register
- *  record status regsiter
+ *  record status register
  */
 typedef union {
     struct {
@@ -831,7 +831,7 @@ typedef union {
 } assist_debug_core_1_rcd_pdebugpc_reg_t;
 
 /** Type of core_1_rcd_pdebugsp register
- *  record status regsiter
+ *  record status register
  */
 typedef union {
     struct {
@@ -844,7 +844,7 @@ typedef union {
 } assist_debug_core_1_rcd_pdebugsp_reg_t;
 
 
-/** Group: exception monitor regsiter */
+/** Group: exception monitor register */
 /** Type of core_0_iram0_exception_monitor_0 register
  *  exception monitor status register0
  */

components/soc/esp32p4/register/soc/axi_dma_reg.h

@@ -770,7 +770,7 @@ extern "C" {
 #define AXI_DMA_RX_CH_ARB_WEIGH_CH0_V  0x0000000FU
 #define AXI_DMA_RX_CH_ARB_WEIGH_CH0_S  4
 /** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [8]; default: 0;
- *  0: mean not optimazation weight function ,1: mean optimazation
+ *  0: mean not optimization weight function ,1: mean optimization
  */
 #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0    (BIT(8))
 #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S)
@@ -1654,7 +1654,7 @@ extern "C" {
 #define AXI_DMA_RX_CH_ARB_WEIGH_CH1_V  0x0000000FU
 #define AXI_DMA_RX_CH_ARB_WEIGH_CH1_S  4
 /** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [8]; default: 0;
- *  0: mean not optimazation weight function ,1: mean optimazation
+ *  0: mean not optimization weight function ,1: mean optimization
  */
 #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1    (BIT(8))
 #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S)
@@ -2538,7 +2538,7 @@ extern "C" {
 #define AXI_DMA_RX_CH_ARB_WEIGH_CH2_V  0x0000000FU
 #define AXI_DMA_RX_CH_ARB_WEIGH_CH2_S  4
 /** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [8]; default: 0;
- *  0: mean not optimazation weight function ,1: mean optimazation
+ *  0: mean not optimization weight function ,1: mean optimization
  */
 #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2    (BIT(8))
 #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S)
@@ -3384,7 +3384,7 @@ extern "C" {
 #define AXI_DMA_TX_CH_ARB_WEIGH_CH0_V  0x0000000FU
 #define AXI_DMA_TX_CH_ARB_WEIGH_CH0_S  4
 /** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [8]; default: 0;
- *  0: mean not optimazation weight function ,1: mean optimazation
+ *  0: mean not optimization weight function ,1: mean optimization
  */
 #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0    (BIT(8))
 #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S)
@@ -4230,7 +4230,7 @@ extern "C" {
 #define AXI_DMA_TX_CH_ARB_WEIGH_CH1_V  0x0000000FU
 #define AXI_DMA_TX_CH_ARB_WEIGH_CH1_S  4
 /** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [8]; default: 0;
- *  0: mean not optimazation weight function ,1: mean optimazation
+ *  0: mean not optimization weight function ,1: mean optimization
  */
 #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1    (BIT(8))
 #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S)
@@ -5076,7 +5076,7 @@ extern "C" {
 #define AXI_DMA_TX_CH_ARB_WEIGH_CH2_V  0x0000000FU
 #define AXI_DMA_TX_CH_ARB_WEIGH_CH2_S  4
 /** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [8]; default: 0;
- *  0: mean not optimazation weight function ,1: mean optimazation
+ *  0: mean not optimization weight function ,1: mean optimization
  */
 #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2    (BIT(8))
 #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S)
@@ -5490,11 +5490,11 @@ extern "C" {
 #define AXI_DMA_RDN_ECO_LOW_S  0
 
 /** AXI_DMA_WRESP_CNT_REG register
- *  AXI wr responce cnt register.
+ *  AXI wr response cnt register.
  */
 #define AXI_DMA_WRESP_CNT_REG (DR_REG_AXI_DMA_BASE + 0x2b8)
 /** AXI_DMA_WRESP_CNT : RO; bitpos: [3:0]; default: 0;
- *  axi wr responce cnt reg.
+ *  axi wr response cnt reg.
  */
 #define AXI_DMA_WRESP_CNT    0x0000000FU
 #define AXI_DMA_WRESP_CNT_M  (AXI_DMA_WRESP_CNT_V << AXI_DMA_WRESP_CNT_S)
@@ -5502,11 +5502,11 @@ extern "C" {
 #define AXI_DMA_WRESP_CNT_S  0
 
 /** AXI_DMA_RRESP_CNT_REG register
- *  AXI wr responce cnt register.
+ *  AXI wr response cnt register.
  */
 #define AXI_DMA_RRESP_CNT_REG (DR_REG_AXI_DMA_BASE + 0x2bc)
 /** AXI_DMA_RRESP_CNT : RO; bitpos: [3:0]; default: 0;
- *  axi rd responce cnt reg.
+ *  axi rd response cnt reg.
  */
 #define AXI_DMA_RRESP_CNT    0x0000000FU
 #define AXI_DMA_RRESP_CNT_M  (AXI_DMA_RRESP_CNT_V << AXI_DMA_RRESP_CNT_S)

components/soc/esp32p4/register/soc/bitscrambler_reg.h

@@ -216,7 +216,7 @@ extern "C" {
 #define BITSCRAMBLER_TX_COND_MODE_S  4
 /** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
  *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
- *  by reset, 1: fetch by instrutions
+ *  by reset, 1: fetch by instructions
  */
 #define BITSCRAMBLER_TX_FETCH_MODE    (BIT(5))
 #define BITSCRAMBLER_TX_FETCH_MODE_M  (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
@@ -291,7 +291,7 @@ extern "C" {
 #define BITSCRAMBLER_RX_COND_MODE_S  4
 /** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
  *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
- *  by reset, 1: fetch by instrutions
+ *  by reset, 1: fetch by instructions
  */
 #define BITSCRAMBLER_RX_FETCH_MODE    (BIT(5))
 #define BITSCRAMBLER_RX_FETCH_MODE_M  (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)

components/soc/esp32p4/register/soc/bitscrambler_struct.h

@@ -208,7 +208,7 @@ typedef union {
         uint32_t tx_cond_mode:1;
         /** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
          *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
-         *  by reset, 1: fetch by instrutions
+         *  by reset, 1: fetch by instructions
          */
         uint32_t tx_fetch_mode:1;
         /** tx_halt_mode : R/W; bitpos: [6]; default: 0;
@@ -261,7 +261,7 @@ typedef union {
         uint32_t rx_cond_mode:1;
         /** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
          *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
-         *  by reset, 1: fetch by instrutions
+         *  by reset, 1: fetch by instructions
          */
         uint32_t rx_fetch_mode:1;
         /** rx_halt_mode : R/W; bitpos: [6]; default: 0;

components/soc/esp32p4/register/soc/cache_reg.h

@@ -4270,7 +4270,7 @@ extern "C" {
 #define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x258)
 /** CACHE_L1_ICACHE0_UNALLOC_CLR : R/W; bitpos: [0]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request is responded but not completed.
  */
 #define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
 #define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
@@ -4278,7 +4278,7 @@ extern "C" {
 #define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
 /** CACHE_L1_ICACHE1_UNALLOC_CLR : R/W; bitpos: [1]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request is responded but not completed.
  */
 #define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
 #define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
@@ -4300,7 +4300,7 @@ extern "C" {
 #define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
 /** CACHE_L1_DCACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l1 dcache where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request is responded but not completed.
  */
 #define CACHE_L1_DCACHE_UNALLOC_CLR    (BIT(4))
 #define CACHE_L1_DCACHE_UNALLOC_CLR_M  (CACHE_L1_DCACHE_UNALLOC_CLR_V << CACHE_L1_DCACHE_UNALLOC_CLR_S)
@@ -6156,7 +6156,7 @@ extern "C" {
 #define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b8)
 /** CACHE_L2_CACHE_UNALLOC_CLR : R/W; bitpos: [5]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l2 icache where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request is responded but not completed.
  */
 #define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
 #define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)

components/soc/esp32p4/register/soc/ecc_mult_reg.h

@@ -64,7 +64,7 @@ extern "C" {
  */
 #define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
 /** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
+ *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
  *  the caculatrion is done.
  */
 #define ECC_MULT_START    (BIT(0))
@@ -97,7 +97,7 @@ extern "C" {
  *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
  *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
  *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
- *  8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
+ *  8: mod addition. 9. mod subtraction. 10: mod multiplication. 11: mod division.
  */
 #define ECC_MULT_WORK_MODE    0x0000000FU
 #define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)

components/soc/esp32p4/register/soc/ecc_mult_struct.h

@@ -77,7 +77,7 @@ typedef union {
 typedef union {
     struct {
         /** start : R/W/SC; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
+         *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
          *  the caculatrion is done.
          */
         uint32_t start:1;
@@ -98,7 +98,7 @@ typedef union {
          *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
          *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
          *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
-         *  8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
+         *  8: mod addition. 9. mod subtraction. 10: mod multiplication. 11: mod division.
          */
         uint32_t work_mode:4;
         /** security_mode : R/W; bitpos: [8]; default: 0;

components/soc/esp32p4/register/soc/ecdsa_reg.h

@@ -155,7 +155,7 @@ extern "C" {
  */
 #define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
 /** ECDSA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
+ *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
  *  after configuration.
  */
 #define ECDSA_START    (BIT(0))
@@ -243,7 +243,7 @@ extern "C" {
  */
 #define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
 /** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
+ *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
  *  bit will be self-cleared after configuration.
  */
 #define ECDSA_SHA_START    (BIT(0))
@@ -256,7 +256,7 @@ extern "C" {
  */
 #define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
 /** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
+ *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
  *  bit will be self-cleared after configuration.
  */
 #define ECDSA_SHA_CONTINUE    (BIT(0))

components/soc/esp32p4/register/soc/ecdsa_struct.h

@@ -57,7 +57,7 @@ typedef union {
 typedef union {
     struct {
         /** start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
+         *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
          *  after configuration.
          */
         uint32_t start:1;
@@ -228,7 +228,7 @@ typedef union {
 typedef union {
     struct {
         /** sha_start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
+         *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
          *  bit will be self-cleared after configuration.
          */
         uint32_t sha_start:1;
@@ -243,7 +243,7 @@ typedef union {
 typedef union {
     struct {
         /** sha_continue : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
+         *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
          *  bit will be self-cleared after configuration.
          */
         uint32_t sha_continue:1;

components/soc/esp32p4/register/soc/efuse_reg.h

@@ -7,7 +7,7 @@
 
 #include <stdint.h>
 #include "soc/soc.h"
-#include "efuse_defs.h"
+#include "soc/efuse_defs.h"
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32p4/register/soc/gpio_reg.h

@@ -12151,11 +12151,11 @@ extern "C" {
 #define GPIO_SEND_SEQ_S  0
 
 /** GPIO_RECIVE_SEQ_REG register
- *  High speed sdio pad bist recive sequence
+ *  High speed sdio pad bist receive sequence
  */
 #define GPIO_RECIVE_SEQ_REG (DR_REG_GPIO_BASE + 0x71c)
 /** GPIO_RECIVE_SEQ : RO; bitpos: [31:0]; default: 0;
- *  High speed sdio pad bist recive sequence
+ *  High speed sdio pad bist receive sequence
  */
 #define GPIO_RECIVE_SEQ    0xFFFFFFFFU
 #define GPIO_RECIVE_SEQ_M  (GPIO_RECIVE_SEQ_V << GPIO_RECIVE_SEQ_S)

components/soc/esp32p4/register/soc/gpio_struct.h

@@ -580,12 +580,12 @@ typedef union {
 } gpio_send_seq_reg_t;
 
 /** Type of recive_seq register
- *  High speed sdio pad bist recive sequence
+ *  High speed sdio pad bist receive sequence
  */
 typedef union {
     struct {
         /** recive_seq : RO; bitpos: [31:0]; default: 0;
-         *  High speed sdio pad bist recive sequence
+         *  High speed sdio pad bist receive sequence
          */
         uint32_t recive_seq:32;
     };

components/soc/esp32p4/register/soc/hp_system_reg.h

@@ -39,7 +39,7 @@ extern "C" {
  */
 #define HP_SYSTEM_CPU_INT_FROM_CPU_0_REG (DR_REG_HP_SYS_BASE + 0x10)
 /** HP_SYSTEM_CPU_INT_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
- *  set 1 will triger a interrupt
+ *  set 1 will trigger a interrupt
  */
 #define HP_SYSTEM_CPU_INT_FROM_CPU_0    (BIT(0))
 #define HP_SYSTEM_CPU_INT_FROM_CPU_0_M  (HP_SYSTEM_CPU_INT_FROM_CPU_0_V << HP_SYSTEM_CPU_INT_FROM_CPU_0_S)
@@ -51,7 +51,7 @@ extern "C" {
  */
 #define HP_SYSTEM_CPU_INT_FROM_CPU_1_REG (DR_REG_HP_SYS_BASE + 0x14)
 /** HP_SYSTEM_CPU_INT_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
- *  set 1 will triger a interrupt
+ *  set 1 will trigger a interrupt
  */
 #define HP_SYSTEM_CPU_INT_FROM_CPU_1    (BIT(0))
 #define HP_SYSTEM_CPU_INT_FROM_CPU_1_M  (HP_SYSTEM_CPU_INT_FROM_CPU_1_V << HP_SYSTEM_CPU_INT_FROM_CPU_1_S)
@@ -63,7 +63,7 @@ extern "C" {
  */
 #define HP_SYSTEM_CPU_INT_FROM_CPU_2_REG (DR_REG_HP_SYS_BASE + 0x18)
 /** HP_SYSTEM_CPU_INT_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
- *  set 1 will triger a interrupt
+ *  set 1 will trigger a interrupt
  */
 #define HP_SYSTEM_CPU_INT_FROM_CPU_2    (BIT(0))
 #define HP_SYSTEM_CPU_INT_FROM_CPU_2_M  (HP_SYSTEM_CPU_INT_FROM_CPU_2_V << HP_SYSTEM_CPU_INT_FROM_CPU_2_S)
@@ -75,7 +75,7 @@ extern "C" {
  */
 #define HP_SYSTEM_CPU_INT_FROM_CPU_3_REG (DR_REG_HP_SYS_BASE + 0x1c)
 /** HP_SYSTEM_CPU_INT_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
- *  set 1 will triger a interrupt
+ *  set 1 will trigger a interrupt
  */
 #define HP_SYSTEM_CPU_INT_FROM_CPU_3    (BIT(0))
 #define HP_SYSTEM_CPU_INT_FROM_CPU_3_M  (HP_SYSTEM_CPU_INT_FROM_CPU_3_V << HP_SYSTEM_CPU_INT_FROM_CPU_3_S)
@@ -87,7 +87,7 @@ extern "C" {
  */
 #define HP_SYSTEM_CACHE_CLK_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x20)
 /** HP_SYSTEM_REG_L2_CACHE_CLK_ON : R/W; bitpos: [0]; default: 1;
- *  l2 cahce clk enable
+ *  l2 cache clk enable
  */
 #define HP_SYSTEM_REG_L2_CACHE_CLK_ON    (BIT(0))
 #define HP_SYSTEM_REG_L2_CACHE_CLK_ON_M  (HP_SYSTEM_REG_L2_CACHE_CLK_ON_V << HP_SYSTEM_REG_L2_CACHE_CLK_ON_S)
@@ -269,7 +269,7 @@ extern "C" {
  */
 #define HP_SYSTEM_PROBEA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x50)
 /** HP_SYSTEM_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
- *  Tihs field is used to selec probe_group from probe_group0 to probe_group15 for
+ *  This field is used to selec probe_group from probe_group0 to probe_group15 for
  *  module's probe_out[31:0] in a mode
  */
 #define HP_SYSTEM_REG_PROBE_A_MOD_SEL    0x0000FFFFU
@@ -277,21 +277,21 @@ extern "C" {
 #define HP_SYSTEM_REG_PROBE_A_MOD_SEL_V  0x0000FFFFU
 #define HP_SYSTEM_REG_PROBE_A_MOD_SEL_S  0
 /** HP_SYSTEM_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
- *  Tihs field is used to selec module's probe_out[31:0] as probe out in a mode
+ *  This field is used to selec module's probe_out[31:0] as probe out in a mode
  */
 #define HP_SYSTEM_REG_PROBE_A_TOP_SEL    0x000000FFU
 #define HP_SYSTEM_REG_PROBE_A_TOP_SEL_M  (HP_SYSTEM_REG_PROBE_A_TOP_SEL_V << HP_SYSTEM_REG_PROBE_A_TOP_SEL_S)
 #define HP_SYSTEM_REG_PROBE_A_TOP_SEL_V  0x000000FFU
 #define HP_SYSTEM_REG_PROBE_A_TOP_SEL_S  16
 /** HP_SYSTEM_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0;
- *  Tihs field is used to selec probe_out[31:16]
+ *  This field is used to selec probe_out[31:16]
  */
 #define HP_SYSTEM_REG_PROBE_L_SEL    0x00000003U
 #define HP_SYSTEM_REG_PROBE_L_SEL_M  (HP_SYSTEM_REG_PROBE_L_SEL_V << HP_SYSTEM_REG_PROBE_L_SEL_S)
 #define HP_SYSTEM_REG_PROBE_L_SEL_V  0x00000003U
 #define HP_SYSTEM_REG_PROBE_L_SEL_S  24
 /** HP_SYSTEM_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0;
- *  Tihs field is used to selec probe_out[31:16]
+ *  This field is used to selec probe_out[31:16]
  */
 #define HP_SYSTEM_REG_PROBE_H_SEL    0x00000003U
 #define HP_SYSTEM_REG_PROBE_H_SEL_M  (HP_SYSTEM_REG_PROBE_H_SEL_V << HP_SYSTEM_REG_PROBE_H_SEL_S)
@@ -310,7 +310,7 @@ extern "C" {
  */
 #define HP_SYSTEM_PROBEB_CTRL_REG (DR_REG_HP_SYS_BASE + 0x54)
 /** HP_SYSTEM_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
- *  Tihs field is used to selec probe_group from probe_group0 to probe_group15 for
+ *  This field is used to selec probe_group from probe_group0 to probe_group15 for
  *  module's probe_out[31:0] in b mode.
  */
 #define HP_SYSTEM_REG_PROBE_B_MOD_SEL    0x0000FFFFU
@@ -318,7 +318,7 @@ extern "C" {
 #define HP_SYSTEM_REG_PROBE_B_MOD_SEL_V  0x0000FFFFU
 #define HP_SYSTEM_REG_PROBE_B_MOD_SEL_S  0
 /** HP_SYSTEM_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
- *  Tihs field is used to select module's probe_out[31:0]  as probe_out in b mode
+ *  This field is used to select module's probe_out[31:0]  as probe_out in b mode
  */
 #define HP_SYSTEM_REG_PROBE_B_TOP_SEL    0x000000FFU
 #define HP_SYSTEM_REG_PROBE_B_TOP_SEL_M  (HP_SYSTEM_REG_PROBE_B_TOP_SEL_V << HP_SYSTEM_REG_PROBE_B_TOP_SEL_S)
@@ -1069,7 +1069,7 @@ extern "C" {
  */
 #define HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (DR_REG_HP_SYS_BASE + 0x140)
 /** HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL : R/W; bitpos: [3:0]; default: 15;
- *  Set  this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0
+ *  Set  this field to sel peri with DMA RX interface to connect with bitscrambler: 4'h0
  *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
  *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
  *  else : none
@@ -1079,7 +1079,7 @@ extern "C" {
 #define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_V  0x0000000FU
 #define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_S  0
 /** HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL : R/W; bitpos: [7:4]; default: 15;
- *  Set  this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0
+ *  Set  this field to sel peri with DMA TX interface to connect with bitscrambler: 4'h0
  *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
  *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
  *  else : none

components/soc/esp32p4/register/soc/hp_system_struct.h

@@ -48,7 +48,7 @@ typedef union {
 typedef union {
     struct {
         /** cpu_int_from_cpu_0 : R/W; bitpos: [0]; default: 0;
-         *  set 1 will triger a interrupt
+         *  set 1 will trigger a interrupt
          */
         uint32_t cpu_int_from_cpu_0:1;
         uint32_t reserved_1:31;
@@ -64,7 +64,7 @@ typedef union {
 typedef union {
     struct {
         /** cpu_int_from_cpu_1 : R/W; bitpos: [0]; default: 0;
-         *  set 1 will triger a interrupt
+         *  set 1 will trigger a interrupt
          */
         uint32_t cpu_int_from_cpu_1:1;
         uint32_t reserved_1:31;
@@ -80,7 +80,7 @@ typedef union {
 typedef union {
     struct {
         /** cpu_int_from_cpu_2 : R/W; bitpos: [0]; default: 0;
-         *  set 1 will triger a interrupt
+         *  set 1 will trigger a interrupt
          */
         uint32_t cpu_int_from_cpu_2:1;
         uint32_t reserved_1:31;
@@ -96,7 +96,7 @@ typedef union {
 typedef union {
     struct {
         /** cpu_int_from_cpu_3 : R/W; bitpos: [0]; default: 0;
-         *  set 1 will triger a interrupt
+         *  set 1 will trigger a interrupt
          */
         uint32_t cpu_int_from_cpu_3:1;
         uint32_t reserved_1:31;
@@ -112,7 +112,7 @@ typedef union {
 typedef union {
     struct {
         /** reg_l2_cache_clk_on : R/W; bitpos: [0]; default: 1;
-         *  l2 cahce clk enable
+         *  l2 cache clk enable
          */
         uint32_t reg_l2_cache_clk_on:1;
         /** reg_l1_d_cache_clk_on : R/W; bitpos: [1]; default: 1;
@@ -283,20 +283,20 @@ typedef union {
 typedef union {
     struct {
         /** reg_probe_a_mod_sel : R/W; bitpos: [15:0]; default: 0;
-         *  Tihs field is used to selec probe_group from probe_group0 to probe_group15 for
+         *  This field is used to selec probe_group from probe_group0 to probe_group15 for
          *  module's probe_out[31:0] in a mode
          */
         uint32_t reg_probe_a_mod_sel:16;
         /** reg_probe_a_top_sel : R/W; bitpos: [23:16]; default: 0;
-         *  Tihs field is used to selec module's probe_out[31:0] as probe out in a mode
+         *  This field is used to selec module's probe_out[31:0] as probe out in a mode
          */
         uint32_t reg_probe_a_top_sel:8;
         /** reg_probe_l_sel : R/W; bitpos: [25:24]; default: 0;
-         *  Tihs field is used to selec probe_out[31:16]
+         *  This field is used to selec probe_out[31:16]
          */
         uint32_t reg_probe_l_sel:2;
         /** reg_probe_h_sel : R/W; bitpos: [27:26]; default: 0;
-         *  Tihs field is used to selec probe_out[31:16]
+         *  This field is used to selec probe_out[31:16]
          */
         uint32_t reg_probe_h_sel:2;
         /** reg_probe_global_en : R/W; bitpos: [28]; default: 0;
@@ -316,12 +316,12 @@ typedef union {
 typedef union {
     struct {
         /** reg_probe_b_mod_sel : R/W; bitpos: [15:0]; default: 0;
-         *  Tihs field is used to selec probe_group from probe_group0 to probe_group15 for
+         *  This field is used to selec probe_group from probe_group0 to probe_group15 for
          *  module's probe_out[31:0] in b mode.
          */
         uint32_t reg_probe_b_mod_sel:16;
         /** reg_probe_b_top_sel : R/W; bitpos: [23:16]; default: 0;
-         *  Tihs field is used to select module's probe_out[31:0]  as probe_out in b mode
+         *  This field is used to select module's probe_out[31:0]  as probe_out in b mode
          */
         uint32_t reg_probe_b_top_sel:8;
         /** reg_probe_b_en : R/W; bitpos: [24]; default: 0;
@@ -834,7 +834,7 @@ typedef union {
 } hp_system_tcm_rdn_eco_high_reg_t;
 
 
-/** Group: HP GPIO DED HOLD CTRL REG */
+/** Group: HP GPIO DEAD HOLD CTRL REG */
 /** Type of gpio_ded_hold_ctrl register
  *  NA
  */
@@ -1021,14 +1021,14 @@ typedef union {
 typedef union {
     struct {
         /** bitscrambler_peri_rx_sel : R/W; bitpos: [3:0]; default: 15;
-         *  Set  this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0
+         *  Set  this field to sel peri with DMA RX interface to connect with bitscrambler: 4'h0
          *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
          *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
          *  else : none
          */
         uint32_t bitscrambler_peri_rx_sel:4;
         /** bitscrambler_peri_tx_sel : R/W; bitpos: [7:4]; default: 15;
-         *  Set  this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0
+         *  Set  this field to sel peri with DMA TX interface to connect with bitscrambler: 4'h0
          *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
          *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
          *  else : none

components/soc/esp32p4/register/soc/i2s_reg.h

@@ -320,7 +320,7 @@ extern "C" {
 #define I2S_TX_SLAVE_MOD_V  0x00000001U
 #define I2S_TX_SLAVE_MOD_S  3
 /** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
- *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
  */
 #define I2S_TX_STOP_EN    (BIT(4))
 #define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)

components/soc/esp32p4/register/soc/i2s_struct.h

@@ -496,7 +496,7 @@ typedef union {
          */
         uint32_t tx_slave_mod:1;
         /** tx_stop_en : R/W; bitpos: [4]; default: 1;
-         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
          */
         uint32_t tx_stop_en:1;
         /** tx_chan_equal : R/W; bitpos: [5]; default: 0;

components/soc/esp32p4/register/soc/i3c_slv_reg.h

@@ -103,7 +103,7 @@ extern "C" {
 #define I3C_SLV_STNOTSTOP_V  0x00000001U
 #define I3C_SLV_STNOTSTOP_S  0
 /** I3C_SLV_STMSG : RO; bitpos: [1]; default: 0;
- *  Is 1 if this bus Slave is listening to the bus traffic or repsonding, If
+ *  Is 1 if this bus Slave is listening to the bus traffic or responding, If
  *  STNOSTOP=1, then this will be 0 when a non-matching address seen until next
  *  respeated START it STOP.
  */

components/soc/esp32p4/register/soc/i3c_slv_struct.h

@@ -83,7 +83,7 @@ typedef union {
          */
         uint32_t stnotstop:1;
         /** stmsg : RO; bitpos: [1]; default: 0;
-         *  Is 1 if this bus Slave is listening to the bus traffic or repsonding, If
+         *  Is 1 if this bus Slave is listening to the bus traffic or responding, If
          *  STNOSTOP=1, then this will be 0 when a non-matching address seen until next
          *  respeated START it STOP.
          */
@@ -459,10 +459,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** capablities : RO; bitpos: [31:0]; default: 2081684508;
+        /** capabilities : RO; bitpos: [31:0]; default: 2081684508;
          *  NA
          */
-        uint32_t capablities:32;
+        uint32_t capabilities:32;
     };
     uint32_t val;
 } i3c_slv_capabilities_reg_t;

components/soc/esp32p4/register/soc/io_mux_reg.h

@@ -5,7 +5,7 @@
  */
 
 #pragma once
-#include "soc.h"
+#include "soc/soc.h"
 
 /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
 /* Output enable in sleep mode */

components/soc/esp32p4/register/soc/isp_reg.h

@@ -521,56 +521,56 @@ extern "C" {
  */
 #define ISP_BF_GAU0_REG (DR_REG_ISP_BASE + 0x30)
 /** ISP_GAU_TEMPLATE21 : R/W; bitpos: [3:0]; default: 15;
- *  this field configures index 21 of gausian template
+ *  this field configures index 21 of gaussian template
  */
 #define ISP_GAU_TEMPLATE21    0x0000000FU
 #define ISP_GAU_TEMPLATE21_M  (ISP_GAU_TEMPLATE21_V << ISP_GAU_TEMPLATE21_S)
 #define ISP_GAU_TEMPLATE21_V  0x0000000FU
 #define ISP_GAU_TEMPLATE21_S  0
 /** ISP_GAU_TEMPLATE20 : R/W; bitpos: [7:4]; default: 15;
- *  this field configures index 20 of gausian template
+ *  this field configures index 20 of gaussian template
  */
 #define ISP_GAU_TEMPLATE20    0x0000000FU
 #define ISP_GAU_TEMPLATE20_M  (ISP_GAU_TEMPLATE20_V << ISP_GAU_TEMPLATE20_S)
 #define ISP_GAU_TEMPLATE20_V  0x0000000FU
 #define ISP_GAU_TEMPLATE20_S  4
 /** ISP_GAU_TEMPLATE12 : R/W; bitpos: [11:8]; default: 15;
- *  this field configures index 12 of gausian template
+ *  this field configures index 12 of gaussian template
  */
 #define ISP_GAU_TEMPLATE12    0x0000000FU
 #define ISP_GAU_TEMPLATE12_M  (ISP_GAU_TEMPLATE12_V << ISP_GAU_TEMPLATE12_S)
 #define ISP_GAU_TEMPLATE12_V  0x0000000FU
 #define ISP_GAU_TEMPLATE12_S  8
 /** ISP_GAU_TEMPLATE11 : R/W; bitpos: [15:12]; default: 15;
- *  this field configures index 11 of gausian template
+ *  this field configures index 11 of gaussian template
  */
 #define ISP_GAU_TEMPLATE11    0x0000000FU
 #define ISP_GAU_TEMPLATE11_M  (ISP_GAU_TEMPLATE11_V << ISP_GAU_TEMPLATE11_S)
 #define ISP_GAU_TEMPLATE11_V  0x0000000FU
 #define ISP_GAU_TEMPLATE11_S  12
 /** ISP_GAU_TEMPLATE10 : R/W; bitpos: [19:16]; default: 15;
- *  this field configures index 10 of gausian template
+ *  this field configures index 10 of gaussian template
  */
 #define ISP_GAU_TEMPLATE10    0x0000000FU
 #define ISP_GAU_TEMPLATE10_M  (ISP_GAU_TEMPLATE10_V << ISP_GAU_TEMPLATE10_S)
 #define ISP_GAU_TEMPLATE10_V  0x0000000FU
 #define ISP_GAU_TEMPLATE10_S  16
 /** ISP_GAU_TEMPLATE02 : R/W; bitpos: [23:20]; default: 15;
- *  this field configures index 02 of gausian template
+ *  this field configures index 02 of gaussian template
  */
 #define ISP_GAU_TEMPLATE02    0x0000000FU
 #define ISP_GAU_TEMPLATE02_M  (ISP_GAU_TEMPLATE02_V << ISP_GAU_TEMPLATE02_S)
 #define ISP_GAU_TEMPLATE02_V  0x0000000FU
 #define ISP_GAU_TEMPLATE02_S  20
 /** ISP_GAU_TEMPLATE01 : R/W; bitpos: [27:24]; default: 15;
- *  this field configures index 01 of gausian template
+ *  this field configures index 01 of gaussian template
  */
 #define ISP_GAU_TEMPLATE01    0x0000000FU
 #define ISP_GAU_TEMPLATE01_M  (ISP_GAU_TEMPLATE01_V << ISP_GAU_TEMPLATE01_S)
 #define ISP_GAU_TEMPLATE01_V  0x0000000FU
 #define ISP_GAU_TEMPLATE01_S  24
 /** ISP_GAU_TEMPLATE00 : R/W; bitpos: [31:28]; default: 15;
- *  this field configures index 00 of gausian template
+ *  this field configures index 00 of gaussian template
  */
 #define ISP_GAU_TEMPLATE00    0x0000000FU
 #define ISP_GAU_TEMPLATE00_M  (ISP_GAU_TEMPLATE00_V << ISP_GAU_TEMPLATE00_S)
@@ -582,7 +582,7 @@ extern "C" {
  */
 #define ISP_BF_GAU1_REG (DR_REG_ISP_BASE + 0x34)
 /** ISP_GAU_TEMPLATE22 : R/W; bitpos: [3:0]; default: 15;
- *  this field configures index 22 of gausian template
+ *  this field configures index 22 of gaussian template
  */
 #define ISP_GAU_TEMPLATE22    0x0000000FU
 #define ISP_GAU_TEMPLATE22_M  (ISP_GAU_TEMPLATE22_V << ISP_GAU_TEMPLATE22_S)
@@ -2584,7 +2584,7 @@ extern "C" {
 #define ISP_AE_MONITOR_TH_V  0x000000FFU
 #define ISP_AE_MONITOR_TH_S  8
 /** ISP_AE_MONITOR_PERIOD : R/W; bitpos: [21:16]; default: 0;
- *  this field cnfigures ae monitor frame period
+ *  this field configures ae monitor frame period
  */
 #define ISP_AE_MONITOR_PERIOD    0x0000003FU
 #define ISP_AE_MONITOR_PERIOD_M  (ISP_AE_MONITOR_PERIOD_V << ISP_AE_MONITOR_PERIOD_S)
@@ -3030,7 +3030,7 @@ extern "C" {
  */
 #define ISP_DMA_CNTL_REG (DR_REG_ISP_BASE + 0x10c)
 /** ISP_DMA_EN : WT; bitpos: [0]; default: 0;
- *  write 1 to triger dma to get 1 frame
+ *  write 1 to trigger dma to get 1 frame
  */
 #define ISP_DMA_EN    (BIT(0))
 #define ISP_DMA_EN_M  (ISP_DMA_EN_V << ISP_DMA_EN_S)
@@ -3090,7 +3090,7 @@ extern "C" {
  */
 #define ISP_CAM_CNTL_REG (DR_REG_ISP_BASE + 0x114)
 /** ISP_CAM_EN : R/W; bitpos: [0]; default: 0;
- *  write 1 to start recive camera data, write 0 to disable
+ *  write 1 to start receive camera data, write 0 to disable
  */
 #define ISP_CAM_EN    (BIT(0))
 #define ISP_CAM_EN_M  (ISP_CAM_EN_V << ISP_CAM_EN_S)
@@ -3111,7 +3111,7 @@ extern "C" {
 #define ISP_CAM_RESET_V  0x00000001U
 #define ISP_CAM_RESET_S  2
 /** ISP_CAM_CLK_INV : R/W; bitpos: [3]; default: 0;
- *  this bit configures the invertion of cam clk from pad. 0: not invert cam clk, 1:
+ *  this bit configures the inversion of cam clk from pad. 0: not invert cam clk, 1:
  *  invert cam clk
  */
 #define ISP_CAM_CLK_INV    (BIT(3))
@@ -3487,7 +3487,7 @@ extern "C" {
  */
 #define ISP_AWB_MODE_REG (DR_REG_ISP_BASE + 0x164)
 /** ISP_AWB_MODE : R/W; bitpos: [1:0]; default: 3;
- *  this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel
+ *  this field configures awb algo sel. 00: none selected. 01: sel algo0. 10: sel
  *  algo1. 11: sel both algo0 and algo1
  */
 #define ISP_AWB_MODE    0x00000003U

components/soc/esp32p4/register/soc/l2mem_monitor_struct.h

@@ -12,7 +12,7 @@ extern "C" {
 
 /** Group: configuration registers */
 /** Type of log_setting register
- *  log config regsiter
+ *  log config register
  */
 typedef union {
     struct {
@@ -43,7 +43,7 @@ typedef union {
 } mem_monitor_log_setting_reg_t;
 
 /** Type of log_setting1 register
- *  log config regsiter
+ *  log config register
  */
 typedef union {
     struct {
@@ -61,7 +61,7 @@ typedef union {
 } mem_monitor_log_setting1_reg_t;
 
 /** Type of log_check_data register
- *  check data regsiter
+ *  check data register
  */
 typedef union {
     struct {
@@ -89,7 +89,7 @@ typedef union {
 } mem_monitor_log_data_mask_reg_t;
 
 /** Type of log_min register
- *  log boundary regsiter
+ *  log boundary register
  */
 typedef union {
     struct {
@@ -102,7 +102,7 @@ typedef union {
 } mem_monitor_log_min_reg_t;
 
 /** Type of log_max register
- *  log boundary regsiter
+ *  log boundary register
  */
 typedef union {
     struct {

components/soc/esp32p4/register/soc/lp_clkrst_reg.h

@@ -829,7 +829,7 @@ extern "C" {
 #define LP_CLKRST_HP_FOSC_20M_CLK_EN_V  0x00000001U
 #define LP_CLKRST_HP_FOSC_20M_CLK_EN_S  24
 /** LP_CLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1;
- *  XTAL 40M Clock Enalbe.
+ *  XTAL 40M Clock Enable.
  */
 #define LP_CLKRST_HP_XTAL_40M_CLK_EN    (BIT(25))
 #define LP_CLKRST_HP_XTAL_40M_CLK_EN_M  (LP_CLKRST_HP_XTAL_40M_CLK_EN_V << LP_CLKRST_HP_XTAL_40M_CLK_EN_S)

components/soc/esp32p4/register/soc/lp_clkrst_struct.h

@@ -611,7 +611,7 @@ typedef union {
          */
         uint32_t hp_fosc_20m_clk_en:1;
         /** hp_xtal_40m_clk_en : R/W; bitpos: [25]; default: 1;
-         *  XTAL 40M Clock Enalbe.
+         *  XTAL 40M Clock Enable.
          */
         uint32_t hp_xtal_40m_clk_en:1;
         /** hp_cpll_400m_clk_en : R/W; bitpos: [26]; default: 1;