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https://github.com/espressif/esp-idf
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Merge branch 'refactor/hal_function_set_exception_vector_table' into 'master'
soc: add hal api to set exception vector table base address See merge request espressif/esp-idf!7905
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commit
59381b60c0
@ -130,10 +130,8 @@ void IRAM_ATTR call_start_cpu0(void)
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bootloader_init_mem();
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//Move exception vectors to IRAM
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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// Move exception vectors to IRAM
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cpu_hal_set_vecbase(&_init_start);
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rst_reas[0] = rtc_get_reset_reason(0);
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@ -273,9 +271,8 @@ static void wdt_reset_cpu1_info_enable(void)
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void IRAM_ATTR call_start_cpu1(void)
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{
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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// Move exception vectors to IRAM
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cpu_hal_set_vecbase(&_init_start);
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ets_set_appcpu_boot_addr(0);
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@ -114,10 +114,8 @@ void IRAM_ATTR call_start_cpu0(void)
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bootloader_init_mem();
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//Move exception vectors to IRAM
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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// Move exception vectors to IRAM
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cpu_hal_set_vecbase(&_init_start);
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rst_reas = rtc_get_reset_reason(0);
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@ -109,6 +109,13 @@ void cpu_hal_clear_watchpoint(int id);
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#endif // SOC_CPU_WATCHPOINTS_NUM > 0
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/**
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* Set exception vector table base address.
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*
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* @param base address to move the exception vector table to
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*/
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void cpu_hal_set_vecbase(const void* base);
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#ifdef __cplusplus
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}
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#endif
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@ -166,6 +166,11 @@ static inline void cpu_ll_break(void)
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__asm__ ("break 0,0");
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}
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static inline void cpu_ll_set_vecbase(const void* vecbase)
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{
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asm volatile ("wsr %0, vecbase" :: "r" (vecbase));
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}
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#ifdef __cplusplus
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}
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#endif
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@ -162,6 +162,11 @@ static inline void cpu_ll_break(void)
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__asm__ ("break 0,0");
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}
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static inline void cpu_ll_set_vecbase(const void* vecbase)
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{
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asm volatile ("wsr %0, vecbase" :: "r" (vecbase));
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}
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#ifdef __cplusplus
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}
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#endif
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@ -54,4 +54,9 @@ void cpu_hal_clear_watchpoint(int id)
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{
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cpu_ll_clear_watchpoint(id);
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}
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#endif // SOC_CPU_WATCHPOINTS_NUM > 0
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#endif // SOC_CPU_WATCHPOINTS_NUM > 0
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void cpu_hal_set_vecbase(const void* base)
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{
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cpu_ll_set_vecbase(base);
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}
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