diff --git a/.gitlab/ci/target-test.yml b/.gitlab/ci/target-test.yml index 9dd088c1bd..9f72b08eb2 100644 --- a/.gitlab/ci/target-test.yml +++ b/.gitlab/ci/target-test.yml @@ -362,6 +362,22 @@ component_ut_pytest_esp32_flash_multi: - build_pytest_components_esp32 tags: [ esp32, flash_mutli ] +component_ut_pytest_esp32_xtal32k: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32 + needs: + - build_pytest_components_esp32 + tags: [ esp32, xtal32k ] + +component_ut_pytest_esp32_no32kXtal: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32 + needs: + - build_pytest_components_esp32 + tags: [ esp32, no32kXtal ] + component_ut_pytest_esp32_rs485_multi: extends: - .pytest_components_dir_template @@ -370,6 +386,15 @@ component_ut_pytest_esp32_rs485_multi: - build_pytest_components_esp32 tags: [ esp32, multi_dut_modbus_rs485 ] +component_ut_pytest_esp32_psramv0: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32 + needs: + - build_pytest_components_esp32 + tags: [ esp32, psramv0 ] + + component_ut_pytest_esp32s2_generic: extends: - .pytest_components_dir_template @@ -1042,33 +1067,12 @@ UT_035: - ESP32S2_IDF - UT_T1_1 -UT_036: - extends: .unit_test_esp32_template - tags: - - ESP32_IDF - - UT_T1_PSRAMV0 - - psram - UT_038: extends: .unit_test_esp32s2_template tags: - ESP32S2_IDF - UT_T1_ESP_FLASH -UT_041: - extends: .unit_test_esp32_template - tags: - - ESP32_IDF - - UT_T1_no32kXTAL - - psram - -UT_043: - extends: .unit_test_esp32_template - tags: - - ESP32_IDF - - UT_T1_32kXTAL - - psram - UT_S2_SDSPI: extends: .unit_test_esp32s2_template tags: diff --git a/components/esp_hw_support/.build-test-rules.yml b/components/esp_hw_support/.build-test-rules.yml index e61b946b79..0de7028cab 100644 --- a/components/esp_hw_support/.build-test-rules.yml +++ b/components/esp_hw_support/.build-test-rules.yml @@ -9,3 +9,9 @@ components/esp_hw_support/test_apps/dma: components/esp_hw_support/test_apps/etm: disable: - if: SOC_ETM_SUPPORTED != 1 + +components/esp_hw_support/test_apps/rtc_clk: + disable: + - if: IDF_TARGET in ["esp32c6"] + temporary: true + reason: Unsupported on C6 for now. TODO IDF-5645 diff --git a/components/esp_hw_support/test/CMakeLists.txt b/components/esp_hw_support/test/CMakeLists.txt deleted file mode 100644 index 5479db5f6a..0000000000 --- a/components/esp_hw_support/test/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -idf_component_register(SRC_DIRS "." - PRIV_INCLUDE_DIRS "${include_dirs}" - PRIV_REQUIRES cmock test_utils esp_hw_support driver efuse esp_timer esp_psram spi_flash) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") - -target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_test_dport_xt_highint5") diff --git a/components/esp_hw_support/test/test_ahb_arb.c b/components/esp_hw_support/test/test_ahb_arb.c deleted file mode 100644 index 9e65b81235..0000000000 --- a/components/esp_hw_support/test/test_ahb_arb.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "sdkconfig.h" - -#if CONFIG_IDF_TARGET_ESP32 - -#include -#include -#include -#include "esp32/rom/lldesc.h" -#include "esp_private/periph_ctrl.h" -#include "hal/gpio_hal.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/semphr.h" -#include "freertos/queue.h" -#include "freertos/xtensa_api.h" - -#include "unity.h" - -#include "soc/uart_periph.h" -#include "soc/dport_reg.h" -#include "soc/gpio_periph.h" -#include "soc/i2s_periph.h" - - - -#define DPORT_I2S0_CLK_EN (BIT(4)) -#define DPORT_I2S0_RST (BIT(4)) - - -/* -This test tests the s32c1i instruction when the AHB bus is also used. To create some AHB traffic, we use the I2S interface -to copy bytes over from one memory location to another. DO NOT USE the i2s routines inhere, they've been trial-and-error'ed until -the point where they happened to do what I want. -*/ - -static void lcdIfaceInit(void) -{ - periph_module_enable(PERIPH_I2S0_MODULE); - - //Init pins to i2s functions - SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable - - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO2_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO5_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO18_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO20_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, 2); //11 - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, 0); //RS - - WRITE_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG, (148 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC2_OUT_SEL_CFG_REG, (149 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC5_OUT_SEL_CFG_REG, (150 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC16_OUT_SEL_CFG_REG, (151 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC17_OUT_SEL_CFG_REG, (152 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC18_OUT_SEL_CFG_REG, (153 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC19_OUT_SEL_CFG_REG, (154 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC20_OUT_SEL_CFG_REG, (155 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC26_OUT_SEL_CFG_REG, (156 << GPIO_FUNC0_OUT_SEL_S)); //RS - WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, (I2S0O_WS_OUT_IDX << GPIO_FUNC0_OUT_SEL_S)); -// WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG, (I2S0O_BCK_OUT_IDX< - -#include "esp_types.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/semphr.h" -#include "freertos/queue.h" -#include "freertos/xtensa_api.h" -#include "unity.h" -#include "soc/uart_periph.h" -#include "soc/dport_reg.h" -#include "hal/gpio_hal.h" -#include "driver/gpio.h" - - -/* -This test tests the 'fast' peripherial bus at 0x3ff40000. This bus is connected directly to the core, and as such -can receive 'speculative' reads, that is, reads that may or may not actually be executed in the code flow. This -may mess with any FIFOs mapped in the region: if a byte gets dropped due to a missed speculative read, the fifo -may advance to the next byte anyway. - -This code tests reading/writing from the UART1 FIFO, using both cores. For this to work, it's required that the -UARTs RX and TX lines are connected. -*/ - - -void test_fastbus_cp(int fifo_addr, unsigned char *buf, int len, int *dummy); - -static volatile int state = 0; -static volatile int xor = 0; -static unsigned char res[128]; - -static void tskOne(void *pvParameters) -{ - int run = 0, err = 0; - int x; - int ct[256]; - volatile int w; - int dummy; - while (1) { - state = 1; - for (x = 0; x < 64; x++) { - WRITE_PERI_REG(UART_FIFO_REG(1), x ^ xor); - } - for (w = 0; w < (1 << 14); w++); //delay - state = 2; - test_fastbus_cp(UART_FIFO_REG(1), &res[0], 64, &dummy); - for (w = 0; w < (1 << 10); w++); //delay - for (x = 0; x < 255; x++) { - ct[x] = 0; //zero ctrs - } - for (x = 0; x < 128; x++) { - ct[(int)res[x]^xor]++; //count values - } - for (x = 0; x < 255; x++) { //check counts - if (ct[x] != (x < 128 ? 1 : 0)) { - //Disregard first few loops; there may be crap in the fifo. - if (run > 2) { - err++; - printf("Error! Received value %d %d times!\n", x, ct[x]); - } - } - } - run++; - if ((run & 255) == 0) { - printf("Loop %d errct %d\n", run, err); - } - xor = (xor + 1) & 0xff; - } -} - -#define FB2ADDR 0x40098000 - -static void tskTwo(void *pvParameters) -{ - int x; - int dummy; - int *p = (int *)FB2ADDR; - int *s = (int *)test_fastbus_cp; - for (x = 0; x < 100; x++) { - *p++ = *s++; - } - void (*test_fastbus_cp2)(int fifo_addr, unsigned char * buf, int len, int * dummy) = (void *)FB2ADDR; - - - while (1) { - while (state != 1) ; - for (x = 64; x < 128; x++) { - WRITE_PERI_REG(UART_FIFO_REG(1), x ^ xor); - } - while (state != 2); - test_fastbus_cp2(UART_FIFO_REG(1), &res[64], 64, &dummy); - } -} - - -// TODO: split this thing into separate orthogonal tests -TEST_CASE("Fast I/O bus test", "[hw][ignore]") -{ - int i; - if ((REG_UART_BASE(0) >> 16) != 0x3ff4) { - printf("Error! Uart base isn't on fast bus.\n"); - TEST_ASSERT(0); - } - - gpio_pullup_dis(10); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, FUNC_SD_DATA2_U1RXD); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, FUNC_SD_DATA3_U1TXD); - - int reg_val = (1 << UART_RXFIFO_FULL_THRHD_S); - WRITE_PERI_REG(UART_CONF1_REG(1), reg_val); - WRITE_PERI_REG(UART_CLKDIV_REG(1), 0x30); //semi-random -// CLEAR_PERI_REG_MASK(UART_INT_ENA_REG(1), UART_TXFIFO_EMPTY_INT_ENA|UART_RXFIFO_TOUT_INT_ENA); - - TaskHandle_t th[2]; - printf("Creating tasks\n"); - xTaskCreatePinnedToCore(tskOne , "tskone" , 2048, NULL, 3, &th[0], 0); - xTaskCreatePinnedToCore(tskTwo , "tsktwo" , 2048, NULL, 3, &th[1], 1); - - // Let stuff run for 20s - while (1) { - vTaskDelay(20000 / portTICK_PERIOD_MS); - } - - //Shut down all the tasks - for (i = 0; i < 2; i++) { - vTaskDelete(th[i]); - } - xt_ints_off(1 << ETS_UART0_INUM); -} - -#endif // CONFIG_IDF_TARGET_ESP32 diff --git a/components/esp_hw_support/test/test_fastbus_asm.S b/components/esp_hw_support/test/test_fastbus_asm.S deleted file mode 100644 index ccef358e21..0000000000 --- a/components/esp_hw_support/test/test_fastbus_asm.S +++ /dev/null @@ -1,38 +0,0 @@ -#include "sdkconfig.h" - -#if CONFIG_IDF_TARGET_ESP32 - -/* -This little bit of code is executed in-place by one CPU, but copied to a different memory region -by the other CPU. Make sure it stays position-independent. -*/ - .text - .align 4 - .global test_fastbus_cp - .type test_fastbus_cp,@function -//Args: -//a2 - fifo addr -//a3 - buf addr -//a4 - len -//a5 - ptr to int to use -test_fastbus_cp: - entry a1,64 -back: - beqi a4, 0, out //check if loop done - s32i a4, a5, 0 //store value, for shits and/or giggles - memw //make sure write happens - l32i a4, a5, 0 //load value again, to thwart any prediction in the pipeline - bbsi a4, 0, pred //Random jump to check predictive reads. Both branches should do the same. - l32i a6, a2, 0 //read from fifo 1 - j predout -pred: - l32i a6, a2, 0 //read from fifo 2 -predout: - s8i a6, a3, 0 //store result - addi a3, a3, 1 //inc ptr - addi a4, a4, -1 //next - j back //loop again -out: - retw //and we are done - -#endif // CONFIG_IDF_TARGET_ESP32 diff --git a/components/esp_hw_support/test/test_tsens.c b/components/esp_hw_support/test/test_tsens.c deleted file mode 100644 index 0eb016bc3b..0000000000 --- a/components/esp_hw_support/test/test_tsens.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "sdkconfig.h" - -#if CONFIG_IDF_TARGET_ESP32 - -#include -#include "unity.h" -#include "esp_rom_sys.h" -#include "soc/rtc_periph.h" -#include "soc/sens_periph.h" - -TEST_CASE("can control TSENS using registers", "[rtc][ignore]") -{ - SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S); - SET_PERI_REG_BITS(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_CLK_DIV, 10, SENS_TSENS_CLK_DIV_S); - CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP); - CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT); - SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP_FORCE); - SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP); - esp_rom_delay_us(100); - SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT); - esp_rom_delay_us(5); - int res = GET_PERI_REG_BITS2(SENS_SAR_SLAVE_ADDR3_REG, SENS_TSENS_OUT, SENS_TSENS_OUT_S); - printf("res=%d\n", res); -} - - -#endif // CONFIG_IDF_TARGET_ESP32 diff --git a/components/esp_hw_support/test/test_unal_dma.c b/components/esp_hw_support/test/test_unal_dma.c deleted file mode 100644 index 96a97d497c..0000000000 --- a/components/esp_hw_support/test/test_unal_dma.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "sdkconfig.h" - -#if CONFIG_IDF_TARGET_ESP32 - -#include -#include -#include -#include -#include "esp32/rom/lldesc.h" -#include "esp_private/periph_ctrl.h" -#include "hal/gpio_hal.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/semphr.h" -#include "freertos/queue.h" -#include "freertos/xtensa_api.h" -#include "unity.h" - -#include "soc/dport_reg.h" -#include "soc/gpio_periph.h" -#include "soc/i2s_periph.h" - - -#define DPORT_I2S0_CLK_EN (BIT(4)) -#define DPORT_I2S0_RST (BIT(4)) - -static volatile lldesc_t dmaDesc[2]; - - -//hacked up routine to essentially do a memcpy() using dma. Supports max 4K-1 bytes. -static void dmaMemcpy(void *in, void *out, int len) -{ - volatile int i; - periph_module_enable(PERIPH_I2S0_MODULE); - - //Init pins to i2s functions - SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable - - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO2_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO5_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO18_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO20_U, 0); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, 2); //11 - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, 0); //RS - - WRITE_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG, (148 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC2_OUT_SEL_CFG_REG, (149 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC5_OUT_SEL_CFG_REG, (150 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC16_OUT_SEL_CFG_REG, (151 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC17_OUT_SEL_CFG_REG, (152 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC18_OUT_SEL_CFG_REG, (153 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC19_OUT_SEL_CFG_REG, (154 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC20_OUT_SEL_CFG_REG, (155 << GPIO_FUNC0_OUT_SEL_S)); - WRITE_PERI_REG(GPIO_FUNC26_OUT_SEL_CFG_REG, (156 << GPIO_FUNC0_OUT_SEL_S)); //RS - WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, (I2S0O_WS_OUT_IDX << GPIO_FUNC0_OUT_SEL_S)); -// WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG, (I2S0O_BCK_OUT_IDX<= leak_threshold, "memory leak"); +} + + +void setUp(void) +{ + // If heap tracing is enabled in kconfig, leak trace the test +#ifdef CONFIG_HEAP_TRACING + setup_heap_record(); + heap_trace_start(HEAP_TRACE_LEAKS); +#endif + + leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT; + + before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); +} + +void tearDown(void) +{ + /*Give idle task time to clean up*/ + vTaskDelay(10); + +#ifdef CONFIG_HEAP_TRACING + heap_trace_stop(); + heap_trace_dump(); +#endif + + size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + check_leak(before_free_8bit, after_free_8bit, "8BIT"); + check_leak(before_free_32bit, after_free_32bit, "32BIT"); + +} + +void app_main(void) +{ + vTaskPrioritySet(NULL, TEST_TASK_PRIORITY); + ESP_LOGI(TAG, "Running esp-hw-support test app"); + unity_run_menu(); +} diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_config.h b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_config.h new file mode 100644 index 0000000000..1b5ec0d9ce --- /dev/null +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_config.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#pragma once + +#define TEST_TASK_PRIORITY 5 diff --git a/components/esp_hw_support/test/test_dport.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c similarity index 93% rename from components/esp_hw_support/test/test_dport.c rename to components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c index 02975e42ea..6c8494e57b 100644 --- a/components/esp_hw_support/test/test_dport.c +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c @@ -8,6 +8,7 @@ #if CONFIG_IDF_TARGET_ESP32 #include #include +#include #include "xtensa/core-macros.h" #include "xtensa/hal.h" #include "esp_types.h" @@ -28,7 +29,8 @@ #include "soc/rtc.h" #include "esp_cpu.h" #include "esp_intr_alloc.h" - +#include "esp_task.h" +#include "test_config.h" #define MHZ (1000000) static volatile bool exit_flag; @@ -91,15 +93,15 @@ void run_tasks(const char *task1_description, void (* task1_func)(void *), const #ifndef CONFIG_FREERTOS_UNICORE printf("assign task accessing DPORT to core 0 and task accessing APB to core 1\n"); - if(task1_func != NULL) xTaskCreatePinnedToCore(task1_func, task1_description, 2048, &exit_sema[0], UNITY_FREERTOS_PRIORITY - 1, &th[0], 0); - if(task2_func != NULL) xTaskCreatePinnedToCore(task2_func, task2_description, 2048, &exit_sema[1], UNITY_FREERTOS_PRIORITY - 1, &th[1], 1); + if(task1_func != NULL) xTaskCreatePinnedToCore(task1_func, task1_description, 2048, &exit_sema[0], TEST_TASK_PRIORITY - 1, &th[0], 0); + if(task2_func != NULL) xTaskCreatePinnedToCore(task2_func, task2_description, 2048, &exit_sema[1], TEST_TASK_PRIORITY - 1, &th[1], 1); #else printf("assign task accessing DPORT and accessing APB\n"); - if(task1_func != NULL) xTaskCreate(task1_func, task1_description, 2048, &exit_sema[0], UNITY_FREERTOS_PRIORITY - 1, &th[0]); - if(task2_func != NULL) xTaskCreate(task2_func, task2_description, 2048, &exit_sema[1], UNITY_FREERTOS_PRIORITY - 1, &th[1]); + if(task1_func != NULL) xTaskCreate(task1_func, task1_description, 2048, &exit_sema[0], TEST_TASK_PRIORITY - 1, &th[0]); + if(task2_func != NULL) xTaskCreate(task2_func, task2_description, 2048, &exit_sema[1], TEST_TASK_PRIORITY - 1, &th[1]); #endif - printf("start wait for %d seconds [Test %s and %s]\n", delay_ms/1000, task1_description, task2_description); + printf("start wait for %"PRIu32" seconds [Test %s and %s]\n", delay_ms/1000, task1_description, task2_description); vTaskDelay(delay_ms / portTICK_PERIOD_MS); // set exit flag to let thread exit @@ -131,7 +133,7 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz) rtc_cpu_freq_config_t old_config; rtc_clk_cpu_freq_get_config(&old_config); - printf("CPU_FREQ = %d MHz\n", old_config.freq_mhz); + printf("CPU_FREQ = %"PRIu32" MHz\n", old_config.freq_mhz); if (cpu_freq_mhz != old_config.freq_mhz) { rtc_cpu_freq_config_t new_config; @@ -281,16 +283,16 @@ TEST_CASE("test for DPORT access performance", "[esp32]") printf("\nPerformance table: \n" "The number of simultaneous read operations of the APB and DPORT registers\n" - "by different methods for %d seconds.\n", delay_ms/1000); + "by different methods for %"PRIu32" seconds.\n", delay_ms/1000); printf("+-----------------------+----------+----------+----------+\n"); printf("| Method read DPORT | DPORT | APB | SUMM |\n"); printf("+-----------------------+----------+----------+----------+\n"); - printf("|1.Only accessAPB |%10d|%10d|%10d|\n", t[0].dport, t[0].apb, t[0].summ); - printf("|2.Only STALL_OTHER_CPU |%10d|%10d|%10d|\n", t[1].dport, t[1].apb, t[1].summ); - printf("|3.Only PRE_READ_APB_REG|%10d|%10d|%10d|\n", t[2].dport, t[2].apb, t[2].summ); + printf("|1.Only accessAPB |%10"PRIu32"|%10"PRIu32"|%10"PRIu32"|\n", t[0].dport, t[0].apb, t[0].summ); + printf("|2.Only STALL_OTHER_CPU |%10"PRIu32"|%10"PRIu32"|%10"PRIu32"|\n", t[1].dport, t[1].apb, t[1].summ); + printf("|3.Only PRE_READ_APB_REG|%10"PRIu32"|%10"PRIu32"|%10"PRIu32"|\n", t[2].dport, t[2].apb, t[2].summ); printf("+-----------------------+----------+----------+----------+\n"); - printf("|4.STALL_OTHER_CPU |%10d|%10d|%10d|\n", t[3].dport, t[3].apb, t[3].summ); - printf("|5.PRE_READ_APB_REG |%10d|%10d|%10d|\n", t[4].dport, t[4].apb, t[4].summ); + printf("|4.STALL_OTHER_CPU |%10"PRIu32"|%10"PRIu32"|%10"PRIu32"|\n", t[3].dport, t[3].apb, t[3].summ); + printf("|5.PRE_READ_APB_REG |%10"PRIu32"|%10"PRIu32"|%10"PRIu32"|\n", t[4].dport, t[4].apb, t[4].summ); printf("+-----------------------+----------+----------+----------+\n"); printf("| ratio=PRE_READ/STALL |%10f|%10f|%10f|\n", (float)t[4].dport/t[3].dport, (float)t[4].apb/t[3].apb, (float)t[4].summ/t[3].summ); printf("+-----------------------+----------+----------+----------+\n"); @@ -306,7 +308,7 @@ static uint32_t start, end; #define BENCHMARK_END(OPERATION) do { \ RSR(CCOUNT, end); \ - printf("%s took %d cycles/op (%d cycles for %d ops)\n", \ + printf("%s took %"PRIu32" cycles/op (%"PRIu32" cycles for %d ops)\n", \ OPERATION, (end - start)/REPEAT_OPS, \ (end - start), REPEAT_OPS); \ } while(0) diff --git a/components/esp_hw_support/test/test_dport_xt_highint5.S b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S similarity index 94% rename from components/esp_hw_support/test/test_dport_xt_highint5.S rename to components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S index 197d7c8cc4..2e7b15fcea 100644 --- a/components/esp_hw_support/test/test_dport_xt_highint5.S +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ #include "sdkconfig.h" #if CONFIG_IDF_TARGET_ESP32 diff --git a/components/esp_hw_support/test/test_ds.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ds.c similarity index 100% rename from components/esp_hw_support/test/test_ds.c rename to components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ds.c diff --git a/components/esp_hw_support/test/test_fp.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_fp.c similarity index 95% rename from components/esp_hw_support/test/test_fp.c rename to components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_fp.c index 47f2a259b8..4848d93d79 100644 --- a/components/esp_hw_support/test/test_fp.c +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_fp.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -227,11 +227,17 @@ float IRAM_ATTR test_fp_benchmark_fp_divide(int counts, unsigned *cycles) return f; } + +extern void set_leak_threshold(int threshold); + TEST_CASE("floating point division performance", "[fp]") { const unsigned COUNTS = 1000; unsigned cycles = 0; + /*From lazy allocating resources when printing floats*/ + set_leak_threshold(-850); + // initialize fpu volatile __attribute__((unused)) float dummy = sqrtf(rand()); @@ -265,6 +271,9 @@ TEST_CASE("floating point square root performance", "[fp]") const unsigned COUNTS = 200; unsigned cycles = 0; + /*From lazy allocating resources when printing floats*/ + set_leak_threshold(-850); + // initialize fpu volatile float __attribute__((unused)) dummy = sqrtf(rand()); diff --git a/components/esp_hw_support/test/test_intr_alloc.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_intr_alloc.c similarity index 100% rename from components/esp_hw_support/test/test_intr_alloc.c rename to components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_intr_alloc.c diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/pytest_esp_hw_support.py b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/pytest_esp_hw_support.py new file mode 100644 index 0000000000..94ddf934ec --- /dev/null +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/pytest_esp_hw_support.py @@ -0,0 +1,21 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + pytest.param('single_core_esp32', marks=[pytest.mark.esp32]), + pytest.param('default', marks=[pytest.mark.supported_targets]), + pytest.param('release', marks=[pytest.mark.supported_targets]), + ], + indirect=True, +) +def test_esp_hw_support(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('![ignore]') + dut.expect_unity_test_output(timeout=120) diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.default b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.default new file mode 100644 index 0000000000..5324680c99 --- /dev/null +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.default @@ -0,0 +1 @@ +# Empty file to be able to parametrize "default" config diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.release b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.release new file mode 100644 index 0000000000..8b0a31a9bc --- /dev/null +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.release @@ -0,0 +1,6 @@ +# set compiler optimization level +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y + +# we can silent the assertion to save the binary footprint +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.single_core_esp32 b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.single_core_esp32 new file mode 100644 index 0000000000..5262d9dafb --- /dev/null +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.single_core_esp32 @@ -0,0 +1,2 @@ +CONFIG_IDF_TARGET="esp32" +CONFIG_FREERTOS_UNICORE=y diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults new file mode 100644 index 0000000000..b71277ca37 --- /dev/null +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_ESP_TASK_WDT_INIT=n +CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192 diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults.esp32 b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults.esp32 new file mode 100644 index 0000000000..966c5e4f95 --- /dev/null +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults.esp32 @@ -0,0 +1,2 @@ +# Set CPU frequency to max for performance tests +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults.esp32s2 b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults.esp32s2 new file mode 100644 index 0000000000..a28e22281d --- /dev/null +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults.esp32s2 @@ -0,0 +1,2 @@ +# Set CPU frequency to max for performance tests +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y diff --git a/components/esp_hw_support/test_apps/rtc_clk/CMakeLists.txt b/components/esp_hw_support/test_apps/rtc_clk/CMakeLists.txt new file mode 100644 index 0000000000..9ced12d554 --- /dev/null +++ b/components/esp_hw_support/test_apps/rtc_clk/CMakeLists.txt @@ -0,0 +1,11 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +set(COMPONENTS main) +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +set(SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers") +list(APPEND SDKCONFIG_DEFAULTS "sdkconfig.defaults") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(rtc_clk) diff --git a/components/esp_hw_support/test_apps/rtc_clk/README.md b/components/esp_hw_support/test_apps/rtc_clk/README.md new file mode 100644 index 0000000000..b5be4985c5 --- /dev/null +++ b/components/esp_hw_support/test_apps/rtc_clk/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | diff --git a/components/esp_hw_support/test_apps/rtc_clk/main/CMakeLists.txt b/components/esp_hw_support/test_apps/rtc_clk/main/CMakeLists.txt new file mode 100644 index 0000000000..37e22584de --- /dev/null +++ b/components/esp_hw_support/test_apps/rtc_clk/main/CMakeLists.txt @@ -0,0 +1,8 @@ +set(srcs "test_app_main.c" + "test_rtc_clk.c") + +# In order for the cases defined by `TEST_CASE` to be linked into the final elf, +# the component can be registered as WHOLE_ARCHIVE +idf_component_register(SRCS ${srcs} + REQUIRES unity driver test_utils + WHOLE_ARCHIVE) diff --git a/components/esp_hw_support/test_apps/rtc_clk/main/test_app_main.c b/components/esp_hw_support/test_apps/rtc_clk/main/test_app_main.c new file mode 100644 index 0000000000..6bd53a060c --- /dev/null +++ b/components/esp_hw_support/test_apps/rtc_clk/main/test_app_main.c @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "unity_test_runner.h" +#include "esp_heap_caps.h" +#include "esp_log.h" +#ifdef CONFIG_HEAP_TRACING +#include "memory_checks.h" +#include "esp_heap_trace.h" +#endif + +#define TEST_MEMORY_LEAK_THRESHOLD_DEFAULT -300 +static int leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT; + +void set_leak_threshold(int threshold) +{ + leak_threshold = threshold; +} + +static size_t before_free_8bit; +static size_t before_free_32bit; +static const char* TAG = "esp_hw_support_test_app"; + +static void check_leak(size_t before_free, size_t after_free, const char *type) +{ + ssize_t delta = after_free - before_free; + printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta); + TEST_ASSERT_MESSAGE(delta >= leak_threshold, "memory leak"); +} + +void setUp(void) +{ + // If heap tracing is enabled in kconfig, leak trace the test +#ifdef CONFIG_HEAP_TRACING + setup_heap_record(); + heap_trace_start(HEAP_TRACE_LEAKS); +#endif + + leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT; + + before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); +} + +void tearDown(void) +{ +#ifdef CONFIG_HEAP_TRACING + heap_trace_stop(); + heap_trace_dump(); +#endif + + size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + check_leak(before_free_8bit, after_free_8bit, "8BIT"); + check_leak(before_free_32bit, after_free_32bit, "32BIT"); + +} + +void app_main(void) +{ + ESP_LOGI(TAG, "Running esp-hw-support test app"); + unity_run_menu(); +} diff --git a/components/esp_hw_support/test/test_rtc_clk.c b/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c similarity index 91% rename from components/esp_hw_support/test/test_rtc_clk.c rename to components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c index a50c72dcf3..c5fca8b290 100644 --- a/components/esp_hw_support/test/test_rtc_clk.c +++ b/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include #include "unity.h" #include "esp_attr.h" @@ -16,14 +17,13 @@ #include "soc/gpio_periph.h" #include "hal/gpio_ll.h" #include "driver/rtc_io.h" -#include "test_utils.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" #include "esp_rom_gpio.h" #include "esp_rom_sys.h" #include "esp_rom_uart.h" - +#include "test_utils.h" #include "esp_sleep.h" #include "esp_system.h" #include "esp_private/esp_clk.h" @@ -136,18 +136,18 @@ static void pull_out_clk(int sel) REG_SET_FIELD(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_SEL0, sel); } -TEST_CASE("Output 150k clock to GPIO25", "[rtc_clk][ignore]") +TEST_CASE("Output 150k clock to GPIO25", "[ignore]") { pull_out_clk(RTC_IO_DEBUG_SEL0_150K_OSC); } -TEST_CASE("Output 32k XTAL clock to GPIO25", "[rtc_clk][ignore]") +TEST_CASE("Output 32k XTAL clock to GPIO25", "[ignore]") { rtc_clk_32k_enable(true); pull_out_clk(RTC_IO_DEBUG_SEL0_32K_XTAL); } -TEST_CASE("Output 8M XTAL clock to GPIO25", "[rtc_clk][ignore]") +TEST_CASE("Output 8M XTAL clock to GPIO25", "[ignore]") { rtc_clk_8m_enable(true, true); SET_PERI_REG_MASK(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_12M_NO_GATING); @@ -184,7 +184,7 @@ TEST_CASE("Calculate 8M clock frequency", "[rtc_clk]") // calibrate 8M/256 clock against XTAL, get 8M/256 clock period uint32_t rtc_8md256_period = rtc_clk_cal(RTC_CAL_8MD256, 100); uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period; - printf("RTC_FAST_CLK=%d Hz\n", rtc_fast_freq_hz); + printf("RTC_FAST_CLK=%"PRIu32" Hz\n", rtc_fast_freq_hz); TEST_ASSERT_INT32_WITHIN(650000, SOC_CLK_RC_FAST_FREQ_APPROX, rtc_fast_freq_hz); } @@ -231,12 +231,12 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay stop_rtc_external_quartz(); #ifdef CONFIG_RTC_CLK_SRC_EXT_CRYS uint32_t bootstrap_cycles = CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES; - printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n", + printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %"PRIu32",\n Calibration cycles = %d.\n", bootstrap_cycles, CONFIG_RTC_CLK_CAL_CYCLES); #else uint32_t bootstrap_cycles = 5; - printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n", + printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %"PRIu32",\n Calibration cycles = %d.\n", bootstrap_cycles, CONFIG_RTC_CLK_CAL_CYCLES); #endif // CONFIG_RTC_CLK_SRC_EXT_CRYS @@ -253,7 +253,7 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay rtc_clk_select_rtc_slow_clk(); selected_src = rtc_clk_slow_src_get(); end_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ); - printf(" [time=%d] ", (end_time - start_time) - start_delay_ms); + printf(" [time=%"PRIu32"] ", (end_time - start_time) - start_delay_ms); if(selected_src != required_src){ printf("FAIL. Time measurement..."); fail = 1; @@ -276,7 +276,7 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay if(fail_measure == 0) { printf("PASS"); } - printf(" [calibration val = %d] \n", esp_clk_slowclk_cal_get()); + printf(" [calibration val = %"PRIu32"] \n", esp_clk_slowclk_cal_get()); stop_rtc_external_quartz(); esp_rom_delay_us(500000); } @@ -284,7 +284,7 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay printf("Test passed successfully\n"); } -TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=UT_T1_32kXTAL]") +TEST_CASE("Test starting external RTC quartz", "[test_env=xtal32k]") { int i = 0, fail = 0; uint32_t start_time; @@ -292,12 +292,12 @@ TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=UT_T1_32kXTAL stop_rtc_external_quartz(); #ifdef CONFIG_RTC_CLK_SRC_EXT_CRYS uint32_t bootstrap_cycles = CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES; - printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n", + printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %"PRIu32",\n Calibration cycles = %d.\n", bootstrap_cycles, CONFIG_RTC_CLK_CAL_CYCLES); #else uint32_t bootstrap_cycles = 5; - printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n", + printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %"PRIu32",\n Calibration cycles = %d.\n", bootstrap_cycles, CONFIG_RTC_CLK_CAL_CYCLES); #endif // CONFIG_RTC_CLK_SRC_EXT_CRYS @@ -311,7 +311,7 @@ TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=UT_T1_32kXTAL rtc_clk_32k_bootstrap(bootstrap_cycles); rtc_clk_select_rtc_slow_clk(); end_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ); - printf(" [time=%d] ", end_time - start_time); + printf(" [time=%"PRIu32"] ", end_time - start_time); if((end_time - start_time) > TIMEOUT_TEST_MS){ printf("FAIL\n"); fail = 1; @@ -325,13 +325,13 @@ TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=UT_T1_32kXTAL printf("Test passed successfully\n"); } -TEST_CASE("Test starting 'External 32kHz XTAL' on the board with it.", "[rtc_clk][test_env=UT_T1_32kXTAL]") +TEST_CASE("Test starting 'External 32kHz XTAL' on the board with it.", "[test_env=xtal32k]") { start_freq(SOC_RTC_SLOW_CLK_SRC_XTAL32K, 200); start_freq(SOC_RTC_SLOW_CLK_SRC_XTAL32K, 0); } -TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_clk][test_env=UT_T1_no32kXTAL]") +TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[test_env=noXtal32k]") { printf("Tries to start the 'External 32kHz XTAL' on the board without it. " "Clock switching to 'Internal 150 kHz RC oscillator'.\n"); @@ -378,8 +378,6 @@ TEST_CASE("Test rtc clk calibration compensation", "[rtc_clk]") TEST_ASSERT_GREATER_THAN(t1, t2); } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) -/* Disabled until deep sleep is brought up TODO ESP32-S3 IDF-2691 */ static RTC_NOINIT_ATTR int64_t start = 0; static void trigger_deepsleep(void) @@ -429,7 +427,6 @@ static void check_time_deepsleep_2(void) TEST_ASSERT_GREATER_THAN(start, end); } -TEST_CASE_MULTIPLE_STAGES("Test rtc clk calibration compensation across deep sleep", "[rtc_clk][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET]", trigger_deepsleep, check_time_deepsleep_1, check_time_deepsleep_2); +TEST_CASE_MULTIPLE_STAGES("Test rtc clk calibration compensation across deep sleep", "", trigger_deepsleep, check_time_deepsleep_1, check_time_deepsleep_2); -#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) #endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) diff --git a/components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py b/components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py new file mode 100644 index 0000000000..16768215ed --- /dev/null +++ b/components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py @@ -0,0 +1,37 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +from typing import Any + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.generic +@pytest.mark.esp32 +def test_rtc_clk(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('[rtc_clk]') + dut.expect_unity_test_output() + + +@pytest.mark.esp32 +@pytest.mark.xtal32k +def test_rtc_xtal32k(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('[test_env=xtal32k]') + dut.expect_unity_test_output() + + +@pytest.mark.esp32 +@pytest.mark.no32kXtal +def test_rtc_no_xtal32k(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('[test_env=noXtal32k]') + dut.expect_unity_test_output() + + +@pytest.mark.generic +@pytest.mark.supported_targets +def test_rtc_calib(case_tester: Any) -> None: + case_tester.run_all_multi_stage_cases() diff --git a/components/esp_hw_support/test_apps/rtc_clk/sdkconfig.defaults b/components/esp_hw_support/test_apps/rtc_clk/sdkconfig.defaults new file mode 100644 index 0000000000..c97863dd9d --- /dev/null +++ b/components/esp_hw_support/test_apps/rtc_clk/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_ESP_TASK_WDT_INIT=n +CONFIG_FREERTOS_HZ=1000 diff --git a/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/CMakeLists.txt b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/CMakeLists.txt new file mode 100644 index 0000000000..963a775cae --- /dev/null +++ b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/CMakeLists.txt @@ -0,0 +1,11 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +set(COMPONENTS main) +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +set(SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers") +list(APPEND SDKCONFIG_DEFAULTS "sdkconfig.defaults") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(test_app_security_support) diff --git a/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/README.md b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/README.md new file mode 100644 index 0000000000..7e7523ec85 --- /dev/null +++ b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/CMakeLists.txt b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/CMakeLists.txt new file mode 100644 index 0000000000..749d633ac2 --- /dev/null +++ b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/CMakeLists.txt @@ -0,0 +1,11 @@ +set(srcs "test_app_main.c" + "test_ds.c" + "test_hmac.c" + "test_random.c" + ) + +# In order for the cases defined by `TEST_CASE` to be linked into the final elf, +# the component can be registered as WHOLE_ARCHIVE +idf_component_register(SRCS ${srcs} + REQUIRES unity driver test_utils efuse + WHOLE_ARCHIVE) diff --git a/components/esp_hw_support/test/digital_signature_test_cases_3072.h b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/digital_signature_test_cases_3072.h similarity index 100% rename from components/esp_hw_support/test/digital_signature_test_cases_3072.h rename to components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/digital_signature_test_cases_3072.h diff --git a/components/esp_hw_support/test/digital_signature_test_cases_4096.h b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/digital_signature_test_cases_4096.h similarity index 100% rename from components/esp_hw_support/test/digital_signature_test_cases_4096.h rename to components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/digital_signature_test_cases_4096.h diff --git a/components/esp_hw_support/test/gen_digital_signature_tests.py b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/gen_digital_signature_tests.py similarity index 100% rename from components/esp_hw_support/test/gen_digital_signature_tests.py rename to components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/gen_digital_signature_tests.py diff --git a/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_app_main.c b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_app_main.c new file mode 100644 index 0000000000..cec79807cb --- /dev/null +++ b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_app_main.c @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "unity_test_runner.h" +#include "esp_heap_caps.h" +#include "esp_log.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "test_config.h" +#ifdef CONFIG_HEAP_TRACING +#include "memory_checks.h" +#include "esp_heap_trace.h" +#endif + +#define TEST_MEMORY_LEAK_THRESHOLD_DEFAULT -400 +static int leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT; + +void set_leak_threshold(int threshold) +{ + leak_threshold = threshold; +} + +static size_t before_free_8bit; +static size_t before_free_32bit; +static const char* TAG = "esp_hw_support_test_app"; + +static void check_leak(size_t before_free, size_t after_free, const char *type) +{ + ssize_t delta = after_free - before_free; + printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta); + TEST_ASSERT_MESSAGE(delta >= leak_threshold, "memory leak"); +} + + +void setUp(void) +{ + // If heap tracing is enabled in kconfig, leak trace the test +#ifdef CONFIG_HEAP_TRACING + setup_heap_record(); + heap_trace_start(HEAP_TRACE_LEAKS); +#endif + + leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT; + + before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); +} + +void tearDown(void) +{ + /*Give idle task time to clean up*/ + vTaskDelay(10); + +#ifdef CONFIG_HEAP_TRACING + heap_trace_stop(); + heap_trace_dump(); +#endif + + size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + check_leak(before_free_8bit, after_free_8bit, "8BIT"); + check_leak(before_free_32bit, after_free_32bit, "32BIT"); + +} + +void app_main(void) +{ + vTaskPrioritySet(NULL, TEST_TASK_PRIORITY); + ESP_LOGI(TAG, "Running esp-hw-support test app"); + unity_run_menu(); +} diff --git a/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_config.h b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_config.h new file mode 100644 index 0000000000..1b5ec0d9ce --- /dev/null +++ b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_config.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#pragma once + +#define TEST_TASK_PRIORITY 5 diff --git a/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_ds.c b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_ds.c new file mode 100644 index 0000000000..23c94d45f3 --- /dev/null +++ b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_ds.c @@ -0,0 +1,443 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "unity.h" + +#include "soc/soc_caps.h" + +#if SOC_DIG_SIGN_SUPPORTED +#if CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/efuse.h" +#include "esp32s2/rom/digital_signature.h" +#include "esp32s2/rom/aes.h" +#include "esp32s2/rom/sha.h" +#elif CONFIG_IDF_TARGET_ESP32C3 +#include "esp32c3/rom/efuse.h" +#include "esp32c3/rom/digital_signature.h" +#include "esp32c3/rom/hmac.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/efuse.h" +#include "esp32s3/rom/digital_signature.h" +#include "esp32s3/rom/aes.h" +#include "esp32s3/rom/sha.h" +#endif + +#include "esp_ds.h" + +#define NUM_RESULTS 10 + +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#define DS_MAX_BITS (4096) +#elif CONFIG_IDF_TARGET_ESP32C3 +#define DS_MAX_BITS (ETS_DS_MAX_BITS) +#endif + +typedef struct { + uint8_t iv[ETS_DS_IV_LEN]; + ets_ds_p_data_t p_data; + uint8_t expected_c[ETS_DS_C_LEN]; + uint8_t hmac_key_idx; + uint32_t expected_results[NUM_RESULTS][DS_MAX_BITS / 32]; +} encrypt_testcase_t; + +// Generated header digital_signature_test_cases_.h (by gen_digital_signature_tests.py) defines +// NUM_HMAC_KEYS, test_hmac_keys, NUM_MESSAGES, NUM_CASES, test_messages[], test_cases[] +// Some adaptations were made: removed the 512 bit case and changed RSA lengths to the enums from esp_ds.h +#if DS_MAX_BITS == 4096 +#define RSA_LEN (ESP_DS_RSA_4096) +#include "digital_signature_test_cases_4096.h" +#elif DS_MAX_BITS == 3072 +#define RSA_LEN (ESP_DS_RSA_3072) +#include "digital_signature_test_cases_3072.h" +#endif + +_Static_assert(NUM_RESULTS == NUM_MESSAGES, "expected_results size should be the same as NUM_MESSAGES in generated header"); + +TEST_CASE("Digital Signature Parameter Encryption data NULL", "[hw_crypto] [ds]") +{ + const char iv [32] = {0}; + esp_ds_p_data_t p_data = {0}; + const char key [32] = {0}; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_encrypt_params(NULL, iv, &p_data, key)); +} + +TEST_CASE("Digital Signature Parameter Encryption iv NULL", "[hw_crypto] [ds]") +{ + esp_ds_data_t data = {0}; + esp_ds_p_data_t p_data = {0}; + const char key [32] = {0}; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_encrypt_params(&data, NULL, &p_data, key)); +} + +TEST_CASE("Digital Signature Parameter Encryption p_data NULL", "[hw_crypto] [ds]") +{ + esp_ds_data_t data = {0}; + const char iv [32] = {0}; + const char key [32] = {0}; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_encrypt_params(&data, iv, NULL, key)); +} + +TEST_CASE("Digital Signature Parameter Encryption key NULL", "[hw_crypto] [ds]") +{ + esp_ds_data_t data = {0}; + const char iv [32] = {0}; + esp_ds_p_data_t p_data = {0}; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_encrypt_params(&data, iv, &p_data, NULL)); +} + +TEST_CASE("Digital Signature Parameter Encryption", "[hw_crypto] [ds]") +{ + for (int i = 0; i < NUM_CASES; i++) { + printf("Encrypting test case %d...\n", i); + const encrypt_testcase_t *t = &test_cases[i]; + esp_ds_data_t result = { }; + esp_ds_p_data_t p_data; + + memcpy(p_data.Y, t->p_data.Y, DS_MAX_BITS / 8); + memcpy(p_data.M, t->p_data.M, DS_MAX_BITS / 8); + memcpy(p_data.Rb, t->p_data.Rb, DS_MAX_BITS / 8); + p_data.M_prime = t->p_data.M_prime; + p_data.length = t->p_data.length; + + esp_err_t r = esp_ds_encrypt_params(&result, t->iv, &p_data, + test_hmac_keys[t->hmac_key_idx]); + printf("Encrypting test case %d done\n", i); + TEST_ASSERT_EQUAL(ESP_OK, r); + TEST_ASSERT_EQUAL(t->p_data.length, result.rsa_length); + TEST_ASSERT_EQUAL_HEX8_ARRAY(t->iv, result.iv, ETS_DS_IV_LEN); + TEST_ASSERT_EQUAL_HEX8_ARRAY(t->expected_c, result.c, ETS_DS_C_LEN); + } +} + +TEST_CASE("Digital Signature start Invalid message", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = { }; + ds_data.rsa_length = RSA_LEN; + esp_ds_context_t *ctx; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(NULL, &ds_data, HMAC_KEY1, &ctx)); +} + +TEST_CASE("Digital Signature start Invalid data", "[hw_crypto] [ds]") +{ + const char *message = "test"; + esp_ds_context_t *ctx; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, NULL, HMAC_KEY1, &ctx)); +} + +TEST_CASE("Digital Signature start Invalid context", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = RSA_LEN; + const char *message = "test"; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY1, NULL)); +} + +TEST_CASE("Digital Signature RSA length 0", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = 0; + const char *message = "test"; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY1, NULL)); +} + +TEST_CASE("Digital Signature RSA length too long", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = 128; + const char *message = "test"; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY1, NULL)); +} + +TEST_CASE("Digital Signature start HMAC key out of range", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = RSA_LEN; + esp_ds_context_t *ctx; + const char *message = "test"; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY5 + 1, &ctx)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY0 - 1, &ctx)); +} + +TEST_CASE("Digital Signature finish Invalid signature ptr", "[hw_crypto] [ds]") +{ + esp_ds_context_t *ctx = NULL; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_finish_sign(NULL, ctx)); +} + +TEST_CASE("Digital Signature finish Invalid context", "[hw_crypto] [ds]") +{ + uint8_t signature_data [128 * 4]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_finish_sign(signature_data, NULL)); +} + +TEST_CASE("Digital Signature Blocking Invalid message", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = { }; + ds_data.rsa_length = RSA_LEN; + uint8_t signature_data [128 * 4]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(NULL, &ds_data, HMAC_KEY1, signature_data)); +} + +TEST_CASE("Digital Signature Blocking Invalid data", "[hw_crypto] [ds]") +{ + const char *message = "test"; + uint8_t signature_data [128 * 4]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, NULL, HMAC_KEY1, signature_data)); +} + +TEST_CASE("Digital Signature Blocking Invalid signature ptr", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = RSA_LEN; + const char *message = "test"; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY1, NULL)); +} + +TEST_CASE("Digital Signature Blocking RSA length 0", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = 0; + const char *message = "test"; + uint8_t signature_data [128 * 4]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY1, signature_data)); +} + +TEST_CASE("Digital Signature Blocking RSA length too long", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = 128; + const char *message = "test"; + uint8_t signature_data [128 * 4]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY1, signature_data)); +} + +TEST_CASE("Digital Signature Blocking HMAC key out of range", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = 127; + const char *message = "test"; + uint8_t signature_data [128 * 4]; + + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY5 + 1, signature_data)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY0 - 1, signature_data)); +} + +#if CONFIG_IDF_ENV_FPGA + +static void burn_hmac_keys(void) +{ + printf("Burning %d HMAC keys to efuse...\n", NUM_HMAC_KEYS); + for (int i = 0; i < NUM_HMAC_KEYS; i++) { + // TODO: vary the purpose across the keys + ets_efuse_purpose_t purpose = ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE; + + // starting from block 1, block 0 occupied with HMAC upstream test key + int __attribute__((unused)) ets_status = ets_efuse_write_key(ETS_EFUSE_BLOCK_KEY1 + i, + purpose, + test_hmac_keys[i], 32); + +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + if (ets_status == ESP_OK) { + printf("written DS test key to block [%d]!\n", ETS_EFUSE_BLOCK_KEY1 + i); + } else { + printf("writing DS test key to block [%d] failed, maybe written already\n", ETS_EFUSE_BLOCK_KEY1 + i); + } +#endif + } +#if CONFIG_IDF_TARGET_ESP32C3 + /* verify the keys are what we expect (possibly they're already burned, doesn't matter but they have to match) */ + uint8_t block_compare[32]; + for (int i = 0; i < NUM_HMAC_KEYS; i++) { + printf("Checking key %d...\n", i); + memcpy(block_compare, (void *)ets_efuse_get_read_register_address(ETS_EFUSE_BLOCK_KEY1 + i), 32); + TEST_ASSERT_EQUAL_HEX8_ARRAY(test_hmac_keys[i], block_compare, 32); + } +#endif +} + +// This test uses the HMAC_KEY0 eFuse key which hasn't been burned by burn_hmac_keys(). +// HMAC_KEY0 is usually used for HMAC upstream (user access) tests. +TEST_CASE("Digital Signature wrong HMAC key purpose (FPGA only)", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = RSA_LEN; + esp_ds_context_t *ctx; + const char *message = "test"; + + // HMAC fails in that case because it checks for the correct purpose +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + TEST_ASSERT_EQUAL(ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_start_sign(message, &ds_data, HMAC_KEY0, &ctx)); +#elif CONFIG_IDF_TARGET_ESP32C3 + TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_start_sign(message, &ds_data, HMAC_KEY0, &ctx)); +#endif +} + +// This test uses the HMAC_KEY0 eFuse key which hasn't been burned by burn_hmac_keys(). +// HMAC_KEY0 is usually used for HMAC upstream (user access) tests. +TEST_CASE("Digital Signature Blocking wrong HMAC key purpose (FPGA only)", "[hw_crypto] [ds]") +{ + esp_ds_data_t ds_data = {}; + ds_data.rsa_length = RSA_LEN; + const char *message = "test"; + uint8_t signature_data [128 * 4]; + + // HMAC fails in that case because it checks for the correct purpose +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + TEST_ASSERT_EQUAL(ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_sign(message, &ds_data, HMAC_KEY0, signature_data)); +#elif CONFIG_IDF_TARGET_ESP32C3 + TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_sign(message, &ds_data, HMAC_KEY0, signature_data)); +#endif +} + +TEST_CASE("Digital Signature Operation (FPGA only)", "[hw_crypto] [ds]") +{ + burn_hmac_keys(); + + for (int i = 0; i < NUM_CASES; i++) { + printf("Running test case %d...\n", i); + const encrypt_testcase_t *t = &test_cases[i]; + + // copy encrypt parameter test case into ds_data structure + esp_ds_data_t ds_data = { }; + memcpy(ds_data.iv, t->iv, ETS_DS_IV_LEN); + memcpy(ds_data.c, t->expected_c, ETS_DS_C_LEN); + ds_data.rsa_length = t->p_data.length; + + for (int j = 0; j < NUM_MESSAGES; j++) { + uint8_t signature[DS_MAX_BITS / 8] = { 0 }; + printf(" ... message %d\n", j); + + esp_ds_context_t *esp_ds_ctx; + + esp_err_t ds_r = esp_ds_start_sign(test_messages[j], + &ds_data, + t->hmac_key_idx + 1, + &esp_ds_ctx); + TEST_ASSERT_EQUAL(ESP_OK, ds_r); + + ds_r = esp_ds_finish_sign(signature, esp_ds_ctx); + TEST_ASSERT_EQUAL(ESP_OK, ds_r); + + TEST_ASSERT_EQUAL_HEX8_ARRAY(t->expected_results[j], signature, sizeof(signature)); + } +#if CONFIG_IDF_TARGET_ESP32C3 + ets_hmac_invalidate_downstream(ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE); +#endif + } +} + +TEST_CASE("Digital Signature Blocking Operation (FPGA only)", "[hw_crypto] [ds]") +{ + burn_hmac_keys(); + + for (int i = 0; i < NUM_CASES; i++) { + printf("Running test case %d...\n", i); + const encrypt_testcase_t *t = &test_cases[i]; + + // copy encrypt parameter test case into ds_data structure + esp_ds_data_t ds_data = { }; + memcpy(ds_data.iv, t->iv, ETS_DS_IV_LEN); + memcpy(ds_data.c, t->expected_c, ETS_DS_C_LEN); + ds_data.rsa_length = t->p_data.length; + + uint8_t signature[DS_MAX_BITS / 8] = { 0 }; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + esp_ds_context_t *esp_ds_ctx; + + esp_err_t ds_r = esp_ds_start_sign(test_messages[0], + &ds_data, + t->hmac_key_idx + 1, + &esp_ds_ctx); + TEST_ASSERT_EQUAL(ESP_OK, ds_r); + + ds_r = esp_ds_finish_sign(signature, esp_ds_ctx); + TEST_ASSERT_EQUAL(ESP_OK, ds_r); +#elif CONFIG_IDF_TARGET_ESP32C3 + esp_err_t ds_r = esp_ds_sign(test_messages[0], + &ds_data, + t->hmac_key_idx + 1, + signature); + TEST_ASSERT_EQUAL(ESP_OK, ds_r); +#endif + + TEST_ASSERT_EQUAL_HEX8_ARRAY(t->expected_results[0], signature, sizeof(signature)); + } +} + +TEST_CASE("Digital Signature Invalid Data (FPGA only)", "[hw_crypto] [ds]") +{ + burn_hmac_keys(); + + // Set up a valid test case + const encrypt_testcase_t *t = &test_cases[0]; + esp_ds_data_t ds_data = { }; + memcpy(ds_data.iv, t->iv, ETS_DS_IV_LEN); + memcpy(ds_data.c, t->expected_c, ETS_DS_C_LEN); + ds_data.rsa_length = t->p_data.length; + + uint8_t signature[DS_MAX_BITS / 8] = { 0 }; + const uint8_t zero[DS_MAX_BITS / 8] = { 0 }; + + // Corrupt the IV one bit at a time, rerun and expect failure + for (int bit = 0; bit < 128; bit++) { + printf("Corrupting IV bit %d...\n", bit); + ds_data.iv[bit / 8] ^= 1 << (bit % 8); + esp_ds_context_t *esp_ds_ctx; + + esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, t->hmac_key_idx + 1, &esp_ds_ctx); + TEST_ASSERT_EQUAL(ESP_OK, ds_r); + ds_r = esp_ds_finish_sign(signature, esp_ds_ctx); +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + TEST_ASSERT_EQUAL(ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r); +#elif CONFIG_IDF_TARGET_ESP32C3 + TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r); +#endif + TEST_ASSERT_EQUAL_HEX8_ARRAY(zero, signature, DS_MAX_BITS / 8); + + ds_data.iv[bit / 8] ^= 1 << (bit % 8); + } + + // Corrupt encrypted key data one bit at a time, rerun and expect failure + printf("Corrupting C...\n"); + for (int bit = 0; bit < ETS_DS_C_LEN * 8; bit++) { + printf("Corrupting C bit %d...\n", bit); + ds_data.c[bit / 8] ^= 1 << (bit % 8); + esp_ds_context_t *esp_ds_ctx; + + esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, t->hmac_key_idx + 1, &esp_ds_ctx); + TEST_ASSERT_EQUAL(ESP_OK, ds_r); + ds_r = esp_ds_finish_sign(signature, esp_ds_ctx); +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + TEST_ASSERT_EQUAL(ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r); +#elif CONFIG_IDF_TARGET_ESP32C3 + TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r); +#endif + TEST_ASSERT_EQUAL_HEX8_ARRAY(zero, signature, DS_MAX_BITS / 8); + + ds_data.c[bit / 8] ^= 1 << (bit % 8); + } +} + +#endif // CONFIG_IDF_ENV_FPGA +#endif // SOC_DIG_SIGN_SUPPORTED diff --git a/components/esp_hw_support/test/test_hmac.c b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_hmac.c similarity index 100% rename from components/esp_hw_support/test/test_hmac.c rename to components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_hmac.c diff --git a/components/esp_hw_support/test/test_random.c b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_random.c similarity index 100% rename from components/esp_hw_support/test/test_random.c rename to components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_random.c diff --git a/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/pytest_security_support.py b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/pytest_security_support.py new file mode 100644 index 0000000000..f044640c38 --- /dev/null +++ b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/pytest_security_support.py @@ -0,0 +1,20 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + pytest.param('default', marks=[pytest.mark.supported_targets]), + pytest.param('release', marks=[pytest.mark.supported_targets]), + ], + indirect=True, +) +def test_security_support(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('![ignore]') + dut.expect_unity_test_output(timeout=120) diff --git a/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.ci.default b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.ci.default new file mode 100644 index 0000000000..5324680c99 --- /dev/null +++ b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.ci.default @@ -0,0 +1 @@ +# Empty file to be able to parametrize "default" config diff --git a/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.ci.release b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.ci.release new file mode 100644 index 0000000000..8b0a31a9bc --- /dev/null +++ b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.ci.release @@ -0,0 +1,6 @@ +# set compiler optimization level +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y + +# we can silent the assertion to save the binary footprint +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.defaults b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.defaults new file mode 100644 index 0000000000..b71277ca37 --- /dev/null +++ b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_ESP_TASK_WDT_INIT=n +CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192 diff --git a/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.defaults.esp32 b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.defaults.esp32 new file mode 100644 index 0000000000..966c5e4f95 --- /dev/null +++ b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.defaults.esp32 @@ -0,0 +1,2 @@ +# Set CPU frequency to max for performance tests +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y diff --git a/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.defaults.esp32s2 b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.defaults.esp32s2 new file mode 100644 index 0000000000..a28e22281d --- /dev/null +++ b/components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.defaults.esp32s2 @@ -0,0 +1,2 @@ +# Set CPU frequency to max for performance tests +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y diff --git a/components/esp_psram/test_apps/psram/main/CMakeLists.txt b/components/esp_psram/test_apps/psram/main/CMakeLists.txt index 7fa3034028..f00ce1a11c 100644 --- a/components/esp_psram/test_apps/psram/main/CMakeLists.txt +++ b/components/esp_psram/test_apps/psram/main/CMakeLists.txt @@ -4,7 +4,7 @@ set(srcs "test_app_main.c" "test_psram.c") if(${target} STREQUAL "esp32") - list(APPEND srcs "test_himem.c") + list(APPEND srcs "test_himem.c" "test_4mpsram.c") endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, diff --git a/components/esp_hw_support/test/test_4mpsram.c b/components/esp_psram/test_apps/psram/main/test_4mpsram.c similarity index 97% rename from components/esp_hw_support/test/test_4mpsram.c rename to components/esp_psram/test_apps/psram/main/test_4mpsram.c index cf41310873..ef1f0838aa 100644 --- a/components/esp_hw_support/test/test_4mpsram.c +++ b/components/esp_psram/test_apps/psram/main/test_4mpsram.c @@ -70,7 +70,7 @@ static void test_spi_bus_occupy(spi_host_device_t expected_occupied_host) } #if CONFIG_SPIRAM_OCCUPY_HSPI_HOST || CONFIG_SPIRAM_OCCUPY_VSPI_HOST -TEST_CASE("some spi bus occpied by psram", "[psram_4m][test_env=UT_T1_PSRAMV0]") +TEST_CASE("some spi bus occpied by psram", "[psram_4m]") { // NOTE: this unit test rely on the config that PSRAM of 8MB is used only when CONFIG_SPIRAM_BANKSWITCH_ENABLE is set //currently all 8M psram don't need more SPI peripherals diff --git a/components/esp_psram/test_apps/psram/pytest_psram.py b/components/esp_psram/test_apps/psram/pytest_psram.py index c08f4718b1..dfc795dbc9 100644 --- a/components/esp_psram/test_apps/psram/pytest_psram.py +++ b/components/esp_psram/test_apps/psram/pytest_psram.py @@ -66,3 +66,19 @@ def test_psram_esp32s3_octal(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('*') dut.expect_unity_test_output() + + +@pytest.mark.esp32 +@pytest.mark.psramv0 +@pytest.mark.parametrize( + 'config', + [ + 'esp32_hspi', + 'esp32_vspi', + ], + indirect=True, +) +def test_psram_esp32_psramv0(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output() diff --git a/tools/unit-test-app/configs/psram_hspi b/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32_hspi similarity index 76% rename from tools/unit-test-app/configs/psram_hspi rename to components/esp_psram/test_apps/psram/sdkconfig.ci.esp32_hspi index 96da87d0fe..9c65cdd622 100644 --- a/tools/unit-test-app/configs/psram_hspi +++ b/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32_hspi @@ -1,8 +1,7 @@ CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=esp_hw_support -TEST_GROUPS=psram_4m CONFIG_ESPTOOLPY_FLASHFREQ_80M=y CONFIG_SPIRAM=y CONFIG_SPIRAM_SPEED_80M=y CONFIG_SPIRAM_OCCUPY_HSPI_HOST=y CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 +CONFIG_SPIRAM_BANKSWITCH_ENABLE=n diff --git a/tools/unit-test-app/configs/psram_vspi b/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32_vspi similarity index 76% rename from tools/unit-test-app/configs/psram_vspi rename to components/esp_psram/test_apps/psram/sdkconfig.ci.esp32_vspi index 6048590480..e024caab12 100644 --- a/tools/unit-test-app/configs/psram_vspi +++ b/components/esp_psram/test_apps/psram/sdkconfig.ci.esp32_vspi @@ -1,8 +1,7 @@ CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=esp_hw_support -TEST_GROUPS=psram_4m CONFIG_ESPTOOLPY_FLASHFREQ_80M=y CONFIG_SPIRAM=y CONFIG_SPIRAM_SPEED_80M=y CONFIG_SPIRAM_OCCUPY_VSPI_HOST=y CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 +CONFIG_SPIRAM_BANKSWITCH_ENABLE=n diff --git a/components/esp_hw_support/test/test_spiram_cache_flush.c b/components/spi_flash/test/test_spiram_cache_flush.c similarity index 100% rename from components/esp_hw_support/test/test_spiram_cache_flush.c rename to components/spi_flash/test/test_spiram_cache_flush.c diff --git a/pytest.ini b/pytest.ini index 37c7266ea5..2b08159450 100644 --- a/pytest.ini +++ b/pytest.ini @@ -68,7 +68,10 @@ markers = MSPI_F4R4: runner with Quad Flash and Quad PSRAM test_jtag_arm: runner where the chip is accessible through JTAG as well adc: ADC related tests should run on adc runners - multi_dut_modbus_rs485: a pair of runners connectd by RS485 bus + xtal32k: Runner with external 32k crystal connected + no32kXtal: Runner with no external 32k crystal connected + multi_dut_modbus_rs485: a pair of runners connected by RS485 bus + psramv0: Runner with PSRAM version 0 # multi-dut markers ieee802154: ieee802154 related tests should run on ieee802154 runners. diff --git a/tools/unit-test-app/configs/default b/tools/unit-test-app/configs/default index c8397196f0..02cfcdb9c4 100644 --- a/tools/unit-test-app/configs/default +++ b/tools/unit-test-app/configs/default @@ -1,4 +1,4 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) # IRAM is full... split some component to default_32_2 CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=esp_hw_support esp_ipc esp_system driver +TEST_COMPONENTS=esp_system driver diff --git a/tools/unit-test-app/configs/default_2 b/tools/unit-test-app/configs/default_2 index 1b52f30e0d..de0745572b 100644 --- a/tools/unit-test-app/configs/default_2 +++ b/tools/unit-test-app/configs/default_2 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be excluded (esp32, esp32s2) CONFIG_IDF_TARGET="esp32" -TEST_EXCLUDE_COMPONENTS=bt esp_hw_support esp_ipc esp_pm esp_system driver soc spi_flash vfs test_utils experimental_cpp_component +TEST_EXCLUDE_COMPONENTS=bt esp_pm esp_system driver soc spi_flash vfs test_utils experimental_cpp_component diff --git a/tools/unit-test-app/configs/default_2_c3 b/tools/unit-test-app/configs/default_2_c3 index 816fe234d4..4312d539df 100644 --- a/tools/unit-test-app/configs/default_2_c3 +++ b/tools/unit-test-app/configs/default_2_c3 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be excluded CONFIG_IDF_TARGET="esp32c3" -TEST_EXCLUDE_COMPONENTS=bt esp_pm esp_hw_support esp_ipc esp_system driver soc spi_flash vfs lwip spiffs experimental_cpp_component perfmon test_utils +TEST_EXCLUDE_COMPONENTS=bt esp_pm esp_system driver soc spi_flash vfs lwip spiffs experimental_cpp_component perfmon test_utils diff --git a/tools/unit-test-app/configs/default_2_s2 b/tools/unit-test-app/configs/default_2_s2 index 884ba50387..9ca23f8cdd 100644 --- a/tools/unit-test-app/configs/default_2_s2 +++ b/tools/unit-test-app/configs/default_2_s2 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be excluded (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_EXCLUDE_COMPONENTS=bt esp_hw_support esp_ipc esp_pm esp_system driver soc spi_flash vfs experimental_cpp_component +TEST_EXCLUDE_COMPONENTS=bt esp_pm esp_system driver soc spi_flash vfs experimental_cpp_component diff --git a/tools/unit-test-app/configs/default_2_s3 b/tools/unit-test-app/configs/default_2_s3 index 9b9c864044..c1c3ecc7eb 100644 --- a/tools/unit-test-app/configs/default_2_s3 +++ b/tools/unit-test-app/configs/default_2_s3 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be excluded (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s3" -TEST_EXCLUDE_COMPONENTS=bt esp32s3 esp_ipc esp_pm esp_system driver soc spi_flash vfs experimental_cpp_component test_utils +TEST_EXCLUDE_COMPONENTS=bt esp32s3 esp_pm esp_system driver soc spi_flash vfs experimental_cpp_component test_utils diff --git a/tools/unit-test-app/configs/default_3_c2 b/tools/unit-test-app/configs/default_3_c2 index 9c551d5ca7..fa0e213fef 100644 --- a/tools/unit-test-app/configs/default_3_c2 +++ b/tools/unit-test-app/configs/default_3_c2 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be included CONFIG_IDF_TARGET="esp32c2" -TEST_EXCLUDE_COMPONENTS=app_trace esp_eth esp_hid esp_netif esp_phy esp_ringbuf esp_wifi espcoredump hal lwip mdns mqtt newlib nvs_flash partition_table sdmmc esp_hw_support esp_ipc esp_system driver soc spi_flash vfs +TEST_EXCLUDE_COMPONENTS=app_trace esp_eth esp_hid esp_netif esp_phy esp_ringbuf esp_wifi espcoredump hal lwip mdns mqtt newlib nvs_flash partition_table sdmmc esp_system driver soc spi_flash vfs diff --git a/tools/unit-test-app/configs/default_c2 b/tools/unit-test-app/configs/default_c2 index 952aee7189..8c31c17705 100644 --- a/tools/unit-test-app/configs/default_c2 +++ b/tools/unit-test-app/configs/default_c2 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be included CONFIG_IDF_TARGET="esp32c2" -TEST_COMPONENTS= esp_hw_support esp_ipc esp_system driver soc spi_flash vfs +TEST_COMPONENTS= esp_system driver soc spi_flash vfs diff --git a/tools/unit-test-app/configs/default_c3 b/tools/unit-test-app/configs/default_c3 index 0aaf09979c..ee79fa1e4a 100644 --- a/tools/unit-test-app/configs/default_c3 +++ b/tools/unit-test-app/configs/default_c3 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be included CONFIG_IDF_TARGET="esp32c3" -TEST_COMPONENTS=esp_hw_support esp_ipc esp_system driver +TEST_COMPONENTS=esp_system driver diff --git a/tools/unit-test-app/configs/default_s2_1 b/tools/unit-test-app/configs/default_s2_1 index de0e638cd6..4ef8dd3cbc 100644 --- a/tools/unit-test-app/configs/default_s2_1 +++ b/tools/unit-test-app/configs/default_s2_1 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_COMPONENTS=esp_hw_support esp_system driver +TEST_COMPONENTS=esp_system driver diff --git a/tools/unit-test-app/configs/default_s3 b/tools/unit-test-app/configs/default_s3 index 346473e97b..f4b4181757 100644 --- a/tools/unit-test-app/configs/default_s3 +++ b/tools/unit-test-app/configs/default_s3 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be included CONFIG_IDF_TARGET="esp32s3" -TEST_COMPONENTS=esp_hw_support esp_ipc esp_system driver soc spi_flash vfs +TEST_COMPONENTS=esp_system driver soc spi_flash vfs diff --git a/tools/unit-test-app/configs/freertos_compliance b/tools/unit-test-app/configs/freertos_compliance index a24787da60..9e1e6cac7f 100644 --- a/tools/unit-test-app/configs/freertos_compliance +++ b/tools/unit-test-app/configs/freertos_compliance @@ -1,4 +1,4 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=driver esp_hw_support esp_ipc spi_flash +TEST_COMPONENTS=driver spi_flash CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE=y diff --git a/tools/unit-test-app/configs/freertos_compliance_c2 b/tools/unit-test-app/configs/freertos_compliance_c2 index 7916012045..09147fbd17 100644 --- a/tools/unit-test-app/configs/freertos_compliance_c2 +++ b/tools/unit-test-app/configs/freertos_compliance_c2 @@ -1,4 +1,4 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32c2" -TEST_COMPONENTS=driver esp_hw_support esp_system spi_flash +TEST_COMPONENTS=driver esp_system spi_flash CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE=y diff --git a/tools/unit-test-app/configs/freertos_compliance_c3 b/tools/unit-test-app/configs/freertos_compliance_c3 index 8fa6fa7d48..106ec0fab0 100644 --- a/tools/unit-test-app/configs/freertos_compliance_c3 +++ b/tools/unit-test-app/configs/freertos_compliance_c3 @@ -1,4 +1,4 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32c3" -TEST_COMPONENTS=driver esp_hw_support esp_system spi_flash +TEST_COMPONENTS=driver esp_system spi_flash CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE=y diff --git a/tools/unit-test-app/configs/freertos_compliance_s2 b/tools/unit-test-app/configs/freertos_compliance_s2 index 022ad1d0b7..5d31b3648d 100644 --- a/tools/unit-test-app/configs/freertos_compliance_s2 +++ b/tools/unit-test-app/configs/freertos_compliance_s2 @@ -1,4 +1,4 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_COMPONENTS=driver esp_hw_support esp_system spi_flash +TEST_COMPONENTS=driver esp_system spi_flash CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE=y diff --git a/tools/unit-test-app/configs/no_optimization_c2 b/tools/unit-test-app/configs/no_optimization_c2 index c0d62b770c..567ec11d78 100644 --- a/tools/unit-test-app/configs/no_optimization_c2 +++ b/tools/unit-test-app/configs/no_optimization_c2 @@ -1,3 +1,3 @@ CONFIG_IDF_TARGET="esp32c2" -TEST_COMPONENTS=esp_ipc spi_flash +TEST_COMPONENTS=spi_flash CONFIG_COMPILER_OPTIMIZATION_NONE=y diff --git a/tools/unit-test-app/configs/no_optimization_c3 b/tools/unit-test-app/configs/no_optimization_c3 index 00719f8712..462b888eb7 100644 --- a/tools/unit-test-app/configs/no_optimization_c3 +++ b/tools/unit-test-app/configs/no_optimization_c3 @@ -1,3 +1,3 @@ CONFIG_IDF_TARGET="esp32c3" -TEST_COMPONENTS=esp_ipc spi_flash +TEST_COMPONENTS=spi_flash CONFIG_COMPILER_OPTIMIZATION_NONE=y diff --git a/tools/unit-test-app/configs/no_optimization_esp32 b/tools/unit-test-app/configs/no_optimization_esp32 index 64114b1215..79280971d3 100644 --- a/tools/unit-test-app/configs/no_optimization_esp32 +++ b/tools/unit-test-app/configs/no_optimization_esp32 @@ -1,3 +1,3 @@ CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=esp_ipc spi_flash +TEST_COMPONENTS=spi_flash CONFIG_COMPILER_OPTIMIZATION_NONE=y diff --git a/tools/unit-test-app/configs/psram b/tools/unit-test-app/configs/psram index 1ac47a225e..aa9f15aa61 100644 --- a/tools/unit-test-app/configs/psram +++ b/tools/unit-test-app/configs/psram @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32" -TEST_EXCLUDE_COMPONENTS=bt driver esp_hw_support esp_ipc esp_pm esp_system spi_flash test_utils soc experimental_cpp_component esp-tls sdmmc +TEST_EXCLUDE_COMPONENTS=bt driver esp_pm esp_system spi_flash test_utils soc experimental_cpp_component esp-tls sdmmc CONFIG_SPIRAM=y CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 CONFIG_SPIRAM_OCCUPY_NO_HOST=y diff --git a/tools/unit-test-app/configs/psram_2 b/tools/unit-test-app/configs/psram_2 index cd575b036e..bb67887028 100644 --- a/tools/unit-test-app/configs/psram_2 +++ b/tools/unit-test-app/configs/psram_2 @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=esp_hw_support esp_ipc esp_system spi_flash soc +TEST_COMPONENTS=esp_system spi_flash soc CONFIG_SPIRAM=y CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 CONFIG_SPIRAM_OCCUPY_NO_HOST=y diff --git a/tools/unit-test-app/configs/psram_8m b/tools/unit-test-app/configs/psram_8m deleted file mode 100644 index 3001befbb1..0000000000 --- a/tools/unit-test-app/configs/psram_8m +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=esp_hw_support -CONFIG_SPIRAM=y -CONFIG_SPIRAM_BANKSWITCH_ENABLE=y -CONFIG_SPIRAM_BANKSWITCH_RESERVE=8 -CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 -CONFIG_SPIRAM_OCCUPY_NO_HOST=y diff --git a/tools/unit-test-app/configs/psram_all_ext_1 b/tools/unit-test-app/configs/psram_all_ext_1 index a3fed000c4..378e0d55ed 100644 --- a/tools/unit-test-app/configs/psram_all_ext_1 +++ b/tools/unit-test-app/configs/psram_all_ext_1 @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=driver esp_hw_support esp_system +TEST_COMPONENTS=driver esp_system CONFIG_SPIRAM=y CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 CONFIG_SPIRAM_OCCUPY_NO_HOST=y diff --git a/tools/unit-test-app/configs/psram_s2_advanced b/tools/unit-test-app/configs/psram_s2_advanced deleted file mode 100644 index b9315bfa9b..0000000000 --- a/tools/unit-test-app/configs/psram_s2_advanced +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_IDF_TARGET="esp32s2" -TEST_COMPONENTS=esp_hw_support -CONFIG_SPIRAM=y -CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y -CONFIG_SPIRAM_RODATA=y -CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y diff --git a/tools/unit-test-app/configs/psram_s2_base b/tools/unit-test-app/configs/psram_s2_base index b9faef087c..251498bf57 100644 --- a/tools/unit-test-app/configs/psram_s2_base +++ b/tools/unit-test-app/configs/psram_s2_base @@ -1,3 +1,3 @@ CONFIG_IDF_TARGET="esp32s2" -TEST_COMPONENTS=esp_hw_support esp_system +TEST_COMPONENTS=esp_system CONFIG_SPIRAM=y diff --git a/tools/unit-test-app/configs/psram_s3_base b/tools/unit-test-app/configs/psram_s3_base index 898ea06ce5..05f38b96dc 100644 --- a/tools/unit-test-app/configs/psram_s3_base +++ b/tools/unit-test-app/configs/psram_s3_base @@ -1,3 +1,3 @@ CONFIG_IDF_TARGET="esp32s3" -TEST_COMPONENTS=esp_hw_support esp_system +TEST_COMPONENTS=esp_system CONFIG_SPIRAM=y diff --git a/tools/unit-test-app/configs/release b/tools/unit-test-app/configs/release index 711449913f..52c7be32aa 100644 --- a/tools/unit-test-app/configs/release +++ b/tools/unit-test-app/configs/release @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=esp_hw_support esp_system esp_ipc driver soc spi_flash vfs +TEST_COMPONENTS=esp_system driver soc spi_flash vfs CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/tools/unit-test-app/configs/release_2 b/tools/unit-test-app/configs/release_2 index 0168546bc0..02b93712ad 100644 --- a/tools/unit-test-app/configs/release_2 +++ b/tools/unit-test-app/configs/release_2 @@ -1,6 +1,6 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32" -TEST_EXCLUDE_COMPONENTS=bt esp_hw_support esp_ipc esp_pm esp_system driver soc spi_flash vfs test_utils experimental_cpp_component +TEST_EXCLUDE_COMPONENTS=bt esp_pm esp_system driver soc spi_flash vfs test_utils experimental_cpp_component CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/tools/unit-test-app/configs/release_2_s2 b/tools/unit-test-app/configs/release_2_s2 index 1318c3c7f2..b89097679c 100644 --- a/tools/unit-test-app/configs/release_2_s2 +++ b/tools/unit-test-app/configs/release_2_s2 @@ -1,6 +1,6 @@ # This config is split between targets since different component needs to be excluded (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_EXCLUDE_COMPONENTS=bt esp_hw_support esp_ipc esp_pm esp_system driver soc spi_flash vfs test_utils experimental_cpp_component +TEST_EXCLUDE_COMPONENTS=bt esp_pm esp_system driver soc spi_flash vfs test_utils experimental_cpp_component CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/tools/unit-test-app/configs/release_c2 b/tools/unit-test-app/configs/release_c2 index 5d17fae005..976d223ef9 100644 --- a/tools/unit-test-app/configs/release_c2 +++ b/tools/unit-test-app/configs/release_c2 @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32c2" -TEST_COMPONENTS=esp_hw_support esp_system esp_ipc driver soc spi_flash vfs sdmmc +TEST_COMPONENTS=esp_system driver soc spi_flash vfs sdmmc CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y diff --git a/tools/unit-test-app/configs/release_c3 b/tools/unit-test-app/configs/release_c3 index 02f2966b79..ec65721ad4 100644 --- a/tools/unit-test-app/configs/release_c3 +++ b/tools/unit-test-app/configs/release_c3 @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32c3" -TEST_COMPONENTS=esp_hw_support esp_ipc esp_system driver +TEST_COMPONENTS=esp_system driver CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y diff --git a/tools/unit-test-app/configs/release_s2 b/tools/unit-test-app/configs/release_s2 index c52a30206b..5daf84c4e7 100644 --- a/tools/unit-test-app/configs/release_s2 +++ b/tools/unit-test-app/configs/release_s2 @@ -1,6 +1,6 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_COMPONENTS=esp_hw_support esp_system driver soc spi_flash vfs +TEST_COMPONENTS=esp_system driver soc spi_flash vfs CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/tools/unit-test-app/configs/release_s3 b/tools/unit-test-app/configs/release_s3 index 7e9b09464f..5ea7a6b1fc 100644 --- a/tools/unit-test-app/configs/release_s3 +++ b/tools/unit-test-app/configs/release_s3 @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32s3" -TEST_COMPONENTS=esp_hw_support esp_system esp_ipc driver soc spi_flash vfs +TEST_COMPONENTS=esp_system driver soc spi_flash vfs CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/tools/unit-test-app/configs/single_core b/tools/unit-test-app/configs/single_core index 49b1c3d18e..70e2c4e849 100644 --- a/tools/unit-test-app/configs/single_core +++ b/tools/unit-test-app/configs/single_core @@ -1,6 +1,6 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=esp_hw_support esp_system driver soc spi_flash vfs +TEST_COMPONENTS=esp_system driver soc spi_flash vfs CONFIG_FREERTOS_UNICORE=y CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY=y CONFIG_ESP32_RTCDATA_IN_FAST_MEM=y diff --git a/tools/unit-test-app/configs/single_core_2 b/tools/unit-test-app/configs/single_core_2 index f4fdf6931b..86d91baf86 100644 --- a/tools/unit-test-app/configs/single_core_2 +++ b/tools/unit-test-app/configs/single_core_2 @@ -1,5 +1,5 @@ # This config is split between targets since different component needs to be excluded (esp32, esp32s2) CONFIG_IDF_TARGET="esp32" -TEST_EXCLUDE_COMPONENTS=bt esp_hw_support esp_system esp_pm esp_ipc driver soc spi_flash vfs test_utils experimental_cpp_component +TEST_EXCLUDE_COMPONENTS=bt esp_system esp_pm driver soc spi_flash vfs test_utils experimental_cpp_component CONFIG_FREERTOS_UNICORE=y CONFIG_ESP32_RTCDATA_IN_FAST_MEM=y diff --git a/tools/unit-test-app/configs/single_core_2_s2 b/tools/unit-test-app/configs/single_core_2_s2 index 5e33f6d3f0..bf26adbb94 100644 --- a/tools/unit-test-app/configs/single_core_2_s2 +++ b/tools/unit-test-app/configs/single_core_2_s2 @@ -1,5 +1,5 @@ # This config is split between targets since different component needs to be excluded (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_EXCLUDE_COMPONENTS=bt esp_hw_support esp_ipc esp_system esp_pm driver soc spi_flash vfs experimental_cpp_component +TEST_EXCLUDE_COMPONENTS=bt esp_system esp_pm driver soc spi_flash vfs experimental_cpp_component CONFIG_FREERTOS_UNICORE=y CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM=y diff --git a/tools/unit-test-app/configs/single_core_s2 b/tools/unit-test-app/configs/single_core_s2 index 2db9f1bbae..576440506e 100644 --- a/tools/unit-test-app/configs/single_core_s2 +++ b/tools/unit-test-app/configs/single_core_s2 @@ -1,4 +1,4 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_COMPONENTS=esp_hw_support esp_system driver soc spi_flash test_utils +TEST_COMPONENTS=esp_system driver soc spi_flash test_utils CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM=y diff --git a/tools/unit-test-app/disabled_configs/psram_2_s2 b/tools/unit-test-app/disabled_configs/psram_2_s2 index d61a7e9abe..5c88bf7f6b 100644 --- a/tools/unit-test-app/disabled_configs/psram_2_s2 +++ b/tools/unit-test-app/disabled_configs/psram_2_s2 @@ -1,4 +1,4 @@ -TEST_COMPONENTS=driver esp_hw_support spi_flash mbedtls +TEST_COMPONENTS=driver spi_flash mbedtls CONFIG_SPIRAM=y CONFIG_IDF_TARGET="esp32s2" CONFIG_SPIRAM_OCCUPY_NO_HOST=y diff --git a/tools/unit-test-app/disabled_configs/psram_8m_s2 b/tools/unit-test-app/disabled_configs/psram_8m_s2 deleted file mode 100644 index dfb70c7e5b..0000000000 --- a/tools/unit-test-app/disabled_configs/psram_8m_s2 +++ /dev/null @@ -1,6 +0,0 @@ -TEST_COMPONENTS=esp_hw_support -CONFIG_SPIRAM=y -CONFIG_SPIRAM_BANKSWITCH_ENABLE=y -CONFIG_SPIRAM_BANKSWITCH_RESERVE=8 -CONFIG_IDF_TARGET="esp32s2" -CONFIG_SPIRAM_OCCUPY_NO_HOST=y diff --git a/tools/unit-test-app/disabled_configs/psram_s2 b/tools/unit-test-app/disabled_configs/psram_s2 index c89ef65f89..d513ad3b83 100644 --- a/tools/unit-test-app/disabled_configs/psram_s2 +++ b/tools/unit-test-app/disabled_configs/psram_s2 @@ -1,4 +1,4 @@ -TEST_EXCLUDE_COMPONENTS=libsodium bt app_update driver esp_hw_support spi_flash +TEST_EXCLUDE_COMPONENTS=libsodium bt app_update driver spi_flash CONFIG_SPIRAM=y CONFIG_IDF_TARGET="esp32s2" CONFIG_SPIRAM_OCCUPY_NO_HOST=y