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feat(esp_hw_support): add esp32p4 pau initial support

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This commit is contained in:
wuzhenghui 2024-02-06 10:49:33 +08:00
parent acd263d006
commit 5d24a818eb
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GPG Key ID: 3EFEDECDEBA39BB9
16 changed files with 306 additions and 20 deletions
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15
components/esp_hw_support/port/esp32p4/pmu_sleep.c
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@ -20,7 +20,9 @@
#include "soc/pmu_reg.h"
#include "soc/pmu_struct.h"
#include "hal/lp_aon_hal.h"
#include "soc/lp_system_reg.h"
#include "hal/pmu_hal.h"
#include "hal/lp_sys_ll.h"
#include "esp_private/esp_pmu.h"
#include "pmu_param.h"
#include "esp_rom_sys.h"
@ -237,6 +239,19 @@ void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp)
}
pmu_sleep_analog_init(PMU_instance(), &config->analog, dslp);
pmu_sleep_param_init(PMU_instance(), &config->param, dslp);
// When light sleep (PD_TOP), the PAU will power down. so need use LP_SYS_BACKUP_DMA_CFG2_REG to store recover link address.
if (!dslp && PMU.hp_sys[PMU_MODE_HP_SLEEP].dig_power.top_pd_en) {
if (PMU.hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en ||
PMU.hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en) {
uint32_t link_sel = PMU.hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_mode & 0x3;
uint32_t link_addr = REG_READ(PAU_REGDMA_LINK_0_ADDR_REG + link_sel * 4);
lp_sys_ll_set_pau_link_addr(link_addr);
pmu_sleep_enable_regdma_backup();
}
} else {
pmu_sleep_disable_regdma_backup();
}
}
void pmu_sleep_increase_ldo_volt(void) {

7
components/esp_hw_support/port/pau_regdma.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,7 +11,7 @@
#include "esp_attr.h"
#include "esp_log.h"
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#include "soc/soc_caps.h"
#include "esp_private/esp_pau.h"
#include "esp_private/periph_ctrl.h"
@ -32,6 +32,9 @@ pau_context_t * __attribute__((weak)) IRAM_ATTR PAU_instance(void)
if (pau_hal.dev == NULL) {
pau_hal.dev = &PAU;
periph_module_enable(PERIPH_REGDMA_MODULE);
#if SOC_PAU_IN_TOP_DOMAIN
pau_hal_lp_sys_initialize();
#endif
}
return &pau_context;

3
components/esp_hw_support/port/regdma_link.c
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@ -531,18 +531,21 @@ static void regdma_link_update_continuous_next_wrapper(void *link, void *next)
{
regdma_link_continuous_t *continuous = __containerof(link, regdma_link_continuous_t, head);
continuous->body.next = next;
continuous->head.eof = !next;
}
static void regdma_link_update_addr_map_next_wrapper(void *link, void *next)
{
regdma_link_addr_map_t *addr_map = __containerof(link, regdma_link_addr_map_t, head);
addr_map->body.next = next;
addr_map->head.eof = !next;
}
static void regdma_link_update_write_wait_next_wrapper(void *link, void *next)
{
regdma_link_write_wait_t *write_wait = __containerof(link, regdma_link_write_wait_t, head);
write_wait->body.next = next;
write_wait->head.eof = !next;
}
static void regdma_link_update_branch_continuous_next_wrapper(void *link, regdma_entry_buf_t *next)

9
components/hal/esp32c6/include/hal/pau_ll.h
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@ -130,14 +130,9 @@ static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev)
dev->int_ena.done_int_ena = 0;
}
static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev)
static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable)
{
dev->int_ena.error_int_ena = 1;
}
static inline void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev)
{
dev->int_ena.error_int_ena = 0;
dev->int_ena.error_int_ena = enable;
}
static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev)

9
components/hal/esp32h2/include/hal/pau_ll.h
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@ -100,14 +100,9 @@ static inline __attribute__((always_inline)) void pau_ll_set_regdma_backup_done_
dev->int_ena.done_int_ena = 0;
}
static inline __attribute__((always_inline)) void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev)
static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable)
{
dev->int_ena.error_int_ena = 1;
}
static inline __attribute__((always_inline)) void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev)
{
dev->int_ena.error_int_ena = 0;
dev->int_ena.error_int_ena = enable;
}
static inline __attribute__((always_inline)) void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev)

8
components/hal/esp32p4/include/hal/clk_gate_ll.h
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@ -47,6 +47,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN;
case PERIPH_ISP_MODULE:
return HP_SYS_CLKRST_REG_ISP_CLK_EN;
case PERIPH_REGDMA_MODULE:
return HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN;
default:
return 0;
}
@ -103,6 +105,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return HP_SYS_CLKRST_REG_RST_EN_ECDSA;
case PERIPH_EMAC_MODULE:
return LP_CLKRST_RST_EN_EMAC;
case PERIPH_REGDMA_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_REGDMA;
default:
return 0;
}
@ -128,6 +132,8 @@ static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
return HP_SYS_CLKRST_PERI_CLK_CTRL25_REG;
case PERIPH_EMAC_MODULE:
return LP_CLKRST_HP_CLK_CTRL_REG;
case PERIPH_REGDMA_MODULE:
return HP_SYS_CLKRST_SOC_CLK_CTRL0_REG;
default:
abort();
return 0;
@ -154,6 +160,8 @@ static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
return HP_SYS_CLKRST_HP_RST_EN2_REG;
case PERIPH_EMAC_MODULE:
return LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG;
case PERIPH_REGDMA_MODULE:
return HP_SYS_CLKRST_HP_RST_EN0_REG;
default:
abort();
return 0;

25
components/hal/esp32p4/include/hal/lp_sys_ll.h
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@ -34,6 +34,31 @@ static inline void lp_sys_ll_inform_wakeup_type(bool dslp)
}
}
static inline void lp_sys_ll_set_pau_aon_bypass(bool bypass)
{
LP_SYS.backup_dma_cfg1.aon_bypass = bypass ? 1 : 0;
}
static inline void lp_sys_ll_set_pau_link_tout_thres(uint32_t tout)
{
LP_SYS.backup_dma_cfg0.link_tout_thres_aon = tout;
}
static inline void lp_sys_ll_set_pau_link_backup_tout_thres(uint32_t tout)
{
LP_SYS.backup_dma_cfg0.link_backup_tout_thres_aon = tout;
}
static inline void lp_sys_ll_set_pau_reg_read_interval(uint32_t val)
{
LP_SYS.backup_dma_cfg0.read_interval_aon = val;
}
static inline void lp_sys_ll_set_pau_link_addr(uint32_t addr)
{
LP_SYS.backup_dma_cfg2.link_addr_aon = addr;
}
#ifdef __cplusplus
}
#endif

150
components/hal/esp32p4/include/hal/pau_ll.h Normal file
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@ -0,0 +1,150 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-C6 PAU(Power Assist Unit) register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/pau_reg.h"
#include "soc/pau_struct.h"
#include "hal/pau_types.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev)
{
return dev->regdma_conf.flow_err;
}
static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link)
{
dev->regdma_conf.link_sel = link;
}
static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem)
{
dev->regdma_conf.to_mem = to_mem ? 1 : 0;
}
static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev)
{
dev->regdma_conf.start = 1;
}
static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev)
{
dev->regdma_conf.start = 0;
}
static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev)
{
dev->regdma_conf.sel_mac = 1;
}
static inline void pau_ll_set_regdma_deselect_wifimac_link(pau_dev_t *dev)
{
dev->regdma_conf.sel_mac = 0;
}
static inline void pau_ll_set_regdma_wifimac_link_backup_direction(pau_dev_t *dev, bool to_mem)
{
dev->regdma_conf.to_mem_mac = to_mem ? 1 : 0;
}
static inline void pau_ll_set_regdma_wifimac_link_backup_start_enable(pau_dev_t *dev)
{
dev->regdma_conf.start_mac = 1;
}
static inline void pau_ll_set_regdma_wifimac_link_backup_start_disable(pau_dev_t *dev)
{
dev->regdma_conf.start_mac = 0;
}
static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr)
{
dev->regdma_link_0_addr.val = (uint32_t)link_addr;
}
static inline void pau_ll_set_regdma_link1_addr(pau_dev_t *dev, void *link_addr)
{
dev->regdma_link_1_addr.val = (uint32_t)link_addr;
}
static inline void pau_ll_set_regdma_link2_addr(pau_dev_t *dev, void *link_addr)
{
dev->regdma_link_2_addr.val = (uint32_t)link_addr;
}
static inline void pau_ll_set_regdma_link3_addr(pau_dev_t *dev, void *link_addr)
{
dev->regdma_link_3_addr.val = (uint32_t)link_addr;
}
static inline void pau_ll_set_regdma_wifimac_link_addr(pau_dev_t *dev, void *link_addr)
{
dev->regdma_link_mac_addr.val = (uint32_t)link_addr;
}
static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev)
{
return dev->regdma_current_link_addr.val;
}
static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev)
{
return dev->regdma_backup_addr.val;
}
static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev)
{
return dev->regdma_mem_addr.val;
}
static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev)
{
return dev->int_raw.val;
}
static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev)
{
return dev->int_st.val;
}
static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev)
{
dev->int_ena.done_int_ena = 1;
}
static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev)
{
dev->int_ena.done_int_ena = 0;
}
static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable)
{
dev->int_ena.error_int_ena = enable;
}
static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev)
{
dev->int_clr.done_int_clr = 1;
}
static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
{
dev->int_clr.error_int_clr = 1;
}
#ifdef __cplusplus
}
#endif

72
components/hal/esp32p4/pau_hal.c Normal file
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@ -0,0 +1,72 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The HAL layer for PAU (ESP32-C6 specific part)
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "esp_attr.h"
#include "hal/pau_hal.h"
#include "hal/pau_types.h"
#if SOC_PAU_IN_TOP_DOMAIN
#include "hal/lp_sys_ll.h"
#endif
void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr)
{
pau_ll_set_regdma_link0_addr(hal->dev, (*link_addr)[0]);
pau_ll_set_regdma_link1_addr(hal->dev, (*link_addr)[1]);
pau_ll_set_regdma_link2_addr(hal->dev, (*link_addr)[2]);
/* The link 3 of REGDMA is reserved, PMU state switching will not use
* REGDMA link 3 */
}
void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore)
{
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
pau_ll_set_regdma_select_wifimac_link(hal->dev);
pau_ll_set_regdma_wifimac_link_backup_direction(hal->dev, backup_or_restore);
pau_ll_set_regdma_wifimac_link_backup_start_enable(hal->dev);
while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
}
void IRAM_ATTR pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal)
{
pau_ll_set_regdma_wifimac_link_backup_start_disable(hal->dev);
pau_ll_set_regdma_deselect_wifimac_link(hal->dev);
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
}
void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore)
{
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
/* The link 3 of REGDMA is reserved, we use it as an extra linked list to
* provide backup and restore services for BLE, IEEE802.15.4 and possibly
* other modules */
pau_ll_select_regdma_entry_link(hal->dev, 3);
pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore);
pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev);
while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
}
void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
{
pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev);
pau_ll_select_regdma_entry_link(hal->dev, 3); /* restore link select to default */
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
}
#if SOC_PAU_IN_TOP_DOMAIN
void IRAM_ATTR pau_hal_lp_sys_initialize(void)
{
lp_sys_ll_set_pau_aon_bypass(true);
lp_sys_ll_set_pau_link_backup_tout_thres(300);
lp_sys_ll_set_pau_link_tout_thres(200);
lp_sys_ll_set_pau_reg_read_interval(50);
}
#endif

11
components/hal/include/hal/pau_hal.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -111,6 +111,15 @@ void pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal);
void pau_hal_regdma_clock_configure(pau_hal_context_t *hal, bool enable);
#endif
#if SOC_PAU_IN_TOP_DOMAIN
/**
* If PAU is in TOP power domain, configuration will be lost after sleep, it is necessary
* to use LP_SYS_BACKUP_DMA_CFG2_REG to override restore link address, do related logic
* initialization by this function.
*/
void pau_hal_lp_sys_initialize(void);
#endif
#endif
#ifdef __cplusplus

8
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@ -187,6 +187,10 @@ config SOC_DCDC_SUPPORTED
bool
default y
config SOC_PAU_SUPPORTED
bool
default y
config SOC_LP_TIMER_SUPPORTED
bool
default y
@ -1443,6 +1447,10 @@ config SOC_PM_PAU_LINK_NUM
int
default 4
config SOC_PAU_IN_TOP_DOMAIN
bool
default y
config SOC_PSRAM_VDD_POWER_MPLL
bool
default y

1
components/soc/esp32p4/include/soc/pau_struct.h
View File

@ -328,6 +328,7 @@ typedef struct {
volatile pau_date_reg_t date;
} pau_dev_t;
extern pau_dev_t PAU;
#ifndef __cplusplus
_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure");

1
components/soc/esp32p4/include/soc/periph_defs.h
View File

@ -69,6 +69,7 @@ typedef enum {
PERIPH_UHCI_MODULE,
PERIPH_PCNT_MODULE,
PERIPH_ASSIST_DEBUG_MODULE,
PERIPH_REGDMA_MODULE,
/* LP peripherals */
PERIPH_LP_I2C0_MODULE,
PERIPH_LP_UART0_MODULE,

3
components/soc/esp32p4/include/soc/reg_base.h
View File

@ -201,8 +201,7 @@
// #define DR_REG_LP_TEE_BASE 0x600B3400
// #define DR_REG_LP_APM_BASE 0x600B3800
//TODO: IDF-7531
// #define DR_REG_PAU_BASE 0x60093000
#define DR_REG_PAU_BASE DR_REG_REGDMA_BASE
//TODO: IDF-7688
// #define DR_REG_TRACE_BASE 0x600C0000

3
components/soc/esp32p4/include/soc/soc_caps.h
View File

@ -70,7 +70,7 @@
// #define SOC_APM_SUPPORTED 1 //TODO: IDF-7542
#define SOC_PMU_SUPPORTED 1
#define SOC_DCDC_SUPPORTED 1
// #define SOC_PAU_SUPPORTED 1 //TODO: IDF-7531
#define SOC_PAU_SUPPORTED 1 //TODO: IDF-7531
#define SOC_LP_TIMER_SUPPORTED 1
#define SOC_ULP_LP_UART_SUPPORTED 1
#define SOC_LP_GPIO_MATRIX_SUPPORTED 1
@ -589,6 +589,7 @@
#define SOC_PM_CPU_RETENTION_BY_SW (1)
#define SOC_PM_PAU_LINK_NUM (4)
#define SOC_PAU_IN_TOP_DOMAIN (1)
/*-------------------------- PSRAM CAPS ----------------------------*/
#define SOC_PSRAM_VDD_POWER_MPLL (1)

1
components/soc/esp32p4/ld/esp32p4.peripherals.ld
View File

@ -96,6 +96,7 @@ PROVIDE ( MIPI_CSI_MEM = 0x50104000 );
PROVIDE ( MIPI_DSI_MEM = 0x50105000 );
PROVIDE ( ISP = 0x500A1000 );
PROVIDE ( DW_GDMA = 0x50081000 );
PROVIDE ( PAU = 0x50082000 );
PROVIDE ( I3C_MST = 0x500DA000 );
PROVIDE ( I3C_MST_MEM = 0x500DA000 );
PROVIDE ( I3C_SLV = 0x500DB000 );